JPH0917936A - Lead frame for semiconductor device and its manufacturing method - Google Patents
Lead frame for semiconductor device and its manufacturing methodInfo
- Publication number
- JPH0917936A JPH0917936A JP7163495A JP16349595A JPH0917936A JP H0917936 A JPH0917936 A JP H0917936A JP 7163495 A JP7163495 A JP 7163495A JP 16349595 A JP16349595 A JP 16349595A JP H0917936 A JPH0917936 A JP H0917936A
- Authority
- JP
- Japan
- Prior art keywords
- lead frame
- adhesive
- semiconductor element
- semiconductor device
- filler
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/4826—Connecting between the body and an opposite side of the item with respect to the body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73215—Layer and wire connectors
Landscapes
- Die Bonding (AREA)
- Lead Frames For Integrated Circuits (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は、リードフレームに半導
体素子を接合する接着技術を改善した半導体装置用リー
ドフレーム及びその製造方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a lead frame for a semiconductor device and a method for manufacturing the same, which has an improved bonding technique for joining a semiconductor element to a lead frame.
【０００２】[0002]
【従来の技術】リードフレームに半導体素子を搭載する
方法として、図４、図５に示すように、リードフレーム
２の半導体素子３が搭載されるべき場所（半導体素子搭
載予定領域）に、両面に接着剤１５ａ、１５ｂを塗布し
たポリイミドテープ１５を予め接着しておき、その接着
剤付きテープ１５を利用して半導体素子３をリードフレ
ーム２に接合する方法があり、ＣＯＬ (Chip on Lead)
、ＬＯＣ (Lead on Chip) は、その代表例である。2. Description of the Related Art As a method of mounting a semiconductor element on a lead frame, as shown in FIGS. 4 and 5, at a place where a semiconductor element 3 of a lead frame 2 is to be mounted (semiconductor element mounting area), both surfaces are mounted. There is a method in which the polyimide tape 15 coated with the adhesives 15a and 15b is adhered in advance and the semiconductor element 3 is bonded to the lead frame 2 by using the adhesive-attached tape 15, and COL (Chip on Lead) is used.
, LOC (Lead on Chip) is a typical example.
【０００３】リードフレーム２へのテープ１５の接着方
法としては、接着剤付きテープ１５を所定の形状に打抜
き、その打抜かれたテープ１５をリードフレーム２の半
導体素子搭載予定領域へ貼合わせる方法が一般的であ
る。この方法は、テープを打抜いて使用するためテープ
の使用量が多くなり、コストアップにつながるという欠
点がある。また、ポリイミドテープの吸湿のためにパッ
ケージ実装する際のリフロー工程で、パッケージクラッ
クが発生する危険性がある。As a method of adhering the tape 15 to the lead frame 2, a method is generally used in which the adhesive-attached tape 15 is punched into a predetermined shape, and the punched tape 15 is attached to the area where the semiconductor element is to be mounted on the lead frame 2. Target. This method has a drawback that the amount of tape used increases because the tape is punched out before use, leading to an increase in cost. In addition, there is a risk that package cracks may occur in the reflow process when the package is mounted due to moisture absorption of the polyimide tape.
【０００４】このような欠点を解消するために、リード
フレームの半導体素子搭載予定領域に接着剤を滴下し、
その接着剤で半導体素子とリードフレームとを接合する
方法が提案されている（たとえば特開平４−７５３５５
号公報）。しかし、この方法では、接着剤の塗布厚さが
十分に厚くできず、半導体素子とリードフレームとの絶
縁が不十分となる可能性がある。In order to eliminate such drawbacks, an adhesive is dropped on a region of the lead frame where the semiconductor element is to be mounted,
A method of joining the semiconductor element and the lead frame with the adhesive has been proposed (for example, JP-A-4-75355).
No.). However, with this method, the coating thickness of the adhesive cannot be made sufficiently thick, and the insulation between the semiconductor element and the lead frame may be insufficient.
【０００５】絶縁厚さを十分に取るためには、(1) 接着
剤の粘度を高くしてリード上の接着剤塗布量を多くする
方法、(2) フィラー入りの接着剤を使用し、フィラーに
よって絶縁厚さを確保する方法（たとえば特開平５−２
１８１１１号公報）が考えられる。In order to obtain a sufficient insulation thickness, (1) a method of increasing the viscosity of the adhesive to increase the amount of adhesive applied on the leads, (2) using an adhesive containing a filler, A method for ensuring an insulation thickness by means of the method (for example, Japanese Patent Laid-Open No. 5-2
18111).
【０００６】[0006]
【発明が解決しようとする課題】しかし、(1) の方法に
ついては、接着剤の粘度を高くすることによって、接着
剤のリードフレーム上への塗布が困難になる欠点があ
る。(2) の方法については、絶縁厚さの確保は可能であ
るが、フィラーの存在のために半導体素子を接合する際
の接着力が低下する欠点をもつ。However, the method (1) has a drawback that it becomes difficult to apply the adhesive to the lead frame by increasing the viscosity of the adhesive. Regarding the method (2), it is possible to secure the insulation thickness, but there is a drawback that the adhesive force at the time of joining the semiconductor elements is lowered due to the presence of the filler.
【０００７】本発明の目的は、上記した従来技術の欠点
を解消し、絶縁厚さを十分に確保でき、かつ半導体素子
との接着力の高い接着剤をもった半導体装置用リードフ
レームを提供することにある。また、本発明の目的は、
接着剤を簡単に塗布することが可能な半導体装置用リー
ドフレームの製造方法を提供することにある。An object of the present invention is to solve the above-mentioned drawbacks of the prior art, and to provide a lead frame for a semiconductor device, which has an adhesive having a sufficient insulation thickness and a high adhesive strength with a semiconductor element. Especially. The object of the present invention is
An object of the present invention is to provide a method of manufacturing a lead frame for a semiconductor device, which can easily apply an adhesive.
【０００８】[0008]
【課題を解決するための手段】本発明のリードフレーム
は、リードフレームの半導体素子搭載予定領域に絶縁性
高温軟化型接着剤を介在して半導体素子を接合した半導
体装置用リードフレームにおいて、絶縁性高温軟化型接
着剤を２層構造とし、リードフレーム側に絶縁性のフィ
ラーを含んだ接着剤を介在させ、半導体素子側にフィラ
ーを含まない接着剤を介在させたものである。この場
合、絶縁性高温軟化型接着剤に含まれる絶縁性フィラー
としては、ＳｉＯ2 、ＡｌＮ、ＳｉＣなどがよく、特に
安価で入手しやすく、粒度のそろった粒子が得やすいと
いう理由から、ＳｉＯ2 が好ましい。The lead frame of the present invention is a lead frame for a semiconductor device in which a semiconductor element is bonded to a semiconductor element mounting region of the lead frame with an insulating high temperature softening type adhesive interposed therebetween. A high temperature softening type adhesive has a two-layer structure, an adhesive containing an insulating filler is interposed on the lead frame side, and an adhesive containing no filler is interposed on the semiconductor element side. In this case, as the insulating filler contained in the insulating high temperature softening type adhesive, for the reason that SiO 2, AlN, SiC, etc. well, especially inexpensive readily available, uniform particles are easily obtained particle size, SiO 2 Is preferred.
【０００９】本発明のリードフレームの製造方法は、リ
ードフレームの半導体素子搭載予定領域に絶縁性高温軟
化型接着剤を直接塗布し、この塗布した接着剤の上に半
導体素子を載せて接合する半導体装置用リードフレーム
の製造方法において、絶縁性高温軟化型接着剤をパッド
印刷法で塗布するようにし、最初に絶縁性のフィラーを
含んだ接着剤を塗布、乾燥し、次にフィラーを含まない
接着剤を塗布、乾燥したものである。According to the method for manufacturing a lead frame of the present invention, the insulating high temperature softening type adhesive is directly applied to the area where the semiconductor element is to be mounted on the lead frame, and the semiconductor element is placed on and bonded to the applied adhesive. In the manufacturing method of the lead frame for the device, the insulating high temperature softening type adhesive is applied by the pad printing method, first the adhesive containing the insulating filler is applied and dried, and then the adhesive containing no filler is applied. The agent is applied and dried.
【００１０】この場合、パッド印刷法に代えてディスペ
ンサ法で塗布するようにしてもよい。また、絶縁性高温
軟化型接着剤がポリイミド、ポリエーテルアミドあるい
はポリエーテルアミドイミドからなる熱可塑性接着剤、
またはこれらの組合わせからなる接着剤を用いるとよ
い。In this case, the dispenser method may be applied instead of the pad printing method. Further, the insulating high temperature softening adhesive is a thermoplastic adhesive made of polyimide, polyether amide or polyether amide imide,
Alternatively, an adhesive composed of a combination of these may be used.
【００１１】[0011]
【作用】本発明のリードフレームのように半導体素子は
フィラーを含まない接着剤と接合されるため十分な接着
力をもち、かつその接着剤とリードフレームの間にはフ
ィラーを含んだ接着剤が存在するために絶縁厚さの確保
ができる。フィラーをＳｉＯ2 とした場合には、半導体
素子を接着する際の加熱、加圧によってもＳｉＯ2 はつ
ぶれることがないため、ので、絶縁厚さを十分に確保す
ることができる。The semiconductor element, like the lead frame of the present invention, has sufficient adhesive strength because it is bonded to the adhesive containing no filler, and the adhesive containing the filler does not exist between the adhesive and the lead frame. Since it exists, the insulation thickness can be secured. When the filler and SiO 2, since it never SiO 2 collapses by heating, pressing at the time of bonding the semiconductor device, so it is possible to sufficiently secure the insulation thickness.
【００１２】また本発明のリードフレームの製造方法の
ように、接着剤をパッド印刷法で塗布する場合には転写
するだけで塗布が行えるので、塗布に時間を要さない。
またディスペンサ法で塗布する場合には接着剤の厚みの
制御が容易である。When the adhesive is applied by the pad printing method as in the lead frame manufacturing method of the present invention, the application can be performed only by transferring, so that the application does not take time.
Further, when applying by the dispenser method, it is easy to control the thickness of the adhesive.
【００１３】絶縁性高温軟化型接着剤をポリイミド、ポ
リエーテルアミドあるいはポリエーテルアミドイミドか
らなる熱可塑性接着剤、またはこれらの組合わせとした
場合には、比較的低温で塗布することができるので、リ
ードフレーム材表面が酸化することがない。When the insulating high temperature softening type adhesive is a thermoplastic adhesive made of polyimide, polyether amide or polyether amide imide, or a combination thereof, it can be applied at a relatively low temperature. The surface of the lead frame material is not oxidized.
【００１４】[0014]
（実施例）以下に、本発明の一実施例を添付図面を用い
て説明する。図１は本発明の一実施例であるリードフレ
ームを用いて構成された半導体装置の断面図、図２はそ
のリードフレームの部分的拡大平面図、図３はその要部
拡大斜視図である。(Embodiment) An embodiment of the present invention will be described below with reference to the accompanying drawings. FIG. 1 is a sectional view of a semiconductor device constructed by using a lead frame which is an embodiment of the present invention, FIG. 2 is a partially enlarged plan view of the lead frame, and FIG. 3 is an enlarged perspective view of a main part thereof.
【００１５】図１において、１は半導体装置で、この半
導体装置１はタブを持たないリードフレーム２を用いて
構成されている。このリードフレーム２は、半導体素子
３を固定してモールド成型により樹脂封入されるインナ
ーリード５と、パッケージ４の外に延出されるアウター
リード６とから主に構成されている。なお、リードフレ
ーム２は図２に示すように枠７に一体形成されている
が、半導体素子３を固定等した後に、対のインナーリー
ド５及びアウターリード６ごとに枠７から切り離され
る。また、この場合のリードフレーム２は、厚さが０．
１２５ｍｍで４２Ｎｉ−Ｆｅ合金製の２４ピンＴＳＯＰ
（Thin Small Outline Package）用に構成されている。In FIG. 1, reference numeral 1 denotes a semiconductor device, which is composed of a lead frame 2 having no tab. The lead frame 2 is mainly composed of an inner lead 5 that fixes the semiconductor element 3 and is encapsulated with resin by molding, and an outer lead 6 that extends out of the package 4. Although the lead frame 2 is integrally formed with the frame 7 as shown in FIG. 2, after the semiconductor element 3 is fixed, the lead frame 2 is separated from the frame 7 for each pair of inner lead 5 and outer lead 6. The lead frame 2 in this case has a thickness of 0.
24-pin TSOP made of 42Ni-Fe alloy with 125mm
It is configured for (Thin Small Outline Package).
【００１６】そして上記リードフレーム２のインナーリ
ード５における半導体素子搭載予定領域２ａには、図３
に示すように、絶縁性を有する２層の接着剤８ａ、８ｂ
が形成されている。そのうちのインナーリード５に近い
層、すなわちインナーリード５と接する接着剤１８ａ
は、ＳｉＯ2 を主成分とするフィラーを含んだ熱可塑性
ポリエーテルアミドイミドによって厚さ２０μｍ程度に
形成され、インナーリード５から遠い層、すなわち半導
体素子３と接する接着剤８ｂは、フィラーを含まない熱
可塑性ポリエーテルアミドイミドによって厚さ１０μｍ
程度に形成されている。なお、ＳｉＯ2 は、形状として
は球状が好ましく、その大きさは直径５μｍ以下、より
好ましくは３μｍ以下で、均一に含ませるとよい。In the semiconductor element mounting area 2a of the inner lead 5 of the lead frame 2 shown in FIG.
As shown in FIG. 2, two-layer adhesives 8a and 8b having an insulating property are provided.
Are formed. A layer close to the inner leads 5, that is, an adhesive 18a that contacts the inner leads 5
Is formed of thermoplastic polyether amide imide containing SiO 2 as a main component to a thickness of about 20 μm, and the layer far from the inner lead 5, that is, the adhesive 8b in contact with the semiconductor element 3 does not contain a filler. 10 μm thick due to thermoplastic polyether amide imide
It is formed to a degree. The shape of SiO 2 is preferably spherical, and the size thereof is 5 μm or less in diameter, more preferably 3 μm or less, and it is preferable that SiO 2 be uniformly contained.
【００１７】このように構成されたリードフレーム２の
インナーリード５に半導体素子３を接合する場合には、
その接着剤８ａ、８ｂを比較的温度の低い２４０〜２７
０℃に加熱し、その接着剤８ａ、８ｂに半導体素子３を
押し付ければよい。これにより接着剤８ｂは溶融して半
導体素子３に強固に接着する。接着剤８ａも一部溶融す
るが、フィラーの存在のためにその厚さが著しく減少す
ることなく、十分な絶縁距離を確保することができる。When the semiconductor element 3 is joined to the inner lead 5 of the lead frame 2 thus constructed,
If the adhesives 8a and 8b are used in a relatively low temperature range of 240 to 27
The semiconductor element 3 may be pressed to the adhesives 8a and 8b by heating to 0 ° C. As a result, the adhesive 8b is melted and firmly adhered to the semiconductor element 3. Although the adhesive 8a also partially melts, the thickness of the adhesive 8a does not significantly decrease due to the presence of the filler, and a sufficient insulation distance can be secured.
【００１８】上記接着剤８ａ、８ｂを塗布形成する方法
として、パッド印刷法やディスペンサ法が用いられる。
パッド印刷法は、ウレタンゴム製のパッドに所定形状及
び所定厚さの接着剤を付着させ、これをインナーリード
に転写する方法である。この場合、接着剤は溶剤で溶か
してワニス状にし、転写部よりも１０〜５０℃高くした
溜め部に収容しておくとよい。また、樹脂を１層塗布す
るごとに、１００〜２５０℃で０．５〜２分の乾燥を行
うことにより２層の接着剤を形成することができる。な
お、２層を連続して塗布し、乾燥を１度で済ませる場合
には、２層の境界で若干の樹脂の混合を生じるが、実用
上問題はない。ディスペンサ法は、空気圧によりニード
ルを通して塗布量をコントロールしながらワニス状の樹
脂をインナーリードに直接塗布する方法である。この方
法は、塗布に時間を有するが、接着剤の厚みの制御が容
易である。As a method of applying and forming the adhesives 8a and 8b, a pad printing method or a dispenser method is used.
The pad printing method is a method in which an adhesive having a predetermined shape and a predetermined thickness is attached to a urethane rubber pad, and the adhesive is transferred to the inner lead. In this case, the adhesive may be dissolved in a solvent to form a varnish, and the adhesive may be stored in a reservoir portion that is 10 to 50 ° C. higher than the transfer portion. Also, every time one layer of the resin is applied, drying is performed at 100 to 250 ° C. for 0.5 to 2 minutes to form a two-layer adhesive. When two layers are continuously coated and dried once, some resin mixing occurs at the boundary between the two layers, but there is no practical problem. The dispenser method is a method of directly applying a varnish-like resin to the inner leads while controlling the application amount through a needle by air pressure. This method takes time to apply, but it is easy to control the thickness of the adhesive.
【００１９】このように構成されたリードフレーム２に
よれば、インナーリード５に半導体素子３を接合するた
めの接着剤が、インナーリード５の半導体素子搭載予定
領域２ａに、絶縁性を有し、接着性の高い接着剤８ｂと
フィラーを含む接着剤８ａを層状に塗布するだけで簡単
に形成され、絶縁性フィルムと比べて、加工が容易で製
造コストがかからない。また、接着剤８ａ、８ｂは薄
く、しかも並設された複数のインナーリード５全体に跨
ることなく最少体積で形成できるため、吸湿量が少な
く、半田リフロー時の加熱等によるパッケージクラック
が生じ難くなり、耐久性が向上する。また、インナーリ
ード５に接着剤８ａ、８ｂを比較的低温で形成すること
ができるので、リードフレーム２材表面が酸化する問題
がなくなる。According to the lead frame 2 thus constructed, the adhesive for bonding the semiconductor element 3 to the inner lead 5 has an insulating property in the semiconductor element mounting region 2a of the inner lead 5, The adhesive 8b having high adhesiveness and the adhesive 8a containing a filler are simply applied to form a layer, and are easily formed, and are easier to process and less costly to manufacture than an insulating film. In addition, since the adhesives 8a and 8b are thin and can be formed in a minimum volume without straddling the entire inner leads 5 arranged in parallel, the amount of moisture absorption is small, and package cracks due to heating during solder reflow are less likely to occur. , Durability is improved. Further, since the adhesives 8a and 8b can be formed on the inner lead 5 at a relatively low temperature, there is no problem of the surface of the lead frame 2 material being oxidized.
【００２０】上記リードフレーム２のインナーリード５
には図１に示すように接着剤８ａ、８ｂを介して半導体
素子３が接合され、半導体素子３の電極端子９とインナ
ーリード５との間がボンディングワイヤ１０によって結
線された後、樹脂封入が行われる。上記インナーリード
５は接着剤８ａ、８ｂが形成される半導体素子搭載予定
領域２ａが他の部分よりもプレス加工で下げて形成さ
れ、接着剤８ａ、８ｂが形成されていないインナーリー
ド５と半導体素子３との間に大きな隙間ｓが形成されて
いるが、これは樹脂封入時の流れ込みを容易にするため
である。Inner leads 5 of the lead frame 2
As shown in FIG. 1, the semiconductor element 3 is bonded via the adhesives 8a and 8b, and the electrode terminal 9 of the semiconductor element 3 and the inner lead 5 are connected by the bonding wire 10, and then resin encapsulation is performed. Done. The inner lead 5 is formed by lowering the semiconductor element mounting region 2a on which the adhesives 8a and 8b are formed by press working as compared with other portions, and the inner leads 5 and the semiconductor element on which the adhesives 8a and 8b are not formed. A large gap s is formed between the gap 3 and the groove 3 for the purpose of facilitating the inflow when the resin is filled.
【００２１】（比較例１）実施例と同じリードフレーム
を使用し、接着剤として、実施例の接着剤８ｂに使用し
た接着剤のみを厚さ３０μｍに塗布し、同様に半導体素
子を搭載した。この場合には、半導体素子を搭載した後
の接着剤厚さが、搭載時の温度と圧力のために厚さ５μ
ｍまで減少した。これは、リードフレームと半導体素子
の絶縁距離としては不十分である。(Comparative Example 1) Using the same lead frame as in Example, only the adhesive used in Example 8 as the adhesive 8b was applied as an adhesive to a thickness of 30 μm, and a semiconductor element was similarly mounted. In this case, the thickness of the adhesive after mounting the semiconductor element is 5 μm due to the temperature and pressure during mounting.
m. This is insufficient as the insulation distance between the lead frame and the semiconductor element.
【００２２】（比較例２）実施例と同じリードフレーム
を使用し、接着剤として実施例の接着剤８ａに使用した
フィラー入りの接着剤のみを厚さ３０μｍに塗布し、同
様に半導体素子を搭載した。この場合には、半導体素子
と接着剤との接着力が不十分で、その後の実装工程で半
導体素子がリードフレームから剥離するものが発生し
た。(Comparative Example 2) Using the same lead frame as in the example, only the adhesive containing the filler used in the adhesive 8a of the example as an adhesive was applied to a thickness of 30 μm, and a semiconductor element was mounted in the same manner. did. In this case, the adhesive force between the semiconductor element and the adhesive was insufficient, and the semiconductor element was separated from the lead frame in the subsequent mounting process.
【００２３】[0023]
【発明の効果】請求項１に記載の半導体装置用リードフ
レームによれば、半導体素子はフィラーを含まない接着
剤と接合されるため十分な接着力をもち、かつその接着
剤とリードフレームの間にはフィラーを含んだ接着剤が
存在するために絶縁厚さの確保ができる。According to the lead frame for a semiconductor device of the present invention, since the semiconductor element is bonded to the adhesive containing no filler, the semiconductor element has a sufficient adhesive force, and between the adhesive and the lead frame. Since there is an adhesive containing a filler, the insulation thickness can be secured.
【００２４】請求項２に記載の半導体装置用リードフレ
ームによれば、フィラーをＳｉＯ2としたので、絶縁厚
さを十分に確保することができる。According to the lead frame for a semiconductor device of the second aspect, since the filler is SiO 2 , the insulation thickness can be sufficiently secured.
【００２５】請求項３に記載の半導体装置用リードフレ
ームの製造方法によれば、リードフレームの半導体素子
搭載予定領域に、フィラーを含む接着剤とフィラーを含
まない接着剤とをパッド印刷法を採用して塗布するよう
にしたので、塗布が簡単で、時間を要さない。According to the method of manufacturing a lead frame for a semiconductor device of the third aspect, an adhesive containing a filler and an adhesive containing no filler are used in a pad printing method in a semiconductor element mounting planned region of the lead frame. Since it is applied in a simple manner, the application is easy and does not take time.
【００２６】請求項４に記載の半導体装置用リードフレ
ームの製造方法によれば、ディスペンサ法で塗布するよ
うにしたので、接着剤の厚みの制御が容易である。According to the manufacturing method of the lead frame for a semiconductor device of the fourth aspect, since the coating is performed by the dispenser method, the thickness of the adhesive can be easily controlled.
【００２７】請求項５に記載の半導体装置用リードフレ
ームの製造方法によれば、ポリイミド、ポリエーテルア
ミドあるいはポリエーテルアミドイミドからなる熱可塑
性接着剤、またはこれらの組合わせからなる接着剤を用
いるようにしたので、比較的低温で塗布することがで
き、リードフレーム材表面が酸化することがない。According to the method of manufacturing a lead frame for a semiconductor device of claim 5, a thermoplastic adhesive made of polyimide, polyether amide or polyether amide imide, or an adhesive made of a combination thereof is used. Therefore, the coating can be applied at a relatively low temperature, and the surface of the lead frame material is not oxidized.
【図１】本発明の一実施例である半導体装置用リードフ
レームを用いて構成された半導体装置の断面図である。FIG. 1 is a sectional view of a semiconductor device configured using a semiconductor device lead frame that is an embodiment of the present invention.
【図２】図１におけるリードフレームの部分的拡大平面
図である。FIG. 2 is a partially enlarged plan view of the lead frame in FIG.
【図３】図２のリードフレームの要部拡大斜視図であ
る。FIG. 3 is an enlarged perspective view of a main part of the lead frame of FIG.
【図４】従来例の半導体装置を示す断面図である。FIG. 4 is a cross-sectional view showing a conventional semiconductor device.
【図５】図４におけるリードフレームの平面図である。5 is a plan view of the lead frame in FIG. 4. FIG.
１ 半導体装置 ２ リードフレーム ２ａ 半導体素子搭載予定領域 ３ 半導体素子 ８ａ フィラーを含んだ接着剤 ８ｂ フィラーを含まない接着剤 DESCRIPTION OF SYMBOLS 1 Semiconductor device 2 Lead frame 2a Semiconductor element mounting planned area 3 Semiconductor element 8a Adhesive containing filler 8b Adhesive containing no filler
───────────────────────────────────────────────────── フロントページの続き (72)発明者 杉本 洋 茨城県土浦市木田余町3550番地 日立電線 株式会社システムマテリアル研究所内 (72)発明者 鈴村 隆志 茨城県日立市助川町３丁目１番１号 日立 電線株式会社電線工場内 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Hiroshi Sugimoto 3550 Kidayo-cho, Tsuchiura-shi, Ibaraki Hitachi Cable Ltd. System Materials Laboratory (72) Inventor Takashi Suzumura 3-1-1 Sukegawa-cho, Hitachi-shi, Ibaraki Hitachi Cable Co., Ltd. inside the cable factory
Claims (5)
に絶縁性高温軟化型接着剤を介在して半導体素子を接合
した半導体装置用リードフレームにおいて、絶縁性高温
軟化型接着剤を２層構造とし、リードフレーム側に絶縁
性のフィラーを含んだ接着剤を介在させ、半導体素子側
にフィラーを含まない接着剤を介在させたことを特徴と
する半導体装置用リードフレーム。1. A lead frame for a semiconductor device, in which a semiconductor element is bonded to an area where a semiconductor element is to be mounted on a lead frame by interposing an insulating high temperature softening adhesive, and the insulating high temperature softening adhesive has a two-layer structure, A lead frame for a semiconductor device, wherein an adhesive containing an insulating filler is interposed on the lead frame side, and an adhesive containing no filler is interposed on the semiconductor element side.
ームにおいて、絶縁性高温軟化型接着剤に含まれる絶縁
性フィラーがＳｉＯ2 からなることを特徴とする半導体
装置用リードフレーム。2. The lead frame for a semiconductor device according to claim 1, wherein the insulating filler contained in the insulating high temperature softening type adhesive is made of SiO 2 .
に絶縁性高温軟化型接着剤を直接塗布し、この塗布した
接着剤の上に半導体素子を載せて接合する半導体装置用
リードフレームの製造方法において、絶縁性高温軟化型
接着剤をパッド印刷法で塗布するようにし、最初に絶縁
性のフィラーを含んだ接着剤を塗布、乾燥し、次にフィ
ラーを含まない接着剤を塗布、乾燥したことを特徴とす
る半導体装置用リードフレームの製造方法。3. A method of manufacturing a lead frame for a semiconductor device, wherein an insulating high temperature softening type adhesive is directly applied to a semiconductor element mounting planned area of a lead frame, and the semiconductor element is placed and bonded on the applied adhesive. Insulating high temperature softening type adhesive is applied by pad printing method, first the adhesive containing insulating filler is applied and dried, then the adhesive without filler is applied and dried. A method for manufacturing a semiconductor device lead frame.
ームの製造方法において、パッド印刷法に代えてディス
ペンサ法で塗布するようにした半導体装置用リードフレ
ームの製造方法。4. The method of manufacturing a lead frame for a semiconductor device according to claim 3, wherein coating is performed by a dispenser method instead of the pad printing method.
ードフレームの製造方法において、絶縁性高温軟化型接
着剤がポリイミド、ポリエーテルアミドあるいはポリエ
ーテルアミドイミドからなる熱可塑性接着剤、またはこ
れらの組合わせからなることを特徴とする半導体装置用
リードフレームの製造方法。5. The method of manufacturing a lead frame for a semiconductor device according to claim 3 or 4, wherein the insulating high temperature softening adhesive is a thermoplastic adhesive made of polyimide, polyether amide or polyether amide imide, or these. A method of manufacturing a lead frame for a semiconductor device, which is characterized by comprising a combination of
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7163495A JPH0917936A (en) | 1995-06-29 | 1995-06-29 | Lead frame for semiconductor device and its manufacturing method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7163495A JPH0917936A (en) | 1995-06-29 | 1995-06-29 | Lead frame for semiconductor device and its manufacturing method |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0917936A true JPH0917936A (en) | 1997-01-17 |
Family
ID=15774959
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP7163495A Pending JPH0917936A (en) | 1995-06-29 | 1995-06-29 | Lead frame for semiconductor device and its manufacturing method |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0917936A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2009246324A (en) * | 2008-03-28 | 2009-10-22 | Powertech Technology Inc | Semiconductor package structure |
-
1995
- 1995-06-29 JP JP7163495A patent/JPH0917936A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2009246324A (en) * | 2008-03-28 | 2009-10-22 | Powertech Technology Inc | Semiconductor package structure |
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