JPH0917884A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPH0917884A
JPH0917884A JP7182177A JP18217795A JPH0917884A JP H0917884 A JPH0917884 A JP H0917884A JP 7182177 A JP7182177 A JP 7182177A JP 18217795 A JP18217795 A JP 18217795A JP H0917884 A JPH0917884 A JP H0917884A
Authority
JP
Japan
Prior art keywords
implantation
transistor
ions
charge
damage
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP7182177A
Other languages
Japanese (ja)
Inventor
Naoki Kawabata
尚樹 川端
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Ricoh Co Ltd
Original Assignee
Ricoh Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ricoh Co Ltd filed Critical Ricoh Co Ltd
Priority to JP7182177A priority Critical patent/JPH0917884A/en
Publication of JPH0917884A publication Critical patent/JPH0917884A/en
Pending legal-status Critical Current

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Landscapes

  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Abstract

PURPOSE: To avoid degrading the withstanding voltage of a gate insulation film and damage thereof by doing the high current ion implantation of a source and drain regions with negative ions for pch transistors and positive ions for nch transistors. CONSTITUTION: BF2 <-> ions are infected at P<+> implantation of a pch transistor. As<-> ions are injected at N<-> implantation of an nch transistor. If the charge up occurs (a resist charges up to positive) at P<+> implantation of the pen transistor, MOS will go to not a storage mode but inverted mode while in case of the nch transistor if the charge up occurs at P<+> implantation, the charges also pass through a substrate and hence the damage of a gate insulation film will be little. Thus, the degradation of the withstanding voltage and damage of the gate insulation film can be certainly avoided.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、半導体装置の製造方法
に関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device.

【0002】[0002]

【従来の技術】従来、MOSFETのソース領域および
ドレイン領域へのイオン注入は、高濃度に形成する必要
があるため、大電流イオン注入装置が用いられている。
2. Description of the Related Art Conventionally, a high current ion implantation apparatus has been used because it is necessary to form a high concentration ion implantation into a source region and a drain region of a MOSFET.

【0003】[0003]

【発明が解決しようとする課題】しかし、大電流イオン
注入工程では、そのチャージアップによるゲート絶縁膜
の破壊が問題となっていた。前記イオン注入工程では通
常、pchトランジスタにおけるP+ 注入時にBF2 +
が用いられ、nchトランジスタにおけるN+ 注入時に
As+ イオンが用いられてきた。チャージアップ防止の
ため、ウエーハ表面近傍において電子シャワーによる中
性化などの方法がとられているが、この方法では必ずし
も十分な効果を得ることはできなかった。特に、pch
トランジスタへのイオン注入において正イオンを用いた
場合、正電荷によるレジストのチャージアップはMOS
が蓄積状態となるため、その電位が直にゲート絶縁膜に
かかるのでゲート破壊が生じやすい。この問題は、近年
の酸化膜の薄膜化においては、特に深刻なものがあっ
た。
However, in the high-current ion implantation process, the breakdown of the gate insulating film due to the charge-up has been a problem. In the ion implantation process, BF 2 + is usually used at the time of P + implantation in a pch transistor.
Has been used, and As + ions have been used during N + implantation in an nch transistor. In order to prevent charge-up, a method such as neutralization by electron shower near the wafer surface has been taken, but this method could not always obtain a sufficient effect. Especially pch
When positive ions are used for ion implantation into a transistor, the charge-up of the resist by positive charges is
Is accumulated, the potential is directly applied to the gate insulating film, so that gate breakdown is likely to occur. This problem has been particularly serious in the recent thinning of the oxide film.

【0004】本発明は、上記問題点に鑑みなされたもの
で、その目的は、pchトランジスタへの大電流イオン
注入工程でのチャージアップに起因するゲート絶縁膜の
耐圧劣化や破壊を防止することにある。
The present invention has been made in view of the above problems, and an object thereof is to prevent the breakdown voltage breakdown and the breakdown of the gate insulating film due to the charge-up in the high current ion implantation step to the pch transistor. is there.

【0005】[0005]

【課題を解決するための手段】本発明に係る半導体装置
の製造方法は、半導体デバイス装置のうちMOSFE
T、特にCMOS構造のpchトランジスタのソース領
域、ドレイン領域形成のための大電流イオン注入を負イ
オンにより行い、nchトランジスタのソース領域、ド
レイン領域形成のための大電流イオン注入を正イオンに
より行うことを特徴とする。
A method of manufacturing a semiconductor device according to the present invention is a method of manufacturing a semiconductor device including a MOSFE device.
T, in particular, a large current ion implantation for forming a source region and a drain region of a p-channel transistor having a CMOS structure is performed by negative ions, and a large current ion implantation for forming a source region and a drain region of an nch transistor is performed by positive ions. Is characterized by.

【0006】[0006]

【作用】本発明では負イオンを注入するものであるた
め、pchトランジスタへのP+注入時にチャージアッ
プが発生(P+ 注入時にレジストが正にチャージアッ
プ)したとしても、MOSは蓄積モードではなく反転モ
ードとなるので、ゲート絶縁膜の耐圧劣化や破壊を防止
することができる。また、pchトランジスタへのN+
注入時にチャージアップが発生した場合には、電荷がレ
ジストから基板へ抜けるので、pchトランジスタにお
けるゲート絶縁膜のダメージは小さくなる。
In the present invention, since negative ions are implanted, even if charge-up occurs during P + implantation into the pch transistor (the resist is positively charged up during P + implantation), the MOS is not in the accumulation mode. Since the mode is the inversion mode, it is possible to prevent the breakdown voltage and the breakdown of the gate insulating film. Also, N + to the pch transistor
When charge-up occurs at the time of implantation, the charge escapes from the resist to the substrate, so that the gate insulating film in the pch transistor is less damaged.

【0007】一方、nchトランジスタの場合、P+
入時にチャージアップが発生しても、やはり電荷がレジ
ストから基板へ抜けるため、ゲート絶縁膜のダメージは
小さくなる。また、nchトランジスタへのN+ 注入時
にチャージアップが発生した場合には、MOSは反転モ
ードとなるため、その電位が全てゲート絶縁膜にかかる
わけではないので、絶縁膜破壊は起こりにくくなる。
On the other hand, in the case of the nch transistor, even if charge-up occurs during P + implantation, the charge still escapes from the resist to the substrate, so that the damage to the gate insulating film is reduced. In addition, when charge-up occurs at the time of N + injection into the nch transistor, the MOS is in the inversion mode, so that not all the potential is applied to the gate insulating film, so that the insulating film breakdown is less likely to occur.

【0008】[0008]

【実施例】以下、本発明の実施例を図面を基に説明す
る。 実施例1 図1(a)は半導体装置の要部平面図、図1(b)はP
+ 領域注入時の断面図、図1(c)はN+ 領域注入時の
断面図である。図中、1はPウエル及びnchトランジ
スタ、2はNウエル及びpchトランジスタ、3はフォ
トレジストである。この実施例では、図1(b)に示す
ように、P+ 領域注入時にはBF2 - イオンを注入す
る。また、図1(c)に示すように、N+ 領域注入時に
はAs+ イオンを注入する。
Embodiments of the present invention will be described below with reference to the drawings. Example 1 FIG. 1A is a plan view of a main part of a semiconductor device, and FIG.
A cross-sectional view at the time of implanting the + region, and FIG. 1C is a cross-sectional view at the time of implanting the N + region. In the figure, 1 is a P well and an nch transistor, 2 is an N well and a pch transistor, and 3 is a photoresist. In this embodiment, as shown in FIG. 1B, BF 2 ions are implanted during P + region implantation. As shown in FIG. 1C, As + ions are implanted at the time of N + region implantation.

【0009】実施例2 図2(a)はP+ 領域注入時の断面図、図2(b)はN
+ 領域注入時の断面図である。この実施例では、図2
(a)に示すように、pchトランジスタにおけるP+
注入時にはAs2 - イオンを注入する。また、図2
(b)に示すようにnchトランジスタにおけるN+
入時にはAs+ イオンを注入する。
Example 2 FIG. 2 (a) is a cross-sectional view at the time of implanting a P + region, and FIG. 2 (b) is N
It is a cross-sectional view at the time of + region implantation. In this embodiment, FIG.
As shown in (a), P + in the pch transistor
At the time of implantation, As 2 ions are implanted. FIG.
As shown in (b), As + ions are implanted at the time of N + implantation in the nch transistor.

【0010】[0010]

【発明の効果】以上の説明で明らかなように、従来技術
ではpchトランジスタのP+ 注入時の大電流イオン注
入を正イオン注入により行っていたのに対して、本発明
では負イオンを注入するものであるため、P+ 注入時に
チャージアップが起こったとしても、MOSは蓄積モー
ドではなく反転モードとなるので、ゲート絶縁膜の耐圧
劣化や破壊を的確に防止することができる効果がある。
As is apparent from the above description, in the prior art, high current ion implantation at the time of P + implantation of a pch transistor was performed by positive ion implantation, whereas in the present invention negative ion implantation is performed. Therefore, even if charge-up occurs during P + implantation, the MOS is in the inversion mode instead of the accumulation mode, so that it is possible to accurately prevent the breakdown voltage breakdown and the breakdown of the gate insulating film.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明の一実施例に係るもので、(a)は半導
体装置の要部平面図、(b)はP+ 注入工程を示すA−
A’断面図、(c)はN+ 注入工程を示すA−A’断面
図である。
[1] relate to an embodiment of the invention, (a) is a fragmentary plan view of a semiconductor device, showing the (b) is P + implantation process A-
A'sectional view, (c) is an AA 'sectional view showing the N + implantation step.

【図2】別の実施例に係るもので、(a)はP+ 注入工
程を示すB−B’断面図、(b)はN+ 注入工程を示す
B−B’断面図である。
2A and 2B relate to another embodiment, and FIG. 2A is a BB ′ sectional view showing a P + implantation step, and FIG. 2B is a BB ′ sectional view showing an N + implantation step.

【符号の説明】[Explanation of symbols]

1 Pウエル及びnchトランジスタ 2 Nウエル及びpchトランジスタ 3 フォトレジスト 1 P well and nch transistor 2 N well and pch transistor 3 Photoresist

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】 半導体デバイス装置のうちMOSFE
T、特にCMOS構造のpchトランジスタのソース領
域、ドレイン領域形成のための大電流イオン注入を負イ
オンにより行い、nchトランジスタのソース領域、ド
レイン領域形成のための大電流イオン注入を正イオンに
より行うことを特徴とする半導体装置の製造方法。
1. A MOSFE of a semiconductor device device
T, in particular, a large current ion implantation for forming a source region and a drain region of a p-channel transistor having a CMOS structure is performed by negative ions, and a large current ion implantation for forming a source region and a drain region of an nch transistor is performed by positive ions. A method for manufacturing a semiconductor device, comprising:
JP7182177A 1995-06-26 1995-06-26 Manufacture of semiconductor device Pending JPH0917884A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7182177A JPH0917884A (en) 1995-06-26 1995-06-26 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7182177A JPH0917884A (en) 1995-06-26 1995-06-26 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPH0917884A true JPH0917884A (en) 1997-01-17

Family

ID=16113696

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7182177A Pending JPH0917884A (en) 1995-06-26 1995-06-26 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPH0917884A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005531156A (en) * 2002-06-26 2005-10-13 セムエキップ インコーポレイテッド Manufacturing method of CMOS device by implantation of N and P type cluster ions and anions

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005531156A (en) * 2002-06-26 2005-10-13 セムエキップ インコーポレイテッド Manufacturing method of CMOS device by implantation of N and P type cluster ions and anions

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