JPH0917884A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE: To avoid degrading the withstanding voltage of a gate insulation film and damage thereof by doing the high current ion implantation of a source and drain regions with negative ions for pch transistors and positive ions for nch transistors. CONSTITUTION: BF2 <-> ions are infected at P<+> implantation of a pch transistor. As<-> ions are injected at N<-> implantation of an nch transistor. If the charge up occurs (a resist charges up to positive) at P<+> implantation of the pen transistor, MOS will go to not a storage mode but inverted mode while in case of the nch transistor if the charge up occurs at P<+> implantation, the charges also pass through a substrate and hence the damage of a gate insulation film will be little. Thus, the degradation of the withstanding voltage and damage of the gate insulation film can be certainly avoided.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device.

[0002]

2. Description of the Related Art Conventionally, a high current ion implantation apparatus has been used because it is necessary to form a high concentration ion implantation into a source region and a drain region of a MOSFET.

[0003]

However, in the high-current ion implantation process, the breakdown of the gate insulating film due to the charge-up has been a problem. In the ion implantation process, BF ₂ ⁺ is usually used at the time of P ⁺ implantation in a pch transistor.
Has been used, and As ⁺ ions have been used during N ⁺ implantation in an nch transistor. In order to prevent charge-up, a method such as neutralization by electron shower near the wafer surface has been taken, but this method could not always obtain a sufficient effect. Especially pch
When positive ions are used for ion implantation into a transistor, the charge-up of the resist by positive charges is
Is accumulated, the potential is directly applied to the gate insulating film, so that gate breakdown is likely to occur. This problem has been particularly serious in the recent thinning of the oxide film.

The present invention has been made in view of the above problems, and an object thereof is to prevent the breakdown voltage breakdown and the breakdown of the gate insulating film due to the charge-up in the high current ion implantation step to the pch transistor. is there.

[0005]

A method of manufacturing a semiconductor device according to the present invention is a method of manufacturing a semiconductor device including a MOSFE device.
T, in particular, a large current ion implantation for forming a source region and a drain region of a p-channel transistor having a CMOS structure is performed by negative ions, and a large current ion implantation for forming a source region and a drain region of an nch transistor is performed by positive ions. Is characterized by.

[0006]

In the present invention, since negative ions are implanted, even if charge-up occurs during P ⁺ implantation into the pch transistor (the resist is positively charged up during P ⁺ implantation), the MOS is not in the accumulation mode. Since the mode is the inversion mode, it is possible to prevent the breakdown voltage and the breakdown of the gate insulating film. Also, N ⁺ to the pch transistor
When charge-up occurs at the time of implantation, the charge escapes from the resist to the substrate, so that the gate insulating film in the pch transistor is less damaged.

On the other hand, in the case of the nch transistor, even if charge-up occurs during P ⁺ implantation, the charge still escapes from the resist to the substrate, so that the damage to the gate insulating film is reduced. In addition, when charge-up occurs at the time of N ⁺ injection into the nch transistor, the MOS is in the inversion mode, so that not all the potential is applied to the gate insulating film, so that the insulating film breakdown is less likely to occur.

[0008]

Embodiments of the present invention will be described below with reference to the drawings. Example 1 FIG. 1A is a plan view of a main part of a semiconductor device, and FIG.
A cross-sectional view at the time of implanting the ⁺ region, and FIG. 1C is a cross-sectional view at the time of implanting the N ⁺ region. In the figure, 1 is a P well and an nch transistor, 2 is an N well and a pch transistor, and 3 is a photoresist. In this embodiment, as shown in FIG. 1B, BF ₂ ⁻ ions are implanted during P ⁺ region implantation. As shown in FIG. 1C, As ⁺ ions are implanted at the time of N ⁺ region implantation.

Example 2 FIG. 2 (a) is a cross-sectional view at the time of implanting a P ⁺ region, and FIG. 2 (b) is N
It is a cross-sectional view at the time of ⁺ region implantation. In this embodiment, FIG.
As shown in (a), P ⁺ in the pch transistor
At the time of implantation, As ₂ ⁻ ions are implanted. FIG.
As shown in (b), As ⁺ ions are implanted at the time of N ⁺ implantation in the nch transistor.

[0010]

As is apparent from the above description, in the prior art, high current ion implantation at the time of P ⁺ implantation of a pch transistor was performed by positive ion implantation, whereas in the present invention negative ion implantation is performed. Therefore, even if charge-up occurs during P ⁺ implantation, the MOS is in the inversion mode instead of the accumulation mode, so that it is possible to accurately prevent the breakdown voltage breakdown and the breakdown of the gate insulating film.

[Brief description of the drawings]

[1] relate to an embodiment of the invention, (a) is a fragmentary plan view of a semiconductor device, showing the (b) is P ⁺ implantation process A-
A'sectional view, (c) is an AA 'sectional view showing the N ⁺ implantation step.

2A and 2B relate to another embodiment, and FIG. 2A is a BB ′ sectional view showing a P ⁺ implantation step, and FIG. 2B is a BB ′ sectional view showing an N ⁺ implantation step.

[Explanation of symbols]

 1 P well and nch transistor 2 N well and pch transistor 3 Photoresist

Claims (1)

[Claims] 1. A MOSFE of a semiconductor device device
T, in particular, a large current ion implantation for forming a source region and a drain region of a p-channel transistor having a CMOS structure is performed by negative ions, and a large current ion implantation for forming a source region and a drain region of an nch transistor is performed by positive ions. A method for manufacturing a semiconductor device, comprising: