JPH09178816A - Multi-ic chip mounted circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To freely combine developed IC chips to form a multi-IC chip mounted circuit, improve the appropriation property of its design asset, appropriate the single test pattern of the IC chip after the assembly is completed, and obtain a high failure inspection rate. SOLUTION: A switching signal input terminal 27, external signal terminals 25a-26c, IC chips 22, 23, and a signal switching IC chip 24 are mounted on a board 21. A control circuit 33 controls signal switching switches 34a-37c based on the mode switching set signal from the switching signal input terminal 27 and selectively connects the external signal terminals 25a-26c including the switching to bypass the IC chips 22, 23. The wafer inspection test pattern of the IC chips 22, 23 is fed to the external signal terminals 25a-26c to test the IC chips 22, 23. The program stored in a program memory section 32b is executed via the control of the control circuit 33 based on the mode switching set signal from the switching signal input terminal 27 to conduct the functional test of the IC chips 22, 23.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multi IC chip mounting circuit in which a plurality of existing semiconductor integrated circuit (IC) chips are mounted on the same substrate.

[0002]

2. Description of the Related Art As a multi-IC chip mounting circuit of this type, Japanese Unexamined Patent Publication No. 4-250644 "Multichip mounting I
C "is known. FIG. 5 shows this conventional multi-IC.
It is a block diagram which shows a chip mounting circuit. The example shown in FIG.
IC chip 1 having a first function in an IC package
And enclose the IC chip 2 having the second function,
A signal line 3 connects between the C chip 1 and the IC chip 2. Further, the terminal 4a of this IC package and the IC chip 1 are connected by a signal line, and the terminal 4b and the IC chip 2 are connected by a signal line.

The IC chip 1 is a logic circuit 1 which is a main function.
a and has a changeover switch 5 between it and the signal pad.
a and 5b are provided. This changeover switch 5a, 5
The bypass wiring 6 is provided between b. The IC chip 2 also has a logic circuit 2a which is a main function. Further, changeover switches 7a and 7b are provided between the switch and the signal pad.

A bypass wiring 8 is provided between the changeover switches 7a and 7b. Further, it has a terminal 9 to which a switching control signal from the outside is supplied, and the IC chip 1 is provided with a control signal line 11 connected to the terminal 9.
The control signal line 11 is connected to the IC chip 2 through the signal pad.
A control signal line 12 that is connected to and is also provided.

In this IC package, a switching control signal from the outside is input to the terminal 9. With this switching control signal I
The changeover switches 5a and 5b of the C chip 1 are switched, and the logic circuit 1a is set to the operation or set to the non-operation through the bypass wiring 6. Similarly, in the IC chip 2, the changeover switches 7a and 7b of the IC chip 2 are switched by the changeover control signal to set the logic circuit 2a to the operating state or the non-operating state through the bypass wiring 8.

In such a multi-chip mounting IC, an assembly inspection is carried out by utilizing the changeover switches 5a, 5b, 7a, 7b and the bypass wirings 6, 8. FIG. 6 is a flowchart showing the processing procedure of this assembly inspection. In the example shown in FIG. 6, a test pattern (signal) for wafer inspection of the IC chips 1 and 2 is diverted to perform an assembly inspection.

First, the IC chips 1 and 2 are manufactured, each wafer is inspected by a test pattern and sealed in an IC package. Next, the bypass switches 8 in the IC chip 2 are selected by the changeover switches 7a and 7b by the switching control signal "1", and the test pattern at the time of wafer inspection is input to the IC chip 1 to perform the functional test. The quality of the assembly inspection of the IC chip 1 is confirmed.

Next, the changeover switches 5a and 5b select the bypass wiring 6 in the IC chip 1 with the changeover control signal "2", and the IC chip 2 receives the test pattern at the time of wafer inspection to perform the functional test. Then, the quality of the assembly inspection of the IC chip 1 is confirmed. When the device is operated thereafter, the logic circuits 1a and 2a are coupled and operated by the switching control signal signal "0".

[0009]

However, the above-mentioned conventional example has the following drawbacks. (1) There are restrictions on the IC chips to be mounted, and only a combination of dedicated IC chips can be mounted. That is, I
Changeover switches 5a, 5b, 7a, 7b for switching the bypass wirings 6, 8 are required in the C chip. Therefore, when configuring an existing IC chip into a multi-IC chip mounting circuit, it is necessary to create a new photomask for adding a bypass wiring and a changeover switch, which is a drawback that mounting is difficult.

(2) It is necessary to change the configuration of the bypass wiring and the changeover switch every time the combination of the mounted IC chips is changed. That is, since the bypass wiring and the changeover switch connect the IC chip on the partner side and the external terminal, individual connection corresponding to the IC chip on the partner side is required, which is not versatile. .

The present invention solves the problems in the prior art as described above, and it is possible to freely combine development-completed IC chips to form a multi-IC chip mounting circuit, which improves the diversion of design assets. And, a multi-IC-chip mounting circuit that can obtain a high failure inspection rate by utilizing a test pattern for an independent test of an IC chip after completion of assembly is provided.

[0012]

In order to achieve the above object, a multi IC chip mounting circuit according to a first aspect of the present invention is mounted on a substrate, a substrate provided with a switching signal input terminal and a plurality of external signal terminals. A signal for switching and connecting between a plurality of IC chips and a plurality of external signal terminals mounted on a substrate based on a mode switching setting signal from a switching signal input terminal. It is configured to include a switching IC chip.

According to a second aspect of the present invention, there is provided a multi-IC chip mounting circuit, wherein the signal switching IC chip has a plurality of signal changeover switches for switching and connecting between a plurality of IC chips and a plurality of external signal terminals. , And a control circuit for controlling the plurality of signal changeover switches based on the mode changeover setting signal from the changeover signal input terminal.

According to a third aspect of the present invention, there is provided a multi-IC chip mounting circuit, wherein a wafer inspection test pattern of the IC chip is supplied to an external signal terminal to test each of the plurality of IC chips.

According to a fourth aspect of the present invention, there is provided a multi-IC chip mounting circuit, wherein the control circuit according to the second aspect is provided with a memory for storing a program, and the program stored in the memory is set for mode switching from a switching signal input terminal. This is executed based on a signal, and a plurality of signal changeover switches are changed over to switch and connect between a plurality of IC chips and a plurality of external signal terminals.

According to a fifth aspect of the present invention, there is provided a multi-IC chip mounting circuit, wherein the plurality of signal changeover switches according to the second aspect are provided with a bypass signal line for bypassing between the plurality of IC chips.

In the multi IC chip mounting circuit having such a configuration, the plurality of IC chips mounted on the substrate are connected between the plurality of IC chips and between the plurality of external signal terminals based on the mode switching setting signal. It is connected by switching to bypass. Further, each IC chip test is performed based on the IC chip wafer inspection test pattern. Further, the stored program is executed to switch the plurality of signal changeover switches.

Therefore, a multi IC chip mounting circuit can be constructed by freely combining the development completed IC chips,
The diversion of the design property is improved. Further, a high failure inspection rate can be obtained by utilizing the test pattern for the independent test of the IC chip after the completion of the assembly. Further, by executing the stored program, it becomes possible to cope with the mounting of IC chips having various functions.

[0019]

BEST MODE FOR CARRYING OUT THE INVENTION Next, an embodiment of a multi IC chip mounting circuit of the present invention will be described in detail with reference to the drawings. FIG. 1 shows a first multi-IC chip mounting circuit of the present invention.
It is a lineblock diagram of an embodiment. In the example shown in FIG. 1, an IC chip 22 having a first function, an IC chip 23 having a second function, and a signal switching connection for switching the operations of the IC chips 22 and 23 are provided on a substrate 21. It has an IC chip 24. Furthermore, the external signal terminals 25a, 2
5b, 25c, 26a, 26b, 26c, and a switching signal input terminal 27.

The IC chip 22 having the first function includes a functional circuit 28 and signal pads 29a, 29b, 29c, 2
9d, 29e, 29f. The IC chip 23 having the second function also includes the functional circuit 30 and the signal pad 31.
It has a, 31b, 31c, 31d, 31e, 31f.

The signal switching IC chip 24 includes a control circuit 33 including a control signal generator 32a and a program memory 32b, and signal changeover switches 34a, 34b, 34.
c, 35a, 35b, 35c, 36a, 36b, 36
c, 37a, 37b, 37c and signal pads 41, 4
2,43,44,45,46,47,48,49,5
0,51,52,53,54,55,56,57,5
8, 59, 96, 97, 98, 99, 100, 101.

The switching signal input terminal 27 and the external signal terminals 25a to 26c of the board 21 are all connected to the board signal lines 60 and 6.
1, 62, 63, 64, 65, 66, signal switching IC
The chip 24 is connected to the signal pads 41 to 44 and 57 to 59, respectively. Further, all of the signal pads 29a to 29f of the IC chip 22 and all of the signal pads 31a to 31f of the IC chip 23 are connected to the board signal lines 67, 68 and 6.
9, 70, 71, 72, 73, 74, 75, 76, 7
The signal pads 45 to 56 of the signal switching IC chip 24 are connected through 7, 78, respectively.

Further, the signal pads 96 to 98 of the signal switching IC chip 24 and the signal pads 101 to 99 are connected by substrate signal lines 87, 88 and 89, respectively. These board signal lines and signal pads are connected by wire bonding or direct soldering.

FIG. 2 is a flow chart showing the processing procedure of the assembly inspection in the first embodiment. The processing procedure of the assembly inspection will be described with reference to the flowchart shown in FIG. First, the signal switching IC chip 24 is manufactured, inspected through a test pattern, and sealed in the substrate 21. Next, I
The C chips 22 and 23 are manufactured, inspected through a test pattern, and sealed on the substrate 21. Next, a switching setting program for the signal switching IC chip 24 was used to perform an assembly inspection in switching modes 0, 1, 2, and 3 described below, and the IC chips 22 and 23 were combined during the subsequent operation of the apparatus. Take action.

Next, the signal connection in the signal switching IC chip 24 and its operation will be described. The signal pad 41 is directly connected to the control circuit 33 by a switching signal line 79, and the control circuit 33 operates by the switching signal supplied to the switching signal input terminal 27. Table 1 below shows the selection operation of the respective signal changeover switches 34a to 37c for the changeover modes 0 to 3.

[0026]

[Table 1]

As shown in Table 1, in the switching mode 0, the control signal generator 32 of the control circuit 33 is supplied through the control signal line 83.
The signal changeover switches 34a to 34c connect the signal pads 57 to 59 to the write signal lines 80, 81 and 82 in accordance with the control signal supplied from a, and the external signal terminals 26a to 2c are connected.
An information signal is input to 6c and the program is written and stored in the program storage unit 32b in the control circuit 33. In this changeover mode 0, the other signal changeover switches 35a-3
The connection operation of 7c may be arbitrary.

In the switching mode 1 shown in Table 1, the control circuit 3
The information read from the program storage unit 32b in 3
New control signals are sent from the control signal generator 32a to the control signal lines 83 to 86, respectively. Accordingly, as shown in Table 1, the signal changeover switches 34a to 34c connect the signal pads 57 to 59 and the signal pads 56 to 54, respectively.

The signal changeover switches 35a to 35c connect the signal pads 51 to 53 and the signal pads 101 to 99, respectively, and the signal changeover switches 36a to 36c connect the signal pads 96 to 98 and the bypass signal lines 93 to 95, respectively. The signal changeover switches 37a to 37c are connected to the bypass signal lines 93 to 95 and the signal pads 44 to 42, respectively.

As described above, in the switching mode 1, the external signal terminals 26a to 26c, the IC chip 22, and the board signal line 87 to.
89, bypass signal lines 93 to 95, and external signal terminal 25
It becomes the structure which electrically connects a-25c. Therefore, by assembling the test pattern used for the wafer inspection at the time of manufacturing the IC chip 22 by inputting the test pattern from the external signal terminals 25a to 26c after mounting on the substrate 21 and performing the functional test of the IC chip 22. Can be inspected. Since the test pattern is diverted in this way, I
The same failure inspection rate can be obtained for the C chip 22 as during wafer inspection.

At the same time, the external signal terminals 25a to 26c are also provided.
And signal pads 42 to 44 of the signal switching IC chip 24,
Each signal connection between 57 and 59 is electrically confirmed. Similarly, the signal pads 51 to 56 and the signal switching I
Each signal connection between the signal pads 29a to 29f of the C chip 24 and each signal connection between the signal pads 96 to 98 and the signal pads 101 to 99 of the signal switching IC chip 24 are electrically connected. It is confirmed.

Next, in the switching mode 2, another information is read from the program storage section 32b in the control circuit 33, and a new control signal is sent from the control signal generating section 32a to the control signal line 8.
3 to 86. As a result, the signal changeover switch 3
4a to 37c are switched to the signal connection corresponding to the switching mode 2 in Table 1, respectively.

In the switching mode 2, the external signal terminals 26a ...
26c, bypass signal lines 90 to 92, substrate signal line 87 to
89, the IC chip 23 having the second function and the external signal terminals 25a to 25c are electrically connected. Therefore, in this switching mode 2, as in switching mode 1, I
By inputting the test pattern used in the wafer inspection when the C chip 23 is manufactured from the external signal terminals 25a to 26c and performing the functional test of the IC chip 23, the assembling quality can be inspected. Since the test pattern is diverted in this way, the same failure inspection rate as that at the time of wafer inspection of the IC chip 23 can be obtained.

At this time, the signal switching IC chip 2 is further added.
4 signal pads 45 to 50 and signal pads 31a to 31
Each signal connection with f is confirmed. As a result, together with the signal path confirmed in the switching mode 1, the assembly inspection of the entire multi IC chip mounting circuit is completed.

In the switching mode 3, a new control signal is further supplied, and the signal changeover switches 34a to 37c perform the signal connection of the switching mode 3 shown in Table 1. As a result, the external signal terminals 26a to 26c, the IC chip 22, the board signal lines 87 to 89, the IC chip 23, and the external signal terminals 25a to
The circuit configuration is 25c. Therefore, the IC chip 2
It is possible to realize a circuit equivalent to the conventional multi-IC chip mounting circuit in which 2 and 23 are directly connected. Here, since the assembly inspection is completed in the switching modes 1 and 2, the design of the assembly inspection test pattern corresponding to the switching mode 3 is unnecessary.

As described above, in the first embodiment, the program is written in the signal switching IC chip 24 in the switching mode 0, and then the I function having the first function in the switching mode 1 is written.
A functional test is performed by bypassing the parts other than the C chip 22. Further, the IC chip 23 having the second function in the switching mode 2
The assembly inspection is performed according to a functional test procedure that bypasses the others, and the wafer inspection test pattern of the IC chips 22 and 23 is diverted to complete the assembly inspection of the entire multi-IC chip mounting circuit.

In this case, since the IC chips 22 and 23 are subjected to the assembly inspection by the existing test pattern for the wafer inspection, the IC chips 22 and 23 have the same high failure inspection rate as in the case of the wafer inspection. Be able to do assembly inspection. As a result, the existing IC chip 2
It is possible to perform the assembly inspection of the entire multi-IC chip mounting circuit by simply diverting the wafer inspection test pattern into Nos. 2 and 23 without any change.

FIG. 3 is a block diagram showing the second embodiment. The multi-IC chip mounting circuit shown in FIG.
1 has an IC chip 202 having a first function and an I chip having a second function.
It has a C chip 203 and an IC chip 204 having a third function. Further, the signal switching IC chip 205 is mounted, and external signal terminals 206, 207, 208, 209,
It has 210, 211, 212, 213 and a switching signal input terminal 214.

The IC chip 202 includes a functional circuit 215 having a first function and signal pads 216, 217, 21.
8, 219, 220, 221, 222, 223, and the IC chip 203 has a functional circuit 224 having a second function and signal pads 225, 226, 227, and
228 and 229.

The IC chip 204 having the third function includes the functional circuit 230 having the third function and the signal pads 231 and 231.
32, 233 and 234. Signal switching IC
The chip 205 has a control circuit 237 including a control signal generation unit 235 and a program storage unit 236. Furthermore, the signal switching blocks 238, 239, 240, 24
1, 242, 243 and signal pads 244, 245, 2
46,247,248,249,250,251,25
2,253,254,255,256,257,25
8,259,260,261,262,263,26
4,265,266,267,268,269,27
0,271,272,273,274,275,27
6,277,278,279,280.

FIG. 4 shows the signal switching blocks 238 to 243.
FIG. 3 is a block diagram showing a detailed configuration of FIG. The example shown in FIG. 4 has a plurality of signal changeover switches SWa, SWb, SWc, and SWd that perform a switching operation on a control signal line, and the function thereof is the same as that of the first embodiment shown in FIG.

In the second embodiment, the switching signal input terminal 214 of the board 201 and all of the external signal terminals 206 to 213 are connected to the board signal lines 281, 282, 283, 284, and 2.
85, 286, 287, 288, 289, the signal pads 244 to 248, 2 of the signal switching IC chip 205.
70, 271, 279 and 280, respectively. Further, all of the signal pads 216 to 223 of the IC chip 202 of the first function, the signal pads 225 to 229 of the IC chip 203 of the second function, and the signal pads 231 to 234 of the IC chip 204 of the third function. Are substrate signal lines 290, 291, 292, 293, 294, 295, 2
96, 297, 298, 299, 300, 301, 30
2, 303, 304, 305, 306, signal pads 249 to 256, 26 of the signal switching IC chip 205.
4 to 268 and 275 to 278, respectively.

Further, the signal pads 257 to 259, 260, 272 of the signal switching IC chip 205 and the signal pad 2
74, 263 to 261, 273 are connected to the substrate signal lines 307, 308, 309, 310, 311 respectively, and only the signal pad 269 is open.
There is no restriction on the assembling method, and a conventional method may be used.

In the second embodiment, the substrate signal line 312 of the signal switching IC chip 205 is connected from the signal pad 244 to the control signal generator 235 in the control circuit 237. Write signal lines 313, 314, 315, 316
However, the signal switching block 238 is connected to the program storage unit 236 in the control circuit 237. Further, the control signal lines 317, 318, 319, 320, 321, 32
2 are connected from the control signal generator 235 in the control circuit 237 to the signal switching blocks 238 to 243, respectively.

Bypass signal lines 323, 324, 325 and 326 are connected to the signal switching blocks 238 and 239, and bypass signal lines 327, 328 and 329 are connected to the signal switching blocks 240 and 241. . Further, bypass signal lines 330 and 331 are connected between the signal switching blocks 242 and 243.

With such a configuration, the signal switching blocks 238 to 243 perform the switching operation shown in Table 2 with respect to the switching mode signals 0, 2, 3, and 4 supplied to the switching signal input terminal 214.

[0047]

[Table 2]

As shown in Table 2, in the switching mode signal 0, the switching modes 1 to 206 are transferred from the external signal terminals 206 to 209 to the program storage section 236 in the control circuit 237 through the signal switching block 238 and the write signal lines 316 to 313. Four
The operation setting program of the signal switching blocks 238 to 243 is written.

As shown in Table 2, in the switching mode signal 1, the program information read from the program storage unit 236 is used to output the control signal line 317 from the control signal generation unit 235.
Through 322, switching setting to the signal switching blocks 238 through 243 is performed. That is, the connection shown in Table 2 is performed. As a result, all the signal pads 216 to 223 of the IC chip 202 having the first function are connected to the external signal terminal 20.
A circuit electrically connected to each of 6 to 213 is configured.

In the switching mode signal 2, the signal pads 225 to 229 of the IC chip 203 having the second function.
Are external signal terminals 206 to 208, 213, 21
1 is electrically connected to each of the circuits.
In switching mode signal 3, an IC having a third function
A circuit is configured in which all of the signal pads 231 to 234 of the chip 204 are electrically connected to the external signal terminals 209, 206, 213 and 212, respectively.

In the case of the switching mode signal 4, the signal switching I
All of the bypass signal lines 323 to 331 of the C chip 205 are set to be separated, and the IC chip 20 having the first function is set.
The second signal pads 216 to 219 are connected to the external signal terminal 209.
To 206 are electrically connected to each other. The signal pads 220 to 222 have a circuit configuration electrically connected to the signal pads 227 to 225 of the IC chip 203 having the second function, respectively.
3 has a circuit configuration electrically connected to the signal pad 231 of the IC chip 204 having the third function.

Further, the IC chip 20 having the second function
The third signal pad 228 has a circuit configuration electrically connected to the signal pad 232 of the IC chip 204 having the third function, and the signal pad 229 has a circuit configuration electrically connected to the external signal terminal 211. . The signal pads 233 and 234 of the IC chip 204 having the third function have a circuit configuration electrically connected to the external signal terminals 213 and 212, respectively. Thus, the I having the first function
C chip 202, IC chip 203 having second function
And a multi-IC chip mounting circuit in which the IC chips 204 having the third function are joined is configured.

As described above, in the second embodiment, the program is written in the signal switching IC chip 205 in the switching mode 0, and then the I function having the first function in the switching mode 1 is used.
A functional test is performed using the test pattern of the C chip 202. Further, in the switching mode 2, a functional test is performed by the test pattern of the IC chip 203 having the second function,
The assembly test of the entire multi IC chip mounting circuit is completed only by performing the function test by the test pattern of the IC chip 204 having the third function in the switching mode 3. In this case, it is not necessary to design the test pattern for the combined function corresponding to the switching mode 4.

In the second embodiment, three ICs are used.
The case of mounting the chips 202 to 204 has been described, but the signal switching IC chip 205 to be mounted on the same substrate.
The circuit configuration of the signal switching IC chip 205 in the first embodiment shown in FIG.
If there are enough signal changeover switches and signal pads to be installed, it is possible to use them simply by changing the program.

Also, when changing or increasing the number of IC chips of each function, it is possible to deal with the change by changing the program and the connection of the board signal line, and two or more signal switching ICs. It is also possible to perform functional division using a chip.

[0056]

As is apparent from the above description, according to the multi-IC chip mounting circuit of claims 1 to 5, a plurality of IC chips mounted on the substrate are provided between the plurality of IC chips and a plurality of external signal terminals. By switching between the two, connection is performed, and each IC chip is tested based on the IC chip wafer inspection test pattern, and the stored program is executed to switch a plurality of signal changeover switches. We are switching.

As a result, it is possible to freely combine the development-completed IC chips to form a multi-IC-chip mounting circuit, improve the diversion of design resources, and further, after the assembly is completed, I
It is possible to obtain a high failure inspection rate by diverting the test pattern for the independent test of the C chip, and by executing the stored program, it becomes possible to implement the mounting of IC chips having various functions.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of a first embodiment of a multi IC chip mounting circuit of the present invention.

FIG. 2 is a flowchart showing a processing procedure of an assembly inspection in the first embodiment.

FIG. 3 is a configuration diagram showing a second embodiment.

4 is a detailed configuration diagram of a signal switching block in FIG.

FIG. 5 is a configuration diagram showing a conventional multi IC chip mounting circuit.

FIG. 6 is a flowchart showing a processing procedure of an assembly inspection in a conventional example.

[Explanation of symbols]

21,201 Substrate 22,23,202-204 IC chip 24,205 Signal switching IC chip 25a-26c, 206-213 External signal terminal 27,214 Switching signal input terminal 28,30,215,224,230 Functional circuit 29a ~ 29f, 31a to 31f, 41 to 59, 96 ~
101,216-223,225-229,2311-2
34, 244-280 Signal pad 32a, 235 Control signal generation part 32b, 236 Program storage part 33, 237 Control circuit 34a-37c, SWa-SWd Signal changeover switch 60-78, 87-89, 281-131 Board signal line 79 , 312 switching signal lines 80-82, 313-316 writing signal lines 90-95, 323-331 bypass signal lines 238-243 signal switching block 83-86, 317-322 control signal lines

Claims (5)

[Claims] 1. A substrate on which a switching signal input terminal and a plurality of external signal terminals are provided, and a plurality of ICs mounted on the substrate.
A chip and a signal switching IC mounted on the substrate for switching and connecting between the plurality of IC chips and a plurality of external signal terminals based on a mode switching setting signal from a switching signal input terminal. A multi-IC chip mounting circuit, comprising: a chip. 2. The signal switching IC chip, a plurality of signal changeover switches for switching and connecting between the plurality of IC chips and a plurality of external signal terminals, and a mode from the switching signal input terminal. The multi-IC chip mounting circuit according to claim 1, further comprising: a control circuit that controls the plurality of signal changeover switches based on a change-over setting signal. 3. The multi-IC chip mounting circuit according to claim 1, wherein a test pattern for wafer inspection of the IC chip is supplied to an external signal terminal to test each of a plurality of IC chips. 4. The control circuit according to claim 2, wherein a memory for storing a program is provided, and the program stored in the memory is executed based on a mode switching setting signal from a switching signal input terminal to output a plurality of signals. A multi-IC-chip mounting circuit, characterized in that a changeover switch is switched to switch between the plurality of IC chips and between a plurality of external signal terminals and to connect them. 5. A multi-IC chip mounting circuit, wherein the plurality of signal changeover switches according to claim 2 are provided with a bypass signal line for bypassing between the plurality of IC chips.