JPH09168123A - Aspect conversion circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To decrease the number of memory cells which are needed for conversion processing of an aspect ratio. SOLUTION: A switch string 13 is controlled and selected by a write clock circuit 12 to divide the pixel strings arrayed in sequence in the horizontal scanning direction into plural blocks. The input image data are stored in a memory block 14 consisting of cells equal to one of divided blocks. Then every stored value selects a memory cell via a switch string 16 controlled by the clock of a read clock circuit 15 and then outputs it through an output terminal 17. Under such conditions, the reading time is shortened according to the writing time and the number of cells is set so as to complete a reading operation when a writing operation equal to a single line is completed. The number of memory cells where the coincidence is secured between the reading time and the writing time is set after the writing and reading operations of a single block are defined as one round and repeated in several times in 1H. Thus the writing and reading operations are defined as one round and repeated in plural times in 1H. As a result, the number of necessary memory cells is extremely decreased compared with the number of pixels equal to 1H.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a television receiver capable of displaying images with different aspect ratios.

[0002]

2. Description of the Related Art When displaying an image having an aspect ratio of 4: 3 on a wide television receiver having a screen aspect ratio of 16: 9, the television signal is displayed without any processing. As in b), it extends in the horizontal direction. Therefore, it is necessary to time-compress the signal of the original image to 3/4 and display an image without distortion as shown in FIG.

Conventionally, compression processing has been realized with the configuration of FIG. 11 using a line memory that divides an image of 1H (one horizontal scanning line period) into fine pixels and holds the values. The compression operation will be described below.

In order to divide one line into M pixels and hold the value of each pixel, the number of cells constituting the line memory is M. And prepare two lines of this line memory,
First, the switches SW1 and SW switched as shown in the figure.
Of the two, the image data input to the memory Ma via the switch SW1 is written. I finished writing,
That is, at the time when one line has been held, the switch S
W1 and SW2 are switched in the opposite manner to that shown in the figure, reading of data from the memory Ma is started, and the next line is written in the other memory Mb. The read rate is faster than the write rate, and the read data is displayed on the TV.
When it is displayed on the screen, it is time-compressed in the horizontal scanning direction, and it is possible to display an image without distortion.

Conventional ICs (integrated circuits) to which this principle is applied include those using capacitors for cells constituting a memory and those using digital memories. In any case, in order to actually compress the television signal, it is necessary to process the luminance signal and the two types of color difference signals.
Since three lines of compression circuits for two line memories described above are required, the area occupied by the circuits used for the memory cells on the IC chip becomes extremely large.

[0006]

It is said that the number of memory cells required is very large in order to simply perform compression in the above-described television receiver capable of displaying images by changing the aspect ratio of the conventional image. There was a problem.

The present invention provides an aspect conversion circuit capable of reducing the number of memory cells required for the conversion processing of the aspect ratio.

[0008]

In order to solve the above-mentioned problems, the aspect conversion circuit of the present invention has a cell for one block when a pixel row arranged in the horizontal scanning direction is divided into a plurality of blocks. A first switch row for guiding the input image data to each cell of the memory, and the first switch row for sequentially storing the horizontal input image data in the memory. A write clock circuit for controlling opening / closing, a second switch row for guiding the image data of each cell of the memory to an output, and the stored image data for sequentially reading in the written order, While changing the clock frequencies of the read clock circuit that controls the opening and closing of the second switch row in sequence and the read and write clock circuits, Characterized by comprising the control means for controlling a plurality of times within one horizontal scanning period of the input image data to round the saw out and write.

With such a configuration, when writing and reading for one block are made one cycle and repeated several times within the 1H period, the number of memory cells is set so that the reading time and the writing time match. As a result, one cycle of writing and reading can be repeated a plurality of times within the 1H period, so that the number of memory cells required for this processing can be significantly smaller than the number of pixels for 1H.

[0010]

Embodiments of the present invention will be described below in detail with reference to the drawings. First, FIG.
The first embodiment of the present invention will be described with reference to the block diagram of FIG. In FIG. 1, this is a circuit that horizontally compresses image data input to the input terminal 11 for each 1H and outputs the compressed image data. Let M be the number of cells in a memory, which is composed of cells for one block when a pixel column sequentially arranged in the horizontal scanning direction is divided into a plurality of blocks. The input signal is selected by the switch train 13 controlled by the write clock circuit 12 and held in the memory cell of the memory 14. Then, each held value is selected from the memory cell by the switch row 16 controlled based on the clock of the read clock circuit 15, and is output from the output terminal 17.

The embodiment of FIG. 1 will be further described with reference to FIG. 2 for reading and writing to the memory 14.
As shown in FIG. 2, the read time T2 is equal to the write time T
Set shorter than 1 and start writing at t1 and t2
At that point, the reading of the image data is started. As a result, reading gradually catches up with writing. When the writing of the number of memory cells for one line is completed,
If setting is made so that reading is also completed, new writing is performed before the value is read and the held value is not lost before being read.

As described above, when one block is written and read once, and repeated several times within the 1H period, the number of memory cells whose read time and write time match may be set. Since one cycle of writing and reading can be repeatedly used within the 1H period, the number of memory cells required for this processing can be significantly smaller than the number of pixels for 1H.

Next, referring to the timing chart of FIG. 3, the first embodiment in which the reading is started after a lapse of a certain time from the start of the writing will be described more specifically.

To start a write operation and start a read operation after a lapse of a certain time, for example, in order to complete the 1H period with the read operation catching up with the write operation after three cycles, write operation is started. It suffices that the time td from the start of reading to the start of reading satisfies the following expression.

That is, the write clock frequency is f
w, the read clock frequency is fr, and the number of memory cells is M
Then, td = [(1 / fw)-(1 / fr)] × M × 3 If fw, fr, and td satisfying this condition are selected, the aspect conversion processing is performed with 1/3 of the number of input pixels of the memory cells. It becomes possible to do. The number of times of writing and reading is not limited to 3 and can be set.

FIG. 4 is an explanatory diagram for explaining the second embodiment of the present invention. This embodiment differs from the first embodiment only in the portion in which the reading to the memory 14 is set later than the writing.

That is, if the reading is made slower than the writing and the writing and the reading are started at the same time, the writing gradually catches up with the reading, but in this case as well, the number of memory cells may be at least a certain minimum number determined by the reading / writing rate. For example, the value held in the cell before being read is not lost before being read.

In this way, if writing and reading of one block are made one cycle and repeated several times within the 1H period,
It is only necessary to set the number of memory cells in which the last read and the write time of the next line match within the H period. Since one cycle of writing and reading can be repeated multiple times within a 1H period, the number of memory cells required for this processing is
It is significantly smaller than the number of pixels for 1H.

The decompression processing in this embodiment can also be performed if conditions are set in the same idea as the compression processing. It should be noted that the number of repetitions of writing and reading is 3
It can be set without limitation.

A third embodiment of the present invention will be described with reference to FIG. In this embodiment, a 16-pixel input image is taken as an example and compressed into a 3/4 image.

That is, the input image data in the horizontal direction is
The image written in the memory is compressed by thinning out i times every N times at a constant cycle. Here, when N is 4 and i is 1, the number of memory cells required for the process of writing in the memory is 16 pixels × (N−i) / N ² = 16 × 3/16 = 3 cells. Writing and reading will be described by affixing the symbols a, b, and c to these three cells in order.

As shown in FIG. 5, the first, second, and third input pixels are sequentially written in the cells a, b, and c in the first cycle, and the fourth pixel is thinned out, and at the same time, the cells are sequentially read from the cell a. Start. When this operation is repeated four times, the output pixel is a compressed signal which is thinned out by one pixel to four pixels.
As is apparent from the figure, the writing is performed again before the reading and the held value is not lost before the reading. By the way, information is thinned out and image is compressed,
Although the output image information is less than the input image information, there is no visual problem because the thinned portion is compressed.

In this embodiment, the number of memory cells can be reduced by the amount of thinning. Further, since the pixel interval between the input pixel and the output pixel and the clock frequency for writing and reading can be set to be the same, a common clock frequency can be used, which can contribute to the reduction of the circuit scale.

Next, a fourth embodiment of the present invention will be described with reference to FIG. In this embodiment, the input image is compressed by changing the read and write frequencies. That is, the reading frequency of the memory is set to N / (N−i) times the writing frequency, the reading is started in parallel with the writing immediately before the writing completes one cycle, and the number of cells in the memory is set to the number of pixels per horizontal scanning of the input image. The input image is compressed by a ratio of (N−i) / N in the horizontal direction and is output.

Also here, when the number of input pixels for processing is 16, the compression ratio is 3/4, N = 4, and i = 1, the number of memory cells required for processing is 16 pixels × i / N = 16 × 1/4 = 4 cells. Writing and reading will be described by sequentially assigning the symbols a, b, c, and d to these four cells.

As shown in FIG. 6, a, b, c,
The 1st, 2nd, 3rd and 4th input pixels are sequentially written in the cell of d, and the reading is started from the cell of a immediately before the fifth pixel is written in the cell of a. If this read frequency is set to 3/4 times the write frequency, the read catches up with the write in four cycles as shown in the figure, and one line compression processing can be realized. Also in this case, writing is performed again before reading is performed and the held value is not lost before reading.

In this embodiment, although the number of cells for which the input image data is not thinned is increased as compared with the embodiment of FIG. 5, since the writing and reading clock frequencies are changed to compress the information, Input image data is not lost in output image data, and more faithful reading can be performed.

Next, referring to the block diagram of FIG. 7, the input image data in the horizontal direction is thinned out i times every N times at a constant cycle, and the image data is compressed and written in the memory. An example will be described in which the invention is applied to a wide television receiver which displays a television signal transmitted with an aspect ratio of 4: 3 on a full screen with an aspect ratio of 16: 9.

Here, an example in which one line of the input image is decomposed into 640 pixels and compressed to 3/4 will be described.
The number of memory cells required for signal processing when N is four times and i is once is: 640 pixels × (N−i) / N ² = 640 × 3/16 = 1
It will be 20 cells.

In FIG. 7, a write clock circuit 71
The read clock circuit 72 and the read clock circuit 72 each have 120 control outputs, and sequentially switch the control outputs corresponding to the given clocks to output control signals. If the write clock circuit 71 is thinned out once every four times and supplied,
In each of the memory cells M1 to M120, a value obtained by thinning out one pixel in four pixels is held, and as a result, 160 pixels are compressed to 120 pixels.

If the read clock circuit 72 is supplied to all 120 cells without thinning at the same time that all the values are written, the read catches up with the write at the point when the write and read cycles are four. The number of input pixels compressed in one cycle is 160 pixels, which is compressed to 120 pixels.
An output image obtained by compressing an input image of 0 × 4 = 640 pixels to 120 × 4 = 480 pixels can be obtained.

A fifth embodiment of the present invention will be described with reference to the block diagram of FIG. The input signals supplied to the input terminal 81 are sample hold circuits 821 to 82.
4 respectively. Sample and hold circuits 821-
824 holds the input signal with the control signal supplied from the control circuit 83 at the timing of the numbers 1 to 4 attached to the control terminal. The output of the sample-hold circuit 821 is multiplied by a coefficient of 3/4, the output of the sample-hold circuit 822 is multiplied by a coefficient of 1/4, and the result is added by the adder 841. The output is supplied to the fixed terminal S2 of the switch 85. . The output of the sample hold circuit 821 is multiplied by a coefficient of 1/2, the output of the sample hold circuit 823 is multiplied by a coefficient of 1/2, and the result is added by an adder 842.
5 to the fixed terminal S3. Further, the output of the sample-hold circuit 823 is multiplied by a coefficient of 1/4, and the output of the sample-hold circuit 824 is multiplied by a coefficient of 3/4 to adder 84.
Then, the output is supplied to the fixed terminal S4 of the switch 85. The fixed terminal S1 of the switch 85 is not connected.

The timing at which the sample hold circuits 821 to 824 are controlled and the timing at which the movable terminal S of the switch 85 is switched coincide with the numbers of the fixed terminals S1 to S4. That is, 1 and S1, 2 and S2, 3 and S3,
4 and S4 operate at the same timing.

The output signal So of the switch 85 is obtained by thinning out the input image data in the horizontal direction once every four times at a constant cycle, compressing the image data and writing the compressed data in the memories M1 to M120. To the data input unit of M120.

Here, the sample hold circuits 821-8
24 are operated in the order of the control signal numbers of the control circuit 83, the input pixel numbers shown in FIG. Of pixels are held in the sample hold circuits 821 to 824, respectively. The outputs of the sample hold circuits 821 to 824 are added to the adders 841 to 841.
842 is used to multiply a predetermined coefficient between adjacent pixels to perform addition, and outputs of three systems are performed. The output of these three systems and the non-connection (NC) state are selected by the switch 85 and output as the switch output So. At this point in time, the signal has already been thinned out by one pixel into four pixels, but a part of the information is included by weighted addition to the pixel immediately before being thinned out.

This signal is sequentially written in the memories M1 to M120 which are composed of memory cells and switches by the write clock WCK which is thinned out once every four times as in FIG. The written signal is not a signal in which one pixel is simply thinned out to four pixels, but includes information on pixels before being thinned out by weighted addition. When the signals are sequentially read at the read clock RCK at the timing shown in FIG.
The output signal after compression shown in is output from the output terminal 86.

In this embodiment, the output pixel No.
Input pixel Nos. 1 ', 2', 3 '... 1, 2, 3 ...
Information is included, and an effect of eliminating information loss caused by thinning out pixels can be obtained.

The present invention is not limited to the above-described embodiments. For example, the memory is not limited to the semiconductor memory, and a capacitor, a CCD (Charge Coupled Device) element or the like may be used.

[0039]

As described above, according to the aspect conversion circuit of the present invention, it is possible to extremely reduce the number of memory cells required for performing the signal processing of the aspect conversion.

[Brief description of the drawings]

FIG. 1 is a block diagram for explaining a first embodiment of the present invention.

FIG. 2 is an explanatory diagram for explaining FIG. 1 more specifically.

FIG. 3 is an explanatory diagram for explaining writing and reading of the memory in FIG.

FIG. 4 is an explanatory diagram for explaining a second embodiment of the present invention.

FIG. 5 is an explanatory diagram for explaining a third embodiment of the present invention.

FIG. 6 is an explanatory diagram for explaining a fourth embodiment of the present invention.

FIG. 7 is a circuit block diagram for more specifically explaining the third embodiment.

FIG. 8 is a circuit block diagram for explaining a fifth embodiment of the present invention.

9 is a timing diagram for explaining the operation of FIG.

FIG. 10 is an explanatory diagram for explaining non-compression and compression signal processing of a conventional image signal.

FIG. 11 is a block diagram for explaining a conventional compression technique.

[Explanation of symbols]

11, 81 ... Input terminals, 12, 71 ... Write clock circuit, 13, 16 ... Switch string, 14 ... Memory, 15,
72 ... read clock circuit, 17, 86 ... output terminal,
821 to 824 ... Sample and hold circuit, 83 ... Control circuit, 841 to 843 ... Adder, 85 ... Switch.

Claims (7)

[Claims] 1. A memory composed of cells for one block when a pixel column arranged sequentially in the horizontal scanning direction is divided into a plurality of blocks, and a first for guiding input image data to each cell of the memory.
Switch row, a write clock circuit that sequentially controls opening and closing of the first switch row to sequentially store the input image data in the horizontal direction in the memory, and outputs the image data of each cell of the memory And a read clock circuit for controlling opening and closing of the second switch row in order to sequentially read the stored image data in the written order. An aspect conversion circuit, characterized in that it comprises a control means for changing the clock frequency of the write clock circuit and repeatedly controlling a cycle of reading and writing a plurality of times within one horizontal scanning time of the input image data. 2. The writing is started a fixed time earlier than the reading, the reading rate is made faster than the writing rate, and the reading is performed in the order in which the writing is performed. When the writing goes through the memory, the writing is returned to the beginning and the reading continues through the memory. Then, the number of memory cells, the read clock frequency, and the write clock frequency are set so that reading is continued at the beginning and one horizontal scan of the input image data is completed before the read cell catches up with the write cell. The aspect conversion circuit according to claim 1. 3. Input image data is thinned N times i times at a constant cycle and written to a memory, reading is started in parallel with writing immediately before one cycle of writing, and continuously read at the same cycle as writing. The number of memory cells is (N-i) / number of pixels per horizontal scanning of the input image data.
N ² times the input image in the horizontal direction (N-i) /
3. The data is compressed and output at a ratio of N.
Aspect conversion circuit described. 4. The read frequency of the memory is set to N / (N−i) times the write frequency, the read is started in parallel with the write immediately before one cycle of the write, and the number of cells in the memory is 1 horizontal scan of the input image. 3. The aspect conversion circuit according to claim 2, wherein the aspect ratio conversion circuit is configured by i / N times the number of pixels per pixel, and the input image is compressed in the horizontal direction at a rate of (N−i) / N and output. 5. A wide television displaying a television signal transmitted with an aspect ratio of 4: 3 on a full screen with an aspect ratio of 16: 9, i = 1, N = 4 and the input image is 3 / horizontally in the horizontal direction. 4. The aspect conversion circuit according to claim 3, wherein the aspect ratio conversion circuit is adapted to be compressed to 4 and output so that it can be seen in a wide television with an aspect ratio of 4: 3. 6. N sample-hold circuits for sequentially switching and holding input signals at fixed time intervals and N for outputting a plurality of outputs of the sample-hold circuits by weighted addition.
With a circuit consisting of -i weighted adders, N consecutive input data strings are converted into N-i data strings, which are used as write data in the memory, and are input without missing pixel information. 4. The aspect conversion circuit according to claim 3, wherein data is thinned out. 7. The memory cell is a capacitor or CCD
The aspect conversion circuit according to claim 1, wherein the aspect conversion circuit is configured by a charge holding unit such as an element.