JPH09167876A - Semiconductor laser and fabrication of semiconductor laser and semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To apply easily to bulk semiconductor structure by providing the upper implantation region and upper mirror of a laser structure such that they are superposed on the lower implantation region only in a specified conductive region. SOLUTION: An elongated lower implantation region 5 of n-type GaAs is formed above a lower mirror 3 and a laser structure 17 is formed of GaAs emission on the lower implantation region 5 between upper and lower AlGaAs space layers 23, 21. Subsequently, an upper implantation region 25 is formed on the laser structure 17 such that the upper implantation region 25 and an upper mirror 27 above the laser structure 17 are superposed on the lower implantation region 5 only in a specified conductive region. This structure can be applied easily to bulk semiconductor structure.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having a new semiconductor structure, which is applicable to an optical device or a transportation device, and further, in an optical device,
The present invention relates to a semiconductor laser device including a vertical cavity surface emitting laser (VCSEL).

[0002]

BACKGROUND OF THE INVENTION Most of the semiconductor structures developed for commercial or research work operate by applying an electric field to a stack of semiconductor layers. In most cases, one or more layers require contact and some carrier confinement in directions other than the growth direction of the structure.

Contacting the upper layer has the difficulty that the contact portion diffuses into the structure, forming unwanted contacts to the lower layer. The problem is that the lower layer is patterned either by so-called shallow ohmic contact or by etching or ion beam damage so that the upper layer physically contacts the lower but not electrically. Has been overcome by.

Selective contact to the lower layer can be easily made by etching the upper layer. But,
In many cases this is not an ideal solution.
Etching away the layer that contacts the underlying layer will leave an etch defect on the etch stack sidewall near where the properties of the layer will be measured. This problem is not limited to etching away layers for contact purposes, but for any purpose that requires carrier confinement, whether to confine the carriers in a fine dimension or to separate and etch a large large area. Is common to any structure of.

These etching steps are problematic for both transport and optics. For example, there are tunneling devices in which the operation of the device depends on carriers that quantum mechanically tunnel from the bound state in one layer to the state in the lower layer. Etch defects may create extra conditions for carriers to tunnel. On the other hand, in optical devices, Vertical Cavity Surface Emitting Lasers (VCSELs) are a good example of defects created by etching for contacts having a significant effect on the emission of the device.

A VCSEL is a laser, which causes resonance between mirror surfaces arranged opposite to each other above and below the active layer, not along a waveguiding layer parallel to the mirror, thereby forming a right angle with the active layer. Radiation occurs.

In principle, VCSELs offer many advantages, such as a small emission cone angle and a low threshold current that can be better coupled to optical fibers. However, this type of structure has the inherent problem that the electrical current used to energize the device must pass vertically through the dielectric stack forming the mirror. Even if the interface of the dielectric stack is graded, the relatively high resistance of the device limits the potential application of the device. Similarly, an impurity-doped dielectric stack results in greater optical loss.

To overcome the aforementioned problems, a structure utilizing lateral current injection has been proposed by JW Scott et al.
al) IEEE J. Quantum. Electron, 29 (5) pp 1295
-1308, May 1993. In this structure, the injection (or contact) layer is located outside the cavity region. The current is confined in the resonator region by one undercut of the cladding layer. However, this causes other problems.

First, in the Scott et al. Structure, the path between the peripheral implant layers channeling around the undercut causes a relatively high current density. Second, undercuts are formed by selective etching, which can cause lattice dislocations that cause dark lines. Thirdly, the precision of the undercut formation when processing the entire wafer is difficult for the control part, which causes a low yield.

By using the VCSEL structure described in GB-A-2,283,612, the drawbacks associated with undercut can be avoided. This utilizes a separation layer formed on top of the first injection layer on top of the first dielectric mirror. Then, the hole is etched to expose a part of the first injection layer, and an inclined surface is left on the separation layer. The layer structure covered with the second implantation layer, that is, the active layer and the cladding layer, is formed by regrowth of the upper portion of the patterned wafer. At that time, the second dielectric mirror is formed so as to cover the bottom of the hole, that is, directly above the portion exposed before the first injection layer.

The terms used in this specification will be briefly described below. The term "low dimensional" is used herein with the several semiconductor devices described. This term is
The present invention relates to a semiconductor device which operates by limiting carrier movement in one or more dimensions. A common way to achieve this limitation in one direction is:
It is realized by two semiconductor compounds with different band gaps, so-called heterojunctions. If the carrier is an electron, a two-dimensional electron gas (2DEG) is formed,
Two-dimensional hole gas (2DHG) if carriers are holes
Is formed. For clarity of technology used herein, a heterojunction is a junction formed between a barrier layer with multiple layers and an active layer. The terms 2DEG and 2DHG refer to a system of bound carriers in which the energy levels of the carriers in one direction are quantized to some extent. The confinement direction is not only for bound systems in which only one energy level is occupied. Similarly, the terms 1-dimensional and 0-dimensional are
A system in which two-dimensional and three-dimensional quantization is performed at least to some extent. The present invention is very useful for these low dimensional devices. However, this technique is easily applicable to more bulk semiconductor structures. An object of the present invention is to provide a semiconductor device having a novel structure. Further, it is an object of the present invention to provide a semiconductor device which can be more refined.

[0012]

According to the present invention, the following means have been taken in order to solve the above-mentioned problems. This semiconductor device is based on pattern wafer / regrowth technology,
The excellent controllability of the boundary limitation of the conductive region where the laser oscillation occurs provides a possibility of further miniaturization. Therefore,
It enables very low threshold currents to be realized, as well as lower resistance in the differential IV characteristic.

The present invention also overcomes the problems of etching by using a patterned layer. The semiconductor layer whose transport properties are to be determined forms a transfer region sandwiched between the regions (contact regions) to be contacted in the (two) conductive regions. The contacts are designed to be easily separated from the transfer area of the device so that they can be easily made as independent contacts, so that they can be easily made in the contact areas. Note that in the present invention, the conductive region extends outside the transfer region.

The present invention (Claim 1) includes a lower implantation region disposed on the lower mirror, an active layer, a laser structure formed on the lower implantation region, and a predetermined conductive region. An upper implant region above the laser structure overlapping only an upper portion of the lower implant region, and an upper mirror above the laser structure.

Usually, the basic laser structure itself comprises respective active layers bounded by upper and lower cladding layers. However, there may be more than one active layer and in fact any basic structure as known in the semiconductor laser art may be used. However, of course, since the laser device of the present invention is a VCSEL, no waveguiding layer is required.

In preferred embodiments of the device described below, the lower implant region is generally elongated and is a portion of the mesa, that is, the upper portion of the mesa region formed by selective etching of the structure containing at least one doped layer, or It is formed inside for convenience. However, a complete layer of doped regions formed on top of the lower mirror can likewise be constructed.

For example, the lower implantation region is formed by forming a lower implantation layer (doped layer) and selectively etching it to form a mesa. It can be left as a mesa, or it can be planarized by forming another layer on the mesa and then etching it until the top of the mesa is evenly exposed again. However, the formation of laser structures by regrowth directly on the mesas has the advantage of being structures that minimize lateral implantation.

The lower implant region can likewise be formed by forming a doped region in the complete semiconductor layer formed on top of the lower mirror. This is because the semiconductor layer is formed as an undoped layer or a lightly doped layer, and the ion beam doping for defining the lower conductive region and the dopant activation annealing are used to form a semiconductor layer for calculator doping in the region. Can be achieved by Alternatively, if the semiconductor layer formed on the lower mirror is formed as a doped layer and selectively damaged by the incident ion beam, only a predetermined region for functioning as the lower implantation region is damaged. It remains as an unreceived doped region. Both of these techniques can be performed either ex-situ using conventional ion masking and ion beam implanters, or in-situ using focused ion beam implanters.

Both the lower and upper implant regions are generally defined so that they extend across each other in their respective directions, eg, at approximately right angles to each other, to define a narrow predetermined conductive region through the device. It is convenient to lengthen. The upper mirror can be formed only on the substantially predetermined conductive region.

A method for manufacturing a semiconductor laser device (claim 2) comprises the following steps. (1) Forming a lower implantation region on the upper part of the lower mirror. (2) Stacking on top of the lower implant region to form a laser structure including an active layer. (3) Forming an upper implant region on the laser structure such that the upper implant region only overlaps the lower implant region of a given conductive region of the device. (4) Forming an upper mirror above the upper implant region.

The preferred embodiment is as follows. (1) The lower implantation region is formed by forming a lower implantation layer on the lower mirror and performing selective etching to form a mesa including the lower implantation region.

(2) The lower implantation region is formed by forming a doped region of the semiconductor layer formed on the lower mirror. (3) The lower implantation region is formed by forming a semiconductor layer as a doped layer and selectively damaging the lower implantation region with an ion beam so that a predetermined region remains.

(4) The lower implantation region is formed by forming a semiconductor layer as a doped layer and performing selective etching so that a predetermined region of the lower implantation region remains. (5) The lower implant region is formed by forming a semiconductor layer as an undoped or lightly doped layer and selectively doping a predetermined region to define the lower conductive region.

(6) The upper implantation region is formed by forming a doped upper implantation layer and selectively damaging it with an ion beam so that a predetermined region remains as the upper implantation region.

(7) The upper implant region is formed by forming a doped upper implant layer and selectively etching to leave the upper implant region above a predetermined region. (8) The upper implant region is formed by forming an undoped or lightly doped upper implant layer and selectively doping a predetermined region to define the upper conductive region.

The present invention (claim 3) provides a semiconductor substrate, a transfer semiconductor region, a generally elongated patterned first contact region along a first major axis, and a generally elongated pattern along a second major axis. A second patterned contact region, the first patterned contact region overlies the semiconductor substrate, the transfer semiconductor region contacts an upper surface of the first contact region, and the second contact region comprises: Contacting the upper surface of the transfer semiconductor region, the first and second contact spindles are substantially non-parallel to each other such that the second contact region overlaps the first contact region only in a predetermined region, A region is characterized in that it is sandwiched between both the first and the second contact region in a predetermined conductive region of the device.

For the avoidance of doubt, "contact area"
Means a single layer or a plurality of layers that require external contacts, and “contact layer” also refers to a layer that requires external contacts. Similarly, “transmission region” means a single layer or multiple layers in which an electric field is applied perpendicular to the plane of the layers. It is a contact layer for the layer and can form part of the transmission region. A layer “overlapping” another layer refers to a related layer that is placed directly above the other layer, whether in direct contact or separated by one or more layers. The "above" position is used with respect to the substrate below the device. Position "vertical" that refers to a layer
Means perpendicular to the plane of the layer.

To facilitate contacting the first and second contact regions, the first and second contact regions generally need to be along the first and second major axes, respectively. The contact area must extend in a direction different from the others. Therefore, the first and second
The principal axes should be substantially non-parallel to each other.
To make this clearer, the first on the surface of the substrate
The projection line of the principal axis must not be parallel to the projection line of the second principal axis on the surface of the substrate.

The present invention applies to devices which require vertical transport of a stack of layers. Here, conduction occurs between the first and second contact regions through the conductive region. The present invention also provides carrier transport within a single layer,
It is applicable to devices where the first and second contact regions modulate the conduction through this layer or deplete or induce carriers in the transfer region. In this case, it is preferable that either or both of the first and second contact regions have a Schottky gate. Such a gate may be provided by a metal layer or a highly doped semiconductor layer. It is likewise possible to combine the gate layer with the device according to the invention in which the conduction takes place between the first and the second contact region.

The contact region may be composed of one or more contact layers, and thus the present invention is such that the first contact region comprises a contact layer and the second contact region comprises a contact layer. Semiconductor device of. The first contact region does not extend all over the semiconductor substrate.

The present invention solves both the problem of carrier confinement and the problem of making independent contacts to multiple layers. In some cases it may be required to contact more than one layer and the invention extends to the above semiconductor device wherein the transfer semiconductor region comprises at least one further patterned contact region. All the first, second and further patterned contact areas are arranged such that they only overlap one another directly above a given conductive area.

In many cases, the second is
It may be convenient if the contact area is substantially perpendicular to the first contact area, and likewise it is generally preferred that the elongated portion of the contact area be substantially rectangular.

The device according to the invention limits the transfer semiconductor region in two directions other than the growth direction. If the transfer semiconductor region has a low-dimensional structure, the carriers are confined in the 0-dimensional quantum state if the region confined by the process for the initial growth is small. For this purpose, the microregions are preferably defined to 4 μm ² or less, for example on the order of 1 μm ² . This allows the creation of devices that simply operate using the single electron effect of the method. Therefore, in some cases, the invention provides that the area of a given conductive region perpendicular to the growth direction defined by the contact region is 1 μm.
It is preferable for the above semiconductor device to be of the order of m ² .

In many cases it is necessary for a metal layer to be provided on the semiconductor layer, whereby the second contact region is preferably a metal layer. In many cases, it is preferred that at least one of the first and second contact regions is in electrical contact with the doped semiconductor layer. Therefore, at least one of the first and second contact regions needs to include a doped semiconductor layer. This layer is a highly doped layer. For the purposes of carrier induction and contact, it is preferred that the transfer region is a doped layer.

When the invention comprises a doped layer, it is preferred if the layer comprises alternating conductivity type portions. This is advantageous for limiting or contacting the structure. For example, if the device is made of a doped layer in the transfer region, this layer may be made so that the portion of the doped layer in the conductive region is of opposite conductivity type to the adjacent portion of the doped layer. Similarly, one or both of the contact regions may be fabricated so that the portion of the doped layer directly stacked on top of or below the conductive region is of the opposite conductivity type to the adjacent portion of the doped layer. Changing the conductivity type of the doped layer and the first and second contact regions in the transfer region in the manner described above provides confinement to the conductive region. A voltage may be applied to the adjacent portion of the opposite conductivity type so that it can operate as a side gate or modulate the confinement potential of the conductive region. The present invention comprises a plurality of doped layers with portions of alternating conductivity type.

Varying the conductivity type of either or both of the contact regions also has advantages with respect to contact and gate placement. Ohmic contacts of a particular conductivity type only electrically contact materials of the same conductivity type.
Therefore, by changing the conductivity type of the second contact so that the portion immediately above the conductive region has the opposite type to that of the adjacent portion, the second contact region is formed on the second contact region which makes contact with only a specific region. A large area ohmic contact is possible. This technique may be used to contact the first contact region as well, for example, the first contact region may be part of the first contact region and may have the same conductivity on the heavily doped substrate or as the first contact region. It may be formed on the mold layer. The highly doped layer or substrate only makes electrical contact with the portion of the first contact region of the same conductivity type.

A particularly useful technique for changing the conductivity type within a doped layer is whether the doped layer comprises an amphoteric dopant. For example, silicon in the GaAs lattice is an amphoteric dopant. Amphoteric dopants can be incorporated as either n-type or p-type dopants depending on the growth conditions and the crystallographic orientation of the growth surface. Therefore, the patterning of the layer exposing the inclined surface can be incorporated as both an acceptor and a donor in the same layer.
If a change in conductivity type of the first contact region is required due to the use of an amphoteric dopant, it is preferred whether any surface of the substrate comprises a sloped surface or the device further comprises a relief area such that the surface has a sloped surface. , The patterned first contact region is stacked on the relief region, and the relief region is stacked on the substrate. For clarity, the relief area is one or more layers stacked on top of the substrate. The first contact area is
Stacked over the relief area. The relief region comprises a doped or undoped layer.

If it is necessary for the doped layer in the transfer region or the second contact region to have portions of different conductivity type, it is preferred that the first contact region has inclined sidewalls. The conductivity type of the part of the doped layer comprising the amphoteric dopant depends on the crystallographic orientation of the part of the layer. Thus, layer patterning may define boundaries of opposite conductivity type portions in the next grown layer, thereby providing a simple self-alignment technique.

At least one of the first and second contact regions may be provided with a single conductivity type doped layer in addition to the doped layer having opposite conductivity type portions. The single conductivity type doped layer may include a non-amphoteric dopant,
Amphoteric dopants may be included or may be formed under different growth conditions such that the dopants are incorporated in a similar manner throughout the layer. For example, the second contact region may include a doped layer having alternating conductive portions such that the contact portion formed directly on the conductive region is of a different conductivity type than the adjacent portion. The contact area is
It may further comprise a layer of opposite conductivity type and a highly doped layer of the same conductivity type as the adjacent contact portion. The highly doped layer makes an electrical connection to the contact. The ohmic contact may be provided in a highly doped layer remote from the conductive region, the doped layer having a portion of opposite conductivity type preferably comprising an amphoteric dopant. However, techniques such as ion implantation are used to the same effect.

The present invention can be applied to an optical device or a transportation device. For example, carrier transport through a layer defines the operation of the device, a tunneling device, or a light-emitting diode that utilizes recombination of carriers of opposite polarity in the transfer semiconductor region, in some cases in the transfer region. It may be necessary to bias the contact layer against the layer, but this is possible if at least one ohmic contact is provided in the transfer semiconductor region.

It is possible to dope the first and second contact regions with opposite conductivity types, ie n and p, for example for the production of semiconductor laser structures. The device according to the invention can therefore also be realized if the layer with the first and second contact regions is highly doped and of opposite conductivity type.

In many cases, it is preferred that the confined transfer semiconductor region be a low dimensional structure. One way to achieve this is that the transmission semiconductor region is further provided with a barrier layer and an active layer, provided by the semiconductor device according to the invention. In some cases carriers may need to be provided to the active layer,
This is possible in the device according to the invention if the barrier layer is doped.

The above-mentioned high mobility in the active layer is possible if the transfer semiconductor region is provided with a modulation-doped heterostructure, which means that the barrier layer provided in the transfer semiconductor layer is a doped layer and an active layer. Is possible in the device according to the invention, which is a modulation-doped layer consisting of an undoped spacer layer in contact with.

The transfer region of the present invention may also comprise an active layer interspersed between the two barrier layers, the first contact region forming the emitter and the second contact region forming the collector. Electrons can be injected from the emitter to the collector across the transfer region. At some emitter / collector bias, an increase in tunnel peak is observed. This means that the device may be configured to operate as a resonant tunneling diode. The transfer region of the present invention may also include more than two barrier layers.

The semiconductor layer structure of the present invention readily lends itself to an array of devices. This can simply be achieved if the first and second contact regions are patterned to form a series of parts. These portions can be arranged such that an array of regions where the contact layers are stacked on top of each other is formed. Therefore, the present invention has the structure as described above, which allows an array of tunnel diodes to be easily manufactured. This structure also allows the formation of an array of high mobility electron gas puddle. If the conductive region is small enough, a zero-dimensional electronic state is formed.

[0046]

Embodiments of the present invention will be described with reference to the drawings. In FIG. 1, the first part of the lower mirror 3 is formed.
A VCSEL device 1 comprising a dielectric stack is shown. On the upper part of the lower mirror 3, an elongated n-type GaAs lower implantation region 5 extending perpendicularly to the paper surface is formed. This shape is best seen in the plan view of FIG. The lower implantation region 5 is formed by causing ion beam damage to the regions 7 and 9 adjacent to the n-doped layer 11 formed by the lower mirror 3. Mirror 3 is G in this case
aAs / AIAs, but with alternating layers 13, 15 etc. staggering different dielectric constants.

On the upper part of the lower implantation region 5, In _0.2 Ga _0.8 As / Ga composed of three parts sandwiched between the lower and upper AIGaAs space layers 21 and 23, respectively.
A laser structure 17 including an As emission region 19 is formed. An elongated upper p-type GaAs implant region 25 is formed in the upper portion of the laser structure 17 from left to right as shown in FIG. 1 and as best seen in the plan view of FIG. This is caused by causing ion beam damage to the adjacent region of the p-type GaAs layer or p-type Ga.
It may be formed in the same manner as the lower implantation region 5 by etching As.

As can be seen in FIG. 2, the implant regions 5 and 2
The conductive area of the device between 5 is defined only by this overlap area. An upper mirror 27 is formed on the upper portion of the same structure as the lower mirror 3, but the period is reduced so that the beam goes out through the mirror 27 and is deflected. In order to radiate from the substrate side,
Mirrors with more cycles grow on the top than on the bottom of the device
Is deposited.

A second embodiment of the semiconductor laser device 31 according to the present invention is shown in FIGS. The device of this embodiment is similar to the device of the first embodiment. A lower implantation region 35 composed of a mesa 37 formed by selective etching of an n-type GaAs layer is formed on the lower mirror 33 having the same structure as the lower mirror 3 of the first embodiment. This lower injection region 35 extends in a direction perpendicular to the plane of the drawing, as better seen in the plan view of FIG.

In _0.2 Ga sandwiched between the respective AlGaAs lower and upper spacer layers 43 and 45.
_A laser structure 39 consisting of _0.8 As / GaAs emitting region 41 is formed by re-growth of the top of the mesa.

The p-type GaAs upper implantation region 47 is formed in the upper part of the laser structure 39 and extends from the left to the right in FIG. 4, as can be seen from FIG. The conductive region (emissive region) through the device is defined by the layers of the device sandwiched between the overlap regions of the lower implant region 35 and the upper implant region 47. The upper mirror 49 has the same structure as the upper mirror 27 of the first embodiment and is formed on the conductive region. Implantation between the n-type GaAs mesa sidewalls and p-type GaAs can be minimized by various techniques.

If the mesa side wall 51 is the (X11) B plane, the growth during the regrowth process is faster on the side wall ((1
(Compared to the (00) plane, it is about 1.2 times larger than the (311) B plane)
right. At that time, the p-type GaAs upper implantation region 47 and n
The separation between the bottom implant region 35 of type GaAs will be greater on this surface 51 than on the top of the mesa. Therefore,
Whatever bias is applied, the sidewall current density will be less than at the top of the mesa. If the side wall is (X1
1) If it is the A-face and the doping order is reversed, control of the silicon doping in this face is obtained by controlling the As pressure during growth. By adjusting this pressure during growth of the upper implant region 47, the doping profile of the mesa sidewalls can be pnpn and only n above the (100) region. In this way, the upper implant region 47 becomes a lower implant region 3 in the sidewall region.
Separated from 5. Sidewall currents can be minimized as well by a vertical steep mesa etch that reduces the overlap area.

A third embodiment of the semiconductor laser device 51 according to the present invention is shown in FIGS. The device of this embodiment is also similar to the first embodiment. First
Lower mirror 53 having the same structure as the lower mirror 3 of the embodiment
As shown in FIG. 6, an n-type GaAs lower implantation region 55, which is elongated and extends perpendicularly to the paper surface, is formed in the upper part of the. The lower implantation region 55 is formed by the selective ion beam implantation into the GaAs layer 57 above the lower mirror 53.
It is formed as a mold-doped region.

The same laser structure 57 as the laser structure 17 of the first embodiment is formed on the lower implantation region 55. An upper implantation region 59 and an upper mirror 61 are formed on the laser structure 57.
These are the same as the upper implantation region 25 and the upper mirror 27 of the first embodiment, respectively.

The semiconductor devices in the following embodiments can be made of a wide range of compounds, but here, Ga is used.
The structure based on As is described. Described in a device having a highly doped first contact layer. There are many methods applied to doping the contact layer.
However, here the doping is provided by an amphoteric dopant.

FIG. 7 is a diagram showing a fourth embodiment of the semiconductor device according to the present invention. According to FIGS. 7A to 7C, the highly-doped n ⁺ GaAs layer 3 is made of semi-insulating GaAs.
It is formed on the substrate 1. Highly doped n ⁺ GaAs layer 3
Are selectively etched to form the patterned first contact layer 5. The patterned first contact layer 5 is patterned within the substantially rectangular portion. The etching is chosen such that inclined surfaces 7, 9 are formed on the sidewalls of the patterned first contact layer 5. FIG. 7 (b)
Shows the A cross section of FIG. From FIG. 7B, a long inclined surface 9 can be seen along the long side wall of the patterned first contact layer 5. The angle that the long inclined surface 9 makes with the plane of the substrate 1 can be finely controlled using wet or dry etching. FIG.
It is a B sectional view of (a). Short slopes 7 are seen along the short sidewalls of the patterned first contact layer 5. The patterned first contact layer 5 may be a single semiconductor layer or a plurality of semiconductor layers.

FIG. 8 shows the structure after the second growth step following FIG. According to FIG. 8, the plurality of semiconductor layers 11 are
It is formed on the substrate 1 and the patterned first contact layer 5 so as to be in contact with and adjacent to both the substrate 1 and the patterned first contact layer 5. The plurality of semiconductor layers 11 follows the relief of the previous pattern layer. The second contact layer 13 is formed on and in contact with and adjacent to the plurality of semiconductor layers 11.

FIG. 9 shows the structure after the second etching, which is subsequent to FIG. 8, in which the second contact layer 13 is etched so as to expose the plurality of semiconductor layers 11. The sidewall profile of the etching is such that no layer is formed over the entire top of the structure above the second contact layer,
It doesn't matter here. The multiple semiconductor layers 11 are therefore sandwiched between the first and second contact layers 5, 13 only in the restricted region 21. Here, the etching depth depends on the device and in some cases the second depth.
In etching the contact layer 13, it is necessary to remove some layers of the semiconductor layers 11.

According to FIG. 10, the first ohmic contact 31 is
The asperities 17 of the first contact layer formed on the first contact layer 5 can be seen through the successively grown layers. First
The first ohmic contact 31 is also disposed on the surface of the plurality of semiconductor layers 11 if there is no layer in the plurality of semiconductor layers 11 to make electrical contact with the ohmic contact 31. The first ohmic contact 3 through the plurality of semiconductor layers 11
If it is not desired to diffuse 1's, the plurality of semiconductor layers 11 may be etched so that the first ohmic contact 31 may be disposed on the first conductive layer. The problem due to etching defects from the etching process is not a problem here because the semiconductor layers are etched far enough away from the confinement region 21 where the layer properties are studied. Etching bumps are therefore not a problem in this case.

The contact to the second contact layer takes two forms, in many cases the second contact layer 1
The upper layer of 3 is a metal layer 35. This upper metal layer 35
May be formed using a process different from that of the other layers which are also part of the second contact layer. Upper metal layer 35
No anneal ohmic contact into the structure that contacts the is required. The second ohmic contact 33 may be provided on the second contact layer 13 if the upper layer is not metal. The actual second ohmic contact 33 often contacts one layer in the plurality of semiconductor layers 11. Here, the upper metal layer 35 is not defined. Only two contacts are shown in any one layer here for clarity, but in practice any number of contacts may be provided. For example, the contact layer may be "Hall Bar
) ”And may have four terminal contacts.

There may be more than one contact layer to apply the invention to some structures. FIG.
It shows how such a structure is realized according to the invention.

In FIG. 11, the first contact layer 41 is formed on the semiconductor substrate 1, and the first contact layer 41 is patterned in a substantially elongated portion. The first inner contact layer 43 is formed on the first contact layer 41, and is patterned in a substantially elongated portion oriented substantially perpendicular to the first contact layer 41.
The second internal contact layer 45 is the first internal contact layer 4
3 and are patterned in a substantially elongated portion that is not parallel to the first contact layer 41 and the first inner contact layer 43. Second contact layer 47
Are formed to be stacked on the second internal contact layer 45, and the first contact layer 41 and the first internal contact layer 4 are formed.
3 and the second inner contact layer 45 is patterned in a substantially elongated portion which is not parallel. The plurality of semiconductor layers are scattered and arranged between any of the contact layers 41, 43, 45 and 47. The plurality of semiconductor layers, the first and second internal contact layers 43 and 45, are enclosed between the first and second contact layers 41 and 47 in only one region as shown. The ohmic contact 61 has contact layers 41, 4
Easy to attach to all 3, 45, 47.

Similar to the above, it may be necessary to form an array of enclosed areas of the present invention. FIG.
Shows such a structure, the process steps of which refer to FIGS. 7 (a) to 8 (b), except that here the first contact layer constitutes an array of elongated portions 61. Explained in detail. Similarly, since the second contact layer 63 also constitutes an array with elongated portions, an array of regions in which the semiconductor layer is limited between the first and second contact layers is formed.

Although many methods are available for patterning the contact layers for the device of the present invention, the method described above is for the layers contained within a plurality of semiconductor layers interspersed between the contact layers. Allows the use of amphoteric dopants in the doping. The formation of layers with amphoteric dopants on different crystal planes may be such that the conductivity type of the doping of the layers is different on the part of the layer formed on the inclined plane relative to that formed on the plane of the substrate. Means

FIG. 13 shows a modification of the configuration of the device. The device is similar to that of FIG. The main difference here is the orientation of the inclined surface with respect to the plane of the substrate 1. The angle the inclined surface makes with the substrate 1 allows for variations in doping on the relief of the patterned first contact layer 5. Only the profile of the long ramp 9 is shown. This is feasible if any doping in the next layer is provided with an amphoteric dopant, namely silicon. For example, the crystal orientation of the substrate 1 is (100)
If the tilted surface 9 is a (311) A surface 71, the growth of the next layer by molecular beam epitaxy (MBE) with a silicon dopant using standard conditions is Doping is n type, (311)
Doping the A-face 71 results in p-type. The change in doping on different planes depends in part on the growth conditions, and when grown at high As pressure, the doping becomes n-type across the relief of the patterned first contact layer 5.

Another example of using amphoteric dopants to create the structure is shown in FIG. Here, the plurality of semiconductor layers 1
1 grows as described with reference to Figures 8 (a) to 8 (c). The second contact layer 13 includes two layers. Amphoteric doped layer 81 and highly doped contact layer 8
3. The amphoteric doped layer 81 contains an amphoteric dopant and is of p type on the (311) A plane 71 and n type on the substrate plane, that is, on the (100) plane. After that, the highly doped contact layer 83 is replaced with the amphoteric doped contact layer 8.
Growing on top of 1. The highly doped contact layer 83 is
Amphoteric dopants are either grown under high As pressure or doped with non-amphoteric dopants such as n-type doped on top of the overall structure. As a result, the amphoteric doped contact layer 81 having the isolated n-type region self-aligned with the conductive region 21 is formed. The isolated n-type region contacts the highly-doped contact layer 83. The present invention is not limited to the above embodiments of the present invention, and it is needless to say that various modifications can be made without departing from the spirit of the present invention.

[0067]

As described in detail above, according to the present invention,
It is possible to provide a semiconductor device having a new structure and capable of further refinement.

[Brief description of the drawings]

FIG. 1 is a sectional view of a first embodiment of a semiconductor laser device according to the present invention.

FIG. 2 is a plan view of the device according to the first embodiment.

FIG. 3 is a sectional view of a semiconductor laser device according to a second embodiment of the present invention.

FIG. 4 is a plan view of the second embodiment.

FIG. 5 is a sectional view of a third embodiment of a semiconductor device according to the present invention.

FIG. 6 is a plan view of the third embodiment.

FIG. 7A is a plan view of the semiconductor device according to the present invention after the first growth and etching steps. (B) is (a)
A sectional view of the semiconductor device shown in FIG. (C) is B sectional drawing of the semiconductor device shown in (a).

FIG. 8A is a plan view of the semiconductor device according to the present invention shown in FIG. 1 after the second growth step. (B) is (a)
A sectional view of the semiconductor device shown in FIG. (C) is B sectional drawing of the semiconductor device shown in (a).

9A is a plan view of the semiconductor device according to the present invention shown in FIG. 4 after the second etching. FIG. (B) is A sectional drawing of the semiconductor device shown to (a). (C) is B sectional drawing of the semiconductor device shown in (a).

FIG. 10 is a plan view of a semiconductor device according to the present invention after the device has been fully processed.

FIG. 11 is a schematic diagram of a device according to the invention with four independent contact layers.

FIG. 12 is a schematic diagram of a device according to the present invention having two contact layers patterned to form an array.

FIG. 13 is a semiconductor device according to the present invention shown in FIG. 8 showing regions of varying conductivity type.

FIG. 14 shows a semiconductor device according to the invention in which two layers, one of varying conductivity type and the other of single conductivity type, are provided as a second contact layer.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 ... Semiconductor device 3 ... Lower mirror 5 ... Lower injection area 7, 9 ... Adjacent area 13, 15 ... Alternate layer 17 ... Laser structure 19 ... GaAs emission area 21 ... Lower spacer layer 23 ... Upper spacer layer 25 ... Upper injection area 27 ... Top mirror

Claims (4)

[Claims] 1. A lower implant region disposed above the lower mirror, a laser structure including an active layer formed above the lower implant region, and a predetermined conductive region above the lower implant region. A semiconductor laser device comprising: an upper implantation region on the upper portion of the laser structure that overlaps the upper structure; and an upper mirror on the upper portion of the laser structure. 2. (1) Forming a lower implant region on top of the lower mirror; (2) Forming a laser structure including an active layer stacked on top of the lower implant region; and (3). Forming an upper implant region on top of the laser structure such that the upper implant region only overlies the lower implant region at a predetermined conductive region of the device; and (4) forming an upper mirror above the upper implant region. Steps to
A method for manufacturing a semiconductor laser device, comprising: 3. A semiconductor substrate and a transmission semiconductor region.
), A patterned first contact region that generally extends along a first major axis, and a patterned second contact region that generally extends along a second major axis. A first contact region is stacked on the semiconductor substrate; the transfer semiconductor region contacts an upper surface of the first contact region; and the second contact region contacts an upper surface of the transfer semiconductor region, The first and second spindles are non-parallel to each other such that the second contact region overlaps the first contact region only in a predetermined region, and the transfer semiconductor region is in the predetermined conductive region of the device. 1. A semiconductor device characterized by being sandwiched between both 1 and the second contact region. 4. A first contact region is formed on a semiconductor substrate, the first contact region is patterned by etching so that a sloped surface is formed on an etched sidewall, and a transfer semiconductor is formed on the first contact region. A region is formed, a second contact region is formed on the plurality of semiconductor layers, and the second contact region is formed by etching so that the second contact region overlaps the first contact region only in a predetermined conductive region. A method for manufacturing a semiconductor device, which comprises patterning.