JPH09167149A - Microcomputer system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To realize a high speed operation without enlarging a bus driver and to reduce power consumption in data transfer in a microprocessor system. SOLUTION: A microprocessor bus 4 to which a microprocessor 1, ROM2 and RAM3 are connected, and an I/O bus 8 to which an input/output port 5, timer 6 and SIO7 are connected are provided. A bus connection circuit 9 controlling the connection/separation of both the buses is provided between both the buses. The bus connection circuit 9 connects both the buses based on a data access signal D showing the access of the input/output port 5, timer 6 or SIO7, a read signal R or a write signal W, which are outputted from the microprocessor 1.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a microcomputer system (including a one-chip microcomputer) in which a microprocessor, ROM, RAM and various peripheral circuits transfer data via a data bus.

[0002]

2. Description of the Related Art Conventionally, a microprocessor and a plurality of peripheral circuits (including ROM and RAM) are all connected to the same data bus to transfer data.

A conventional configuration is shown in FIG. In the figure, 2
1 is a microprocessor, 22 is a ROM, and 23 is an RA
M, 24 are input / output ports, 25 is a timer, 26 is SIO
(Serial input / output interface), all connected to the same data bus 27. Incidentally, 28 is a read signal line, and 29 is a write signal line.

[0004]

The data bus 27 is normally in a floating state except during access. In this case, the bus driver needs to drive the data bus to the HIGH or LOW state for data transfer, and there is a problem that the size of the bus driver must be increased if the data bus length becomes long.

The data bus is precharged at a timing other than data access, and at the time of data transfer, L
In the HIGH state, a precharge bus system that uses the charge of the bus is also used in the HIGH state without performing a bus driver that drives only the OW state and drives into the HIGH state. When the length becomes long and the wiring load becomes large, the size of the bus driver for driving to the LOW state must be increased.

As described above, in the conventional technique, a system including a large number of peripheral circuits and having a long bus wiring length,
Alternatively, it is necessary to increase the size of all bus drivers in a system with a high bus access speed. Therefore, for example, even if an attempt is made to reuse a previously designed peripheral macroblock, there is a situation in which it cannot be done and all the macroblocks have to be redesigned. Further, when the size of the bus driver is increased, there is a problem that the current consumption also increases.

The present invention has been made to solve the above-mentioned conventional problems, and in a microcomputer system having an increased bus wiring length or a system having an increased bus access speed, the size of a bus driver is increased. It is intended to provide means for enabling high-speed operation and reducing current consumption without increasing the power consumption.

[0008]

The current consumption and operating speed in a data bus depend on the total wiring length of the bus, that is, the load capacity of the bus. The present invention shortens the bus length driven by the bus driver without changing the physical wiring length,
It is intended to reduce current consumption and speed up the operation.

The present invention according to claim 1 has a first bus to which a microprocessor, ROM, and RAM are connected, and a second bus to which peripheral circuits other than the ROM and RAM are connected. Between the first bus and the second bus, there is a bus connection circuit for controlling connection / separation of the both buses, and the bus connection circuit is a signal output from the microprocessor and indicating access to the peripheral circuit. According to the above configuration, the first bus and the second bus are connected to each other.

According to the present invention, the frequency is usually
Extremely high RO compared to the access frequency of other peripheral circuits
When accessing M or RAM, the wiring length of the bus is shortened, that is, the bus length of the bus driver of the microprocessor or the output buffer (bus driver) of the ROM or RAM is shortened. It is possible to speed up the operation and reduce the current consumption without increasing the size.

When the peripheral circuits other than the ROM and the RAM are accessed, the wiring length of the bus is basically the same as the conventional one. However, even in this case, the bus connecting circuit also has a buffer for driving the bus. With the structure having the function, the operation speed can be increased without increasing the size of the microprocessor or the bus driver of the peripheral circuit.

The present invention according to claim 2 provides a first bus to which a microprocessor, a ROM and a RAM are connected, and a second bus to which a first portion of a peripheral circuit group other than the ROM and the RAM is connected. A third bus to which the second part of the peripheral circuit group is connected, further comprising the first bus and the second bus.
First control for connecting / disconnecting both buses to and from the bus
A bus connection circuit, and a second bus connection circuit between the first bus and the third bus for controlling connection / separation of the two buses, wherein the first bus connection circuit is the microbus. The second bus connection circuit is configured to connect the first bus and the second bus by a signal output from the processor, the signal indicating access to the first portion, and the second bus connection circuit outputs the second bus output from the microprocessor. It is characterized in that the first bus and the third bus are connected by a signal indicating access to a part.

According to the present invention, since the bus wiring length is shortened even when the peripheral circuits other than the ROM and the RAM are accessed, that is, the bus driven by the bus driver of the microprocessor or the bus driver of the peripheral circuit is driven. Since the length is shortened, the operation speed and current consumption can be reduced without increasing the size of the bus driver.

Also in the second aspect of the present invention, by providing the first and second bus connection circuits with the buffer function, it is possible to further speed up the access to the peripheral circuits other than the ROM and the RAM. It is a thing.

[0015]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram of an embodiment of the present invention (claim 1).

In the figure, 1 is a microprocessor, 2
Is a ROM (program memory), 3 is a RAM (data memory), and these are connected to a microprocessor bus (data bus) 4. Reference numeral 5 is an input / output port, 6 is a timer, and 7 is an SIO (serial input / output interface). These are I / O buses (data buses).
8 is connected. A bus connection circuit 9 is provided between the microprocessor bus 4 and the I / O bus 8 to control connection / separation of the buses 4 and 8. Regarding the address bus, the microprocessor 1,
ROM2, RAM3, input / output port 5, timer 6 and S
IO7 are all connected to the same address bus (not shown).

Reference numeral 10 is a read signal line for transmitting the read signal R, and 11 is a write signal line for transmitting the write signal W. Reference numeral 12 denotes a precharge signal line to which the precharge signal P output from the microprocessor 1 is transmitted, and the precharge signal P transmitted via the signal line 12 is provided inside the bus connection circuit 9. The precharge transistor (P-channel MOS transistor) being turned on is turned on, and the above two buses, that is, the microprocessor bus 4 and the I / O bus 8 are precharged to the HIGH state.

Reference numeral 13 is a peripheral circuit other than the ROM 2 and the RAM 3, that is, the input / output port 5, the timer 6 or the SIO.
7 is a data access signal line through which the data access signal D output from the microprocessor 1 is transmitted at the time of access 7.

The bus connection circuit 9 connects / disconnects the microprocessor bus 4 and the I / O bus 8 based on the data access signal D and the read signal R and the write signal W.
When the read signal R or the write signal W is being output and the data access signal D is being output, the above two buses are connected. Otherwise, both are connected. Separate the bus.

FIG. 3 shows an example of the configuration of the bus connection circuit 9 (for one bit).

In the figure, 4 is a microprocessor bus, 8 is an I / O bus, 31 and 32 are turned on based on the precharge signal P (L level), and the microprocessor buses 4 and 4 respectively. This is a precharge P-channel MOS transistor for precharging the I / O bus 8 to a HIGH state. 33 is an OR gate that receives the read signal R and the write signal W as input;
Is a NAND gate having the output of the OR gate 33 and the data access signal D as its inputs. When the output of the NAND gate is the connection signal S and the connection signal is at the LOW level, the microprocessor bus 4 and the I / O bus 8 are connected, while when the connection signal is at the HIGH level, both The buses are separated. Reference numerals 35 to 38 are circuits provided for the above control, and 35 is a NOR gate having the I / O bus 8 and the connection signal S as its inputs.
The output of the NOR gate 35 is input to its gate 36, and its source and drain are N-channel MOS transistors connected to the microprocessor bus 4 and the ground potential, respectively. Further, 37 is a NOR gate having the microprocessor bus 4 and the connection signal S as its inputs,
The output of the NOR gate 37 is input to its gate 38, and its source and drain are N-channel MOS transistors connected to the I / O bus 8 and the ground potential, respectively.

When the data access signal D is not output (when accessing the ROM or RAM), the NAND gate 3
The output of 4 (connection signal) becomes HIGH level. Therefore, NOR gates 35 and 37 are inactive,
Both buses are separated. That is, a bus driver (output buffer) for a microprocessor or ROM, RAM
Need only drive the microprocessor bus portion. The operation timing chart at this time is shown in FIG.

On the other hand, the data access signal D is output (when accessing the input / output port, the timer and the SIO),
In addition, during the period when the read signal R or the write signal W is being output, the output of the NAND gate 34 (connection signal)
Becomes LOW level, the NOR gates 35 and 37 become active, and both buses are connected. At this time, the NOR gate 35 and the N-channel MOS transistor 3
6, or NOR gate 37 and N-channel MOS transistor 38 function as a bus buffer,
Higher speed is achieved as compared with the case where the microprocessor bus and the I / O bus are simply connected. The operation timing chart at this time is shown in FIG.

The operation will be described in more detail below.

When the microprocessor 1 reads the instruction code from the ROM 2, the ROM address is first output. At the same time, the data access signal D becomes LOW (inactive), the precharge signal P for precharging the bus becomes LOW, and each bus is charged to the HIGH state. Next, when the precharge signal P is HI
It becomes GH and ends charging. Finally, read signal R
Is output, and data (command code) is stored in ROM during this period.
2 is output. Since the data access signal D is LOW regardless of the value of the data output from the ROM,
The connection signal becomes HIGH, the N-channel MOS transistor 38 for driving the I / O bus 8 LOW does not turn on, and the value of the microprocessor bus 4 is the I / O bus 8
Not transmitted to (Fig. 4).

Even when the microprocessor 1 reads the data of the timer 6 of the peripheral circuit, the read signal R is HIG.
When it becomes H, the data is output from the timer 6 to the I / O bus 8. At this time, since the data access signal D is HIGH, the connection signal becomes LOW, and when the data output from the timer 6 is LOW, the I / O bus 8 becomes LOW and the microprocessor bus 4 is also driven LOW. (By NOR gate 35 and N-channel MOS transistor 36). When the value of the timer output is HIGH, the N-channel MOS transistor 36 that drives the microprocessor bus 4 LOW does not turn on and the microprocessor bus 4 becomes HIGH (FIG. 5).

This is the end of the description of the first embodiment.

Next, a second embodiment (claim 2) of the present invention will be described.

FIG. 6 is a block diagram of the same embodiment.

In the figure, 61 is a microprocessor,
62 is a ROM (program memory), 63 is a RAM (data memory), and these are connected to a microprocessor bus (data bus) 64. Further, 65 is a first input / output port, 66 is a timer, 67 is an SIO (serial input / output interface), and these are the first I / O.
It is connected to a bus (data bus) 68. A first bus connection circuit 69 is provided between the microprocessor bus 64 and the first I / O bus 68 to control connection / separation of the buses 64 and 68. Further, 70 is a second input / output port, 71 is an A / D conversion circuit, and 72 is PWM.
(Pulse width conversion circuit), which are connected to the second I / O bus (data bus) 73. A second bus connection circuit 74 is provided between the microprocessor bus 64 and the second I / O bus 73 to control connection / disconnection of the buses 64 and 73. Regarding the address bus, the microprocessor 61, the ROM 62, the RA
M63, first input / output port 65, timer 66, SIO6
7, second input / output port 70, A / D conversion circuit 71 and P
The WMs 72 are all connected to the same address bus (not shown).

Reference numeral 75 is a read signal line for transmitting a read signal R, 76 is a write signal line for transmitting a write signal W,
Reference numeral 77 is a precharge signal line to which the precharge signal P is transmitted.

Reference numeral 78 is a data access signal line to which the data access signal D output from the microprocessor 61 is transmitted when accessing peripheral circuits other than the ROM 62 and the RAM 63. Reference numeral 79 is a first address decode signal line to which the first address decode signal A ₁ output from the first input / output port 65 and the like is transmitted. For example, the address output from the microprocessor 61 is the first input / output port. When accessing the address 65, the first input / output port 65 decodes the address and outputs the first address decode signal A ₁ to the first address decode signal line. The same applies to the other timers 66 and SIO 67. The address output from the microprocessor 61 is the first input / output port 65 and the timer 66.
If neither SIO 67 nor SIO 67 is accessed, no first address decode signal A ₁ is output. Reference numeral 80 denotes a second address decode signal line to which the second address decode signal A ₂ output from the second input / output port 70 or the like is transmitted. For example, the address output from the microprocessor 61 is the second input / output port. 70
When accessing the address, the second input / output port 70 decodes the address and outputs the second address decode signal A ₂ to the second address decode signal line. The same applies to the other A / D conversion circuits 71 and the PWM 72. When the address output from the microprocessor 61 does not access any of the second input / output port 70, the A / D conversion circuit 71, and the PWM 72, no second address decode signal A ₂ is output. .

The first bus connection circuit 69 is based on the data access signal D, the first address decode signal A ₁ , the read signal R and the write signal W, and the microprocessor bus 64 and the first I / O bus 68. Control of connection / separation of the read signal R or the write signal W.
Is output, and the data access signal D and the first address decode signal A ₁ are output,
The above two buses are connected, and in other cases, the two buses are separated. The same applies to the second bus connection circuit 74, except that the first address decode signal A ₁ is replaced with the second address decode signal A ₂ .

The first and second bus connection circuits 69 and 7
FIG. 7 shows a configuration example of 4 (one bit).

An OR gate 39 which receives the first or second address decode signal A ₁ or A ₂ is added, and the output thereof is added to the input of the NAND gate 34. It is the same.

When the microprocessor 61 reads the instruction code from the ROM 62, the address is first output. At the same time, the data access signal D becomes LOW and the precharge signal P for precharging the bus
Goes LOW, and each bus is charged to the HIGH state. Next, the precharge signal P becomes HIGH, ending the charging. Finally, the read signal R is output, and during this period, the data (command code) is output from the ROM 62. Since the data access signal D is LOW regardless of the value of the data output from the ROM, the connection signals of the first bus connection circuit 69 and the second bus connection circuit 74 are HI.
It becomes GH, and the first I / O bus 68 and the second I / O bus 73
N-channel MOS transistor 38 for driving LOW is not turned on, and the value of microprocessor bus 64 is not transmitted to first and second I / O buses 68 and 73.

When the microprocessor 61 reads the data of the timer 66 of the peripheral circuit, when the address of the timer is output, the timer 66 decodes the address and the first address decode signal becomes active and the read When the signal R becomes HIGH, the timer outputs data to the first I / O bus 68. At this time, since the data access signal D is HIGH, the connection signal of the first bus connection circuit 69 is LOW, and when the data output from the timer 66 is LOW, the first I / O bus 68 is LO.
W, the microprocessor bus 64 is also driven LOW. When the value of the timer output is HIGH, the N-channel MOS transistor 36 that drives the microprocessor bus 64 LOW does not turn on, and the microprocessor bus 64 becomes HIGH. At this time, the second I / O
Since the second address decode signal A ₂ from the peripheral circuit connected to the bus 73 is not activated, the connection signal of the second bus connection circuit 74 is HIGH, and therefore the second I / O bus 73 is micro. It is not connected to the processor bus 64.

[0039]

As described in detail above, according to the present invention, high-speed operation can be achieved without increasing the bus driver size, and power consumption can be reduced. Is.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of a first embodiment of the present invention.

FIG. 2 is a configuration diagram of a conventional microprocessor system.

FIG. 3 is a configuration diagram of a bus connection circuit according to the first embodiment.

FIG. 4 is an operation timing chart of the first embodiment.

FIG. 5 is an operation timing chart of the first embodiment.

FIG. 6 is a configuration diagram of a second embodiment of the present invention.

FIG. 7 is a configuration diagram of a bus connection circuit according to the second embodiment.

[Explanation of symbols]

 1,61 Microprocessor 2,62 ROM 3,63 RAM 4,64 Microprocessor bus 5 Input / output port 6,66 Timer 7,67 SIO 8 I / O bus 9 Bus connection circuit 13 Data access signal line 65 First input / output Port 68 First I / O bus 69 First bus connection circuit 70 Second input / output port 71 A / D conversion circuit 72 PWM 73 Second I / O bus 74 Second bus connection circuit 78 Data access signal line 79 First address decode signal Line 80 Second address decode signal line

Claims (3)

[Claims] 1. A microprocessor, ROM and RAM
And a second bus to which peripheral circuits other than the ROM and RAM are connected. Further, between the first bus and the second bus, the connection of both buses is possible. A bus connection circuit for controlling separation is provided, and the bus connection circuit uses the signal output from the microprocessor to indicate the access to the peripheral circuit.
A microcomputer system having a configuration in which a bus and a second bus are connected. 2. Microprocessor, ROM and RAM
Of the peripheral circuits other than the ROM and RAM, and a third bus to which the second part of the peripheral circuit group is connected. Further, a first bus connection circuit for controlling connection / separation of the both buses is provided between the first bus and the second bus, and a first bus connection circuit is provided between the first bus and the third bus. A second bus connection circuit for controlling connection / separation of both buses is provided, and the first bus connection circuit is connected to the first bus and the first bus by a signal output from the microprocessor indicating access to the first portion. The second bus connection circuit is configured to connect the two buses, and the second bus connection circuit is configured to connect the first bus and the third bus by a signal output from the microprocessor and indicating access to the second portion. A microcomputer system characterized by the above. 3. The microcomputer system according to claim 1, wherein the bus connection circuit, or the first and second bus connection circuits have a buffer function.