JPH09163178A - Horizontal synchronization circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To appropriately set a free-running frequency in a horizontal oscillation circuit part and to stabilize the synchronization state with horizontal synchronizing signals of horizontal oscillation output signals by connecting an AFC part and a free-running frequency control part connected to a PLL part to the horizontal oscillation circuit part. SOLUTION: To the AFC part 25, composite synchronizing signals CH including the horizontal synchronizing signals SH of video signals are supplied from an outside and the horizontal oscillation output signals originated from the horizontal oscillation circuit part 22 are inputted. The signals are phase- compared, control signals based on it are supplied to the horizontal oscillation circuit part 22 and the frequency of the horizontal oscillation output signals is controlled. The PLL part 23 generates synchronized output signals from the outside. The free-running frequency control part 24 supplies the control signals corresponding to the frequency of the output signals obtained from the PLL part 23 to the horizontal oscillation circuit part 22 and controls the free-running frequency so as to be matched with the frequency of the horizontal synchronizing signals from the outside. Thus, the horizontal oscillation output signals maintaining the appropriate synchronization state are obtained.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a reproduced image screen display suitable for use in an image display device for selectively displaying a reproduced image screen based on a plurality of types of video signals having different frequencies. The present invention relates to a horizontal synchronizing circuit that generates a horizontal output signal that is synchronized with a horizontal synchronizing signal in a supplied video signal.

[0002]

2. Description of the Related Art With the remarkable development of information processing equipment and information transmission / reception equipment, various kinds of synchronizing signal frequencies including a video signal obtained from a television broadcast signal, a video signal sent from a computer, etc. A multi-purpose image display device has been proposed which is compatible with video signals and can selectively display a reproduced image on the screen based on the video signals. In such a versatile image display device capable of handling a plurality of types of video signals having different sync signal frequencies,
For example, similar to the case of a normal television receiver, when performing screen display of a reproduced image based on each video signal,
It is necessary to form a horizontal output signal and a vertical output signal that are respectively synchronized with the horizontal synchronizing signal and the vertical synchronizing signal in the video signal. Therefore, the multipurpose image display device is also provided with a horizontal synchronizing circuit that generates a horizontal output signal and a vertical synchronizing circuit that generates a vertical output signal.

A horizontal synchronizing circuit used in a versatile image display device, like the horizontal synchronizing circuit used in a normal television receiver, has a horizontal frequency of a frequency that should match the frequency of the horizontal synchronizing signal in an external video signal. A horizontal oscillation circuit section for generating an oscillation output signal and an automatic frequency control section (AFC section) attached to the horizontal oscillation circuit section are provided. However, normally, the adjustment frequency bandwidth (the pull-in frequency range in the AFC unit) for the horizontal oscillation output signal generated from the horizontal oscillation circuit unit by the AFC unit is, for example,
Since it will be a relatively narrow range of a few percent of the free-running frequency of the horizontal oscillator circuit section, relying solely on the AFC section will allow a plurality of horizontal synchronizations to differ in frequency with a relatively large difference. It may be difficult to obtain a horizontal oscillation output signal that properly corresponds to each of the signals. Therefore, the horizontal synchronization circuit used in the versatile image display device is
In addition to the AFC unit, means is provided for controlling the free-running frequency of the horizontal oscillation circuit unit so as to approximately match the frequency of the horizontal synchronizing signal in the video signal from the outside.

FIG. 2 is provided with means for controlling the free-running frequency of such a horizontal oscillation circuit section so as to substantially match the frequency of the horizontal synchronizing signal in the video signal from the outside.
An example of a conventionally proposed horizontal synchronization circuit is shown. This figure 2
In the horizontal synchronizing circuit shown in FIG. 2, the horizontal oscillating circuit section 12 is supplied with the composite synchronizing signal CH including the horizontal synchronizing signal SH in the video signal from the outside supplied to the terminal 11.
The frequency of the horizontal oscillation output signal SOH generated by the AFC unit 14 is controlled by the free-running frequency control unit 13 and the AFC unit 14.

The free-running frequency control unit 13 is supplied with the composite synchronizing signal CH from the terminal 11, and the voltage signal VH corresponding to the frequency of the horizontal synchronizing signal SH included in the composite synchronizing signal CH.
Frequency-voltage conversion unit (FV conversion unit) 15 forming
And an integrator 16 that integrates the voltage signal VH from the FV converter 15 and derives an integrated output obtained as the control signal VHI. Then, the free-running frequency control unit 13 supplies the control signal VHI to the horizontal oscillation circuit unit 12 to set the free-running frequency in the horizontal oscillation circuit unit 12 to the horizontal synchronization signal SH included in the composite synchronization signal CH from the terminal 11. The frequency is controlled so that it substantially matches the frequency.

Further, the AFC section 14 is a horizontal oscillation circuit section 1
2 is supplied with the horizontal oscillation output signal SOH and the composite synchronization signal CH from the terminal 11, and the phase of the horizontal oscillation output signal SOH is compared with the phase of the horizontal synchronization signal SH included in the composite synchronization signal CH. The phase comparison unit 17 that outputs the comparison output signal VP and the comparison output signal VP from the phase comparison unit 17 are integrated, and the integrated output obtained thereby is derived as the control signal VPI, which is fed to the horizontal oscillation circuit unit 12. It is configured by the supply integration unit 18. And
The AFC unit 14 causes the horizontal oscillation output signal SOH emitted from the horizontal oscillation circuit unit 12 to have a frequency matching the frequency of the horizontal synchronization signal SH included in the composite synchronization signal CH from the terminal 11 according to the control signal VPI. Horizontal sync signal SH
Control to be synchronized with.

Under such a circumstance, the horizontal oscillation output signal SOH generated from the horizontal oscillation circuit section 12 is led to the output terminal 19 as a horizontal output signal. As a result of the control by the free-running frequency control unit 13, the frequency of the horizontal oscillation output signal SOH emitted from the horizontal oscillation circuit unit 12 and the terminal 11
If the error between the frequency of the horizontal synchronizing signal SH included in the composite synchronizing signal CH from the above is within the adjustment frequency bandwidth for the horizontal oscillation output signal SOH by the AFC unit 14, the AFC The frequency of the horizontal oscillation output signal SOH emitted from the horizontal oscillation circuit unit 12 and derived as a horizontal output signal to the output terminal 19 under the control of the section 14 is the horizontal synchronization signal SH included in the composite synchronization signal CH from the terminal 11. Will be matched to the frequency of.

[0008]

In the horizontal synchronizing circuit as shown in FIG. 2, the horizontal synchronizing signal SH supplied from the terminal 11 to the FV converter 15 in the free-running frequency controller 13 is included. In the composite synchronization signal CH, in addition to the horizontal synchronization signal SH, a period H that is 1/2 of the period H of the horizontal synchronization signal SH that is arranged in a predetermined period before and after the vertical synchronization signal and the vertical synchronization signal. An equivalent pulse signal having / 2 is often included. When the composite synchronizing signal CH includes the vertical synchronizing signal and the equivalent pulse signal, these vertical synchronizing signal and the equivalent pulse signal are supplied to the FV converter 15 like the horizontal synchronizing signal SH, and This affects the operation of forming the voltage signal VH according to the frequency of the horizontal synchronization signal SH in the FV conversion unit 15, and F-
The voltage signal VH obtained from the V conversion unit 15 will have an error from a value appropriately corresponding to the frequency of the horizontal synchronizing signal SH.

The error generated in the voltage signal VH obtained from the FV converting section 15 has a vertical cycle in the control signal VHI supplied from the integrating section 16 in the free-running frequency control section 13 to the horizontal oscillation circuit section 12. An error that occurs is generated, and an error in the control signal VHI is reflected in the control of the free-running frequency in the horizontal oscillation circuit unit 12 by the free-running frequency control unit 13 to cause an error in the setting of the free-running frequency in the horizontal oscillation circuit unit 12. Causes the inconvenience of causing.

Therefore, in the horizontal synchronizing circuit, in order to reduce the above-mentioned inconvenience, as shown in FIG. 3, the free-running frequency control unit 13 is provided to the control signal VHI obtained from the integrating unit 16.
Is provided and a vertical hold signal SV is also provided, and a sample and hold control signal obtained from the sample and hold unit 20 is provided.
It has been proposed to supply the horizontal oscillation circuit unit 12. In such a case, the sample and hold unit 20
In the above, the level of the control signal VHI obtained from the integrator 16 is sampled at a vertical cycle according to the vertical synchronizing signal SV, and the level extracted by the sampling is held, and the level obtained as a result is obtained. A sample and hold output signal is formed, which is the sample and hold control signal VH.
It is sent from the sample and hold unit 20 as S. By doing so, the sample-and-hold control signal VHS supplied to the horizontal oscillation circuit section 12 to control its free-running frequency is the control signal V obtained from the integrating section 16.
It can be said that the influence of an error generated with a vertical cycle in HI is reduced.

In order to reduce the above-mentioned inconvenience, as shown in FIG. 4, the composite sync signal CH including the horizontal sync signal SH from the terminal 11 is removed from the signal component having the period of H / 2. Through the H / 2 killer section 21, and thereby H
The corrected composite synchronization signal CHH including the horizontal synchronization signal SH is obtained from the / 2 killer unit 21 and the corrected composite synchronization signal CHH is obtained.
It has also been proposed to supply the F-V converter 15 in 3 and the phase comparator 17 in the AFC unit 14 instead of the composite synchronization signal CH. In such a case, the FV converter 15 and the AF in the free-running frequency controller 13
Although the horizontal synchronizing signal SH included in the composite synchronizing signal CH from the terminal 11 is supplied to the phase comparing unit 17 in the C unit 14, a cut in the equivalent pulse signal or the vertical synchronizing signal included in the composite synchronizing signal CH is supplied. A signal component having a period of H / 2, such as a pulse signal, is not supplied. Thereby, the FV converter 1 in the free-running frequency controller 13
5 and the control signal VHI obtained from the integrator 16 based on the voltage signal VH have a cycle such as an equivalent pulse signal included in the composite synchronizing signal CH or a cut pulse signal in the vertical synchronizing signal. Therefore, the error due to the signal component of H / 2 can be excluded.

However, as shown in FIG. 3, the free-running frequency control unit 13 including the sample and hold unit 20.
Is used, the sample-and-hold control signal VHS supplied to the horizontal oscillation circuit section 12 to control its free-running frequency is controlled by the control signal VH obtained from the integration section 16.
In I, it is assumed that the influence of an error occurring with a vertical cycle is reduced, and as shown in FIG. 4, the composite sync signal CH including the horizontal sync signal SH from the terminal 11 is an H / 2 killer. By passing through the unit 21, the control signal VHI supplied to the horizontal oscillation circuit unit 12 to control its free-running frequency is the composite synchronization signal CH.
The state in which the error caused by the signal component having the period of H / 2, such as the equivalent pulse signal included in the above or the cut pulse signal in the vertical synchronizing signal, is not included, is, for example, at the terminal 11. Composite sync signal CH supplied
However, for example, as in the case of a video signal obtained from a standard television signal, the timing of each signal such as a horizontal synchronizing signal, a vertical synchronizing signal, an equivalent pulse signal is based on a standardized format. In the case where the timing of each signal such as the horizontal synchronizing signal, the vertical synchronizing signal, the equivalent pulse signal, etc. does not follow the standardized format, it cannot be obtained.

For example, in a video signal or the like sent from a computer, there is no standardized standard for the synchronizing signal, and therefore, the respective signals such as the horizontal synchronizing signal, the vertical synchronizing signal, the equivalent pulse signal, etc. There are various types of timing that do not conform to the standardized format.

Therefore, in the horizontal synchronizing circuit shown in FIG. 3 or 4, the composite synchronizing signal CH supplied to the terminal 11 is a video signal or the like sent from the computer. , When the timing of each signal such as an equivalent pulse signal is from a video signal that does not conform to the standardized format,
The sample / hold control signal VHS or the control signal VHI supplied from the free-running frequency control unit 13 to the horizontal oscillation circuit unit 12 becomes a vertical synchronization signal other than the horizontal synchronization signal SH included in the composite synchronization signal CH, an equivalent pulse signal, or the like. The resulting error is included, and as a result, the free-running frequency control unit 1
Therefore, an error will occur in the setting of the free-running frequency in the horizontal oscillation circuit section 12 according to 3.

Further, in the horizontal synchronizing circuit shown in FIG. 3 or 4, random pulse noise in a state where the composite synchronizing signal CH supplied to the terminal 11 is mixed with the horizontal synchronizing signal SH included therein. When the component is also included, it is included in the sample hold control signal VHS or the control signal VHI supplied from the free-running frequency control unit 13 to the horizontal oscillation circuit unit 12 due to the random pulse noise component. The error will not be reduced either.

In view of the above point, according to the present invention, the horizontal oscillation output signal generated from the horizontal oscillation circuit section is supplied with the horizontal synchronization signal in the video signal from the outside, and the free-running frequency control section and the AFC are used. The horizontal synchronization signal in the video signal from the outside when the frequency is controlled to be synchronized with the horizontal synchronization signal in the video signal from the outside by the However, even if a vertical synchronizing signal, an equivalent pulse signal, or even a random pulse noise component is supplied in a mixed state, the video signal from the outside is synchronized with the horizontal synchronizing signal or the vertical synchronizing signal. Water signals by the free-running frequency control unit regardless of whether the timing of each signal such as a signal or an equivalent pulse signal conforms to the standardized format. The horizontal synchronization circuit is set so that the free-running frequency is properly set in the oscillator circuit section, and as a result, a horizontal oscillation output signal is obtained in which an appropriate synchronization state with the horizontal synchronization signal from the outside is stably maintained. provide.

[0017]

A horizontal synchronizing circuit according to the present invention includes a horizontal oscillation circuit section for generating a horizontal oscillation output signal having a predetermined frequency, a horizontal oscillation output signal generated from the horizontal oscillation circuit section, and a horizontal signal from the outside. The phase comparison with the synchronization signal is performed to obtain the comparison output signal, and the control signal based on the comparison output signal is supplied to the horizontal oscillation circuit section to control the frequency of the horizontal oscillation output signal. Phase-locked loop section (P
LL section) and a control signal corresponding to the frequency of the output signal obtained from the PLL section, and supplies the control signal to the horizontal oscillation circuit section to set the free-running frequency of the horizontal oscillation circuit section to that of a horizontal synchronization signal from the outside. And a free-running frequency control unit that controls to match the frequency.

In the horizontal synchronizing circuit according to the present invention having the above-described structure, the horizontal synchronizing signal from the outside is supplied to the PLL section, which synchronizes with the horizontal synchronizing signal from the outside obtained from the PLL section. The generated output signal is supplied to the free-running frequency control unit, and the free-running frequency control unit supplies the horizontal oscillation circuit unit with a control signal corresponding to the frequency of the output signal obtained from the PLL unit. Control is performed so that the free-running frequency matches the frequency of the horizontal synchronizing signal from the outside. In such a case, the PLL section has a strict frequency selection characteristic, and substantially selects only the frequency of the horizontal synchronizing signal from the outside and generates an output signal in synchronization with the frequency. Even when the horizontal synchronization signal of the above is in a state in which the vertical synchronization signal, the equivalent pulse signal, and the random pulse noise component and the like are mixed, the PLL unit supplies the free-running frequency control unit. The output signal is a signal accurately synchronized with the horizontal synchronizing signal from the outside, whereby the control signal supplied from the free-running frequency control unit to the horizontal oscillation circuit unit to control the free-running frequency is It is assumed that the vertical synchronization signal, the equivalent pulse signal, and the error due to the random pulse noise component and the like are not included.

Therefore, even when the horizontal synchronizing signal from the outside is supplied with the vertical synchronizing signal, the equivalent pulse signal, and the random pulse noise component mixed therein, the horizontal synchronizing signal from the outside is also supplied. The video signals separated from the sync signals are horizontal sync signals, vertical sync signals,
Regardless of whether the timing of each signal such as the equivalent pulse signal is based on the standardized format,
Horizontal oscillation in which the free-running frequency is properly set in the horizontal oscillation circuit by the free-running frequency controller, so that an appropriate synchronization state with the horizontal synchronization signal from the outside is stably maintained from the horizontal oscillation circuit. An output signal is obtained.

[0020]

1 shows an example of a horizontal synchronizing circuit according to the present invention. In this example, at the terminal 21, for example, a horizontal synchronizing signal SH in a video signal from the outside such as a video signal obtained from a television broadcast signal, a video signal sent from a computer, and a vertical sync signal Composite sync signal CH including sync signal, equivalent pulse signal, etc.
Is supplied. Then, when the composite synchronizing signal CH including the horizontal synchronizing signal SH is supplied to the terminal 21 in this way, the frequency and phase of the horizontal oscillation output signal SOH generated from the horizontal oscillation circuit unit 22 are the PLL unit 23, The horizontal oscillation output signal SOH is controlled by the free-running frequency control unit 24 and the AFC unit 25, and as a result, the horizontal oscillation output signal SOH is included in the composite synchronization signal CH from the terminal 21, that is, the horizontal synchronization signal SH from the outside. It is assumed that the phase state with respect to the horizontal synchronizing signal SH is appropriately maintained with high accuracy and the synchronizing state with the horizontal synchronizing signal SH is stabilized, and the phase state with respect to the horizontal synchronizing signal SH is stabilized. It is led to the output terminal 26.

The PLL section 23 is provided with a voltage controlled oscillator 30, and further, an oscillation output signal SQH issued from the voltage controlled oscillator 30 and a horizontal synchronizing signal S from the terminal 21.
H, and further, a composite synchronizing signal CH including a vertical synchronizing signal, an equivalent pulse signal, etc. is supplied to generate an oscillation output signal SQ.
Horizontal sync signal S included in the phase of H and composite sync signal CH
Comparison from the phase comparison unit 31 and the phase comparison unit 31 which compares the phase of H and sends out the comparison output signal VQ corresponding to the phase difference between the oscillation output signal SQH and the horizontal synchronization signal SH obtained thereby. The output signal VQ is integrated, the integrated output obtained thereby is derived as the control signal VQI, and the composite section synchronizing signal CH from the integrating section 32 and the terminal 21 for supplying it to the voltage controlled oscillator 30 is supplied to it. The FV conversion unit 33 that forms the voltage signal VX according to the frequency of the included horizontal synchronization signal SH, and the voltage signal VX from the FV conversion unit 33 are integrated, and the integrated output obtained thereby is a control signal. It is derived as VXI, and the voltage controlled oscillator 30
It is configured to include an integrator 34 for supplying to.

The FV converter 33 and the integrator 34 form a frequency controller for controlling the free-running frequency in the voltage controlled oscillator 30. This frequency controller is the integrator 34.
By the control signal VXI obtained from the above, the free-running frequency in the voltage controlled oscillator 30 is substantially equal to the horizontal synchronizing signal SH included in the composite synchronizing signal CH from the terminal 21, that is, the frequency of the horizontal synchronizing signal SH from the outside. Control to let. Thereby, the free-running frequency in the voltage controlled oscillator 30 is set.

The phase comparison section 31 and the integration section 32, together with the voltage controlled oscillation section 30, form the basic constituent parts of the PLL. Then, the phase comparison unit 31 and the integration unit 32 form a negative feedback loop for the voltage control oscillation unit 30, and the oscillation output signal SQH issued from the voltage control oscillation unit 30 is generated by the control signal VQI obtained from the integration unit 32. Is controlled so that its frequency coincides with the frequency of the horizontal synchronizing signal SH from the outside and is placed in a synchronized state with the horizontal synchronizing signal SH. Under such circumstances, the voltage controlled oscillator 3
0, P formed by the phase comparison unit 31 and the integration unit 32
The basic constituent part of the LL has a strict frequency selection characteristic, and substantially selects only the frequency of the horizontal synchronizing signal SH to generate an oscillation output signal SQH from the voltage controlled oscillator 30 in synchronization with it. Therefore, even if the horizontal synchronizing signal SH from the outside is in a state in which the vertical synchronizing signal, the equivalent pulse signal, and the random pulse noise component and the like are mixed, the voltage-controlled oscillation is generated. Part 3
The oscillation output signal SQH generated from 0 is a signal that is properly synchronized with the horizontal synchronization signal SH and maintains the same frequency as the frequency of the horizontal synchronization signal SH.

The free-running frequency control section 24 is supplied with the oscillation output signal SQH emitted from the voltage controlled oscillation section 30 in the PLL section 23, and forms an F-V which forms a voltage signal VH corresponding to the frequency of the oscillation output signal SQH. Conversion unit 35, and
It is configured to include an integrating unit 36 that integrates the voltage signal VH from the FV converting unit 35 and derives an integrated output obtained as the control signal VHI. Then, the free-running frequency control unit 24 sends the control signal VHI to the horizontal oscillation circuit unit 22.
To the free-running frequency in the horizontal oscillation circuit section 22,
The control is performed so that the frequency of the oscillation output signal SQH emitted from the voltage controlled oscillator 30 in the PLL unit 23, that is, the frequency of the horizontal synchronizing signal SH from the outside, is substantially matched. Thereby, the free-running frequency in the horizontal oscillation circuit section 22 is set.

In the operation of the free-running frequency control section 24, the horizontal synchronizing signal SH from the outside is in a state in which the vertical synchronizing signal, the equivalent pulse signal, the random pulse noise component and the like are mixed. Even at the beginning,
Since the oscillation output signal SQH emitted from the voltage controlled oscillator 30 in the PLL unit 23 is properly synchronized with the horizontal synchronization signal SH, the oscillation output signal SQH is properly maintained at the same frequency as the frequency of the horizontal synchronization signal SH. Running frequency control unit 24
The control signal VHI supplied from the integrator 36 to the horizontal oscillation circuit 22 in FIG. 2 is caused by the vertical synchronizing signal, the equivalent pulse signal, and the random pulse noise component that are mixed with the horizontal synchronizing signal SH. It is assumed that no error is included. As a result, the setting of the free-running frequency in the horizontal oscillation circuit unit 22 by the free-running frequency control unit 24 is
It is properly performed while setting errors are sufficiently suppressed.

Further, the AFC section 25 is the horizontal oscillation circuit section 2
2 and the horizontal oscillation output signal SOH from the terminal 21
Is supplied, and the phase of the horizontal oscillation output signal SOH is compared with the phase of the horizontal synchronization signal SH included in the composite synchronization signal CH, and the phase is obtained. Comparison output signal V corresponding to the phase difference between the horizontal oscillation output signal SOH and the horizontal synchronization signal SH
The phase comparison unit 27 that outputs P and the comparison output signal VP from the phase comparison unit 27 are integrated, the integrated output obtained thereby is derived as the control signal VPI, and the integrated output is supplied to the horizontal oscillation circuit unit 22. And a part 28.

The AFC section 25 is composed of the horizontal oscillation circuit section 2
2 forms a negative feedback loop for 2, which is optimized from the viewpoint of noise reduction, for example,
It has an integration time constant of several milliseconds (several ms) and is set as a relatively low gain (loop gain). And
The AFC unit 25 uses the control signal VP obtained from the integrating unit 28.
Due to I, the frequency of the horizontal oscillation output signal SOH generated from the horizontal oscillation circuit section 22 becomes the same as the frequency of the horizontal synchronization signal SH from the outside, and the horizontal oscillation output signal SOH is brought into a synchronized state with the horizontal synchronization signal SH. To control. As a result, the horizontal oscillation output signal SOH, which is the horizontal output signal derived to the output terminal 26, is changed from the external horizontal synchronization signal SH.
It is assumed that the phase state with respect to the horizontal synchronizing signal SH is properly maintained with high accuracy and the synchronizing state with the horizontal synchronizing signal SH is stabilized.

In this way, in the example shown in FIG. 1, the horizontal synchronizing signal SH included in the composite synchronizing signal CH from the terminal 21, that is, the horizontal synchronizing signal SH from the outside is
On the other hand, even when the vertical synchronizing signal, the equivalent pulse signal, and the random pulse noise component are supplied in a mixed state, the video signal from which the horizontal synchronizing signal SH from the outside is separated is the horizontal synchronizing signal. Regardless of whether or not the timing of each signal such as a signal, a vertical synchronizing signal, an equivalent pulse signal, etc. conforms to a standardized format, the free-running frequency control unit 24 controls the free-running frequency of the horizontal oscillation circuit unit 22. The setting is properly performed, and as a result, the horizontal oscillation output signal SOH is obtained from the horizontal oscillation circuit section 22 in which the proper synchronization state with the horizontal synchronization signal SH from the outside is stably maintained.

The horizontal synchronizing circuit according to the present invention is shown in FIG.
However, the horizontal oscillation circuit unit 22, the PLL unit 23, the free-running frequency control unit 24, and the AFC are not limited to the example shown in FIG.
It is conceivable that various modifications are made within the range in which the basic configuration including the portion 25 is maintained.

[0030]

As is apparent from the above description, in the horizontal synchronizing circuit according to the present invention, the horizontal synchronizing signal from the outside is provided under the condition that the free-running frequency control unit and the AFC unit for the horizontal oscillation circuit unit are provided. Is supplied to the PLL unit, whereby an output signal obtained from the PLL unit and synchronized with an external horizontal synchronizing signal is supplied to the free-running frequency control unit, and the output obtained from the PLL unit by the free-running frequency control unit. The control signal according to the frequency of the signal is supplied to the horizontal oscillation circuit section,
Control is performed so that the free-running frequency of the horizontal oscillation circuit unit matches the frequency of the horizontal synchronizing signal from the outside.

In this case, the PLL section has a strict frequency selection characteristic, and substantially selects only the frequency of the horizontal synchronizing signal from the outside, and generates the output signal synchronized with it. Even when the horizontal synchronizing signal from the outside is in a state in which the vertical synchronizing signal, the equivalent pulse signal, and the random pulse noise component are mixed, the free-running frequency control is performed from the PLL unit. The output signal supplied to the section is a signal accurately synchronized with the horizontal synchronizing signal from the outside, and as a result, the control supplied from the free-running frequency control section to the horizontal oscillation circuit section to control the free-running frequency. It is assumed that the signal does not include an error caused by a vertical synchronizing signal, an equivalent pulse signal, a random pulse noise component, or the like.

Therefore, according to the horizontal synchronizing circuit of the present invention, the horizontal synchronizing signal from the outside has a state in which the vertical synchronizing signal, the equivalent pulse signal, and the random pulse noise component are mixed. Whether or not the video signal from which the horizontal synchronizing signal has been separated conforms to the standardized format of the timing of each signal such as the horizontal synchronizing signal, the vertical synchronizing signal, and the equivalent pulse signal even when supplied. Regardless, the free-running frequency control section sets the free-running frequency in the horizontal oscillation circuit section appropriately, and as a result, the proper synchronization state with the horizontal synchronization signal from the outside from the horizontal oscillation circuit section is stably maintained. A horizontal oscillation output signal is obtained. Therefore, the horizontal synchronizing circuit according to the present invention can appropriately deal with each of the horizontal synchronizing signals in a plurality of external video signals dispersed in a wide frequency band.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an example of a horizontal synchronizing circuit according to the present invention.

FIG. 2 is a block diagram showing an example of a conventional horizontal synchronizing circuit.

FIG. 3 is a block diagram showing an example of a conventional horizontal synchronizing circuit.

FIG. 4 is a block diagram showing an example of a conventional horizontal synchronizing circuit.

[Explanation of symbols]

 21 terminal 22 horizontal oscillation circuit section 23 PLL section 24 free-running frequency control section 25 AFC section 26 output terminal 27, 31 phase comparison section 28, 32, 34, 36 integration section 30 voltage control oscillation section 33, 35 FV conversion section

Claims (6)

[Claims] 1. A horizontal oscillation circuit section for generating a horizontal oscillation output signal of a predetermined frequency, and a comparison output signal by performing phase comparison between a horizontal oscillation output signal generated from the horizontal oscillation circuit section and a horizontal synchronization signal from the outside. An automatic frequency control unit for controlling the frequency of the horizontal oscillation output signal by supplying a control signal based on the comparison output signal to the horizontal oscillation circuit unit, and an output signal synchronized with a horizontal synchronization signal from the outside. A phase-locked loop unit that is generated and a control signal according to the frequency of an output signal obtained from the phase-locked loop unit are formed, and the control signal is supplied to the horizontal oscillation circuit unit to generate the horizontal oscillation. And a free-running frequency control unit that controls the free-running frequency of the circuit unit to match the frequency of the horizontal synchronizing signal from the outside. 2. A phase comparison section in which an automatic frequency control section compares the phase of a horizontal oscillation output signal emitted from a horizontal oscillation circuit section with a horizontal synchronization signal from the outside, and a comparison output signal obtained from the phase comparison section. 2. The horizontal synchronizing circuit according to claim 1, wherein the horizontal synchronizing circuit is configured to include an integrating section that integrates to form a control signal. 3. A frequency-voltage conversion unit, in which a free-running frequency control unit obtains a voltage signal corresponding to the frequency of an output signal obtained from the phase-locked loop unit, and a voltage signal obtained from the frequency-voltage conversion unit. And an integrator that integrates to form a control signal.
Alternatively, the horizontal synchronization circuit described in 2. 4. A phase-locked loop unit, a phase-controlled oscillation unit, a phase comparison unit for performing phase comparison between an oscillation output signal emitted from the voltage-controlled oscillation unit and an external horizontal synchronizing signal, and the phase. An oscillation output signal emitted from the voltage controlled oscillator, which is configured to include an integrator that forms a control signal by integrating the comparison output signal obtained from the comparator and supplies the control signal to the voltage controlled oscillator. 4. The horizontal synchronizing circuit according to claim 1, wherein the output signal is an output signal synchronized with the external horizontal synchronizing signal. 5. The phase-locked loop unit forms a control signal in accordance with the frequency of a horizontal synchronizing signal from the outside in addition to the voltage controlled oscillator, the phase comparator and the integrator, and outputs the control signal as described above. The horizontal control unit according to claim 4, further comprising a frequency control unit that supplies the voltage-controlled oscillation unit to control the free-running frequency of the voltage-controlled oscillation unit to match the frequency of the horizontal synchronizing signal from the outside. Synchronous circuit. 6. A frequency control section provided in the phase locked loop section is obtained from a frequency-voltage conversion section for obtaining a voltage signal according to the frequency of a horizontal synchronizing signal from the outside, and the frequency-voltage conversion section. 6. An integrating unit for integrating a voltage signal to form a control signal according to the frequency of a horizontal synchronizing signal from the outside.
Horizontal synchronization circuit described.