JPH09162752A - Digital data output device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To allow the output device to need digital data error information and its discrimination circuit by sending error information of transmission digital data in addition to transmission digital data and allowing a receiver side to make error check in addition to detection of a transmission error. SOLUTION: When a data period elapses, at the same time a switch 2 is open, a switch 3 is closed and an error flag obtained by an error correction circuit is fed to an adder 5 via the switch 3. On the other hand, a cyclic redundancy check code CRCC is given serially to the adder 5 via an adder 4 from a generation polynomial register 1. When there is no error in data received by the generation polynomial register 1, since an error flag whose content is '0' is given to one input terminal of the adder 5, the CRCC is outputted to a post stage without any modification and when any error is in existence, the error flag whose content is '1' is given to the adder 5, the data whose logic is inverted are outputted serially.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital data output device, and more particularly to a digital data output device provided with an error detection code or an error correction code.

[0002]

2. Description of the Related Art Conventionally, as an apparatus for reproducing digital data, a digital audio tape recorder (DAT) for reproducing digital data relating to an audio signal recorded on a magnetic tape by a rotary head, a video signal and an audio signal. Digital VTRs and the like are known in which signals are converted to digital data and reproduced from a magnetic tape. The digital data reproduced by these is D /
It is converted into an analog signal by the A converter and output.
Similarly, in a digital broadcast receiver, digital data decoded after reception is converted into an analog signal.

However, in recent years, a digital interface for transmitting digital data such as the digital data reproducing device and the digital broadcasting receiver to another electronic device (for example, a computer) as a digital signal has been developed. IEEE 1394 is known as one of them. In this IEEE 1394, a cyclic redundancy check code (CRCC) is used as an error detection code in the transmitted digital data in order to detect a data error in the transmission path of the transmitted digital data.
Is added for transmission.

FIG. 3 is a block diagram showing an example of a conventional digital data output device for generating the CRCC. As shown in the figure, this conventional device has a generator polynomial register 2
1, an adder 22 inserted in the feedback loop of the generator polynomial register 21, and a switch 23 for controlling data input to the adder 22.

In this conventional apparatus, the digital data input through the switch 23 is added to the data output from the generator polynomial register 21 in the adder 22,
The addition result is output and the generator polynomial register 21
Feedback to

When there is no more data, the switch 23 is turned off, and the remainder obtained by dividing the a-bit information data from the generator polynomial register 21 by the predetermined b-bit generator polynomial determined by the configuration of the generator polynomial register 21 is obtained. Is output. Since such a conventional device is provided on the receiving side and the digital data is composed of a remainder obtained by dividing the information data by the generator polynomial and the information data at that time, this digital data is divided by the generator polynomial. Then, if the residue obtained by this is zero, it is detected that there is no error, and if the residue is not zero, it is detected that there is an error, and the error correction circuit corrects.

[0007]

However, when digital data that happens to have an error that cannot be corrected by the error correction circuit is transmitted through the IEEE 1394 digital interface, an error occurs in the received digital data at the receiving side. It will be recognized as incorrect data, which causes inconvenience. Therefore, conventionally, in order to avoid such inconvenience, correctness information (correction determination bit) of the transmitted digital data is also sent separately from the transmitted digital data, and the reception side determines the correctness of the data separately from the transmission path error detection. Therefore, correct / wrong information of digital data and a judgment circuit for the same are required.

The present invention has been made in view of the above points,
An object of the present invention is to provide a digital data output device capable of eliminating the correctness determination bit of data and the determination circuit by making the transmission line error detection circuit also perform the determination of correctness of digital data.

[0009]

In order to achieve the above-mentioned object, the present invention provides a digital output of digital data in which redundant bits consisting of at least one of an error correction code and an error detection code are added to transmitted information data. In the data output device, when it is detected that the input information data is uncorrectable, a detecting means for outputting an error flag having a predetermined logical value, and an error flag having a predetermined logical value are input. , One of the information data and the redundant bit is changed to a logical value indicating an error and is output.

Here, the logic value changing means in the present invention, when an error flag having a predetermined logic value is input,
A means for inverting the logical value of at least 1 bit of the error detection code and outputting it by inverting it may be used. The logical value changing means includes a generating circuit that generates a CRCC based on the information data and an adding means that adds an error flag to the output CRCC and outputs it as a redundant bit during a period in which the CRCC is output from the generating circuit. It may be configured as follows.

According to the present invention, when uncorrectable data is input, one of the information data and the redundant bit is changed to a logical value indicating an error and then output. It can be detected by the error detection circuit.

[0012]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, embodiments of the present invention will be described with reference to the drawings. FIG. 1 shows a block diagram of an embodiment of the present invention, and FIG. 2 shows a block diagram of an example of a reproducing apparatus to which the present invention is applied. First, the reproducing apparatus will be described with reference to FIG. This reproducing apparatus reproduces, for example, at least one of an error detection code and an error correction code (here, CR which is an error detection code) reproduced from a magnetic tape by a rotary head.
CC) is added to the information data as redundant bits, and the digital data is modulated by a predetermined modulation method, and a high frequency band signal is demodulated by the demodulation circuit 11 to be converted into base band signal band digital data. , The digital data shuffled in the recording system by the deshuffling circuit 12 is deshuffled by the reverse operation and is returned to the original order and input to the error correction circuit 13.

The error correction circuit 13 detects an error by dividing the input reproduced digital signal by the added CRCC generating polynomial, and corrects the error using the added error correction code. However, in the present invention, the correctness / incorrectness determination bit is not added to the reproduced digital signal, and the transmission error is also determined from the error detection using CRCC. The output digital data of the error correction circuit 13 is, for example, IEEE.
It is output via the output circuit 14 having a 1394 interface.

Next, an embodiment of the present invention will be described with reference to the block diagram of FIG. The digital data output device shown in FIG. 1 is provided in the output circuit 14 of FIG. 2 and includes a generator polynomial register 1, a first switch 2 and a second switch.
Switch 3, a first adder 4, and a second adder 5. The generator polynomial register 1 and the first adder 4 obtain the remainder by dividing the input digital data by the generator polynomial, as in the conventional digital data output device.

The switches 2 and 3 are switches that interlock with each other, and when one is on (closed), the other is off (open). The adder 5 adds the output of the adder 4 and the error flag input via the switch 3.

Next, the operation of this embodiment will be described. The data period switch 2 is turned on and the switch 3 is turned off, and the data from the error correction circuit 13 is supplied to the adder 4 via the switch 2 and is added to the output of the generator polynomial register 1 here. After that, the CRCC, which is the remainder divided by the predetermined generator polynomial, is input to the generator polynomial register 1 to be calculated.

When the data period elapses, the switch 2 is turned off and the switch 3 is turned on at the same time, and the error flag obtained by the error correction circuit 13 is input to the adder 5 via the switch 3. The CRCC is serially input from the generator polynomial register 1 to the adder 5 via the adder 4. Here, the adder 5 is a 2-input exclusive OR circuit (EX-OR circuit).

When the data input to the generator polynomial register 1 has no error, the value indicating that there is no error is "
An error flag of "0" is input to one input terminal of the adder 5 and CRCC calculated based on the data.
Is serially input to the other input terminal of the adder 5, the CRCC is output to the subsequent stage as it is.

On the other hand, when the data input to the generator polynomial register 1 has an error, the adder 5 to which the CRCC calculated based on the data is input has a value indicating that there is an error. The error flag of "1" is input. Therefore, the CRCC serially input to the adder 5
Is logically inverted by an exclusive OR operation with the error flag, and is serially output.

The output CRCC of the adder 5 is added to the data and transmitted to another device. In other devices, this data is divided using a CRCC generator polynomial and error detection is performed based on the presence / absence of a remainder, so that it can be determined whether or not the data is in error. In other words, when all bits of CRCC are logically inverted, it is determined that there is an error because the CRCC has a value different from the original CRCC, and thus the conventionally required correctness / incorrectness determination bit can be eliminated, and thus the correct / incorrectness determination bit determination circuit can be performed. Can be unnecessary.

The present invention is not limited to the above-described embodiment, and when the data input to the generator polynomial register 1 has an error, for example, at least one bit in the generator polynomial register 1 is inverted. Alternatively, the method of setting or clearing the generator polynomial register 1 to a certain value may be used.

Further, the present invention is not limited to the error detection code using the CRCC, and even in the case of the digital data output signal using the error correction code, the contents of the check word can be changed in the same manner to correct the error. You may add the error exceeding. Further, the method of changing the error check word from the positive one has been described, but the same effect can be obtained even if the data is changed from that input to the error check circuit.

Further, the present invention can be applied not only to the reproducing apparatus but also to the digital broadcasting receiver.

[0024]

As described above, according to the present invention,
When uncorrectable data is input, one of the information data and the redundant bit is changed to a logical value that indicates an error and then output, so that the correctness of the output digital data is detected by the error detection circuit in the transmission line. As a result, the correctness / incorrectness judgment bit of data and the correctness / wrongness judgment circuit, which have been conventionally required in the digital interface, can be eliminated, the transmission / reception circuit can be simplified, and the transmission line capacity can be saved.

[Brief description of the drawings]

FIG. 1 is a block diagram of an embodiment of the present invention.

FIG. 2 is a block diagram of an example of a playback device to which the present invention is applied.

FIG. 3 is a block diagram of an example of the related art.

[Explanation of symbols]

 1 Generator Polynomial Register 2, 3 Switch 4, 5 Adder

Claims (3)

[Claims] 1. A digital data output device for outputting digital data in which redundant bits consisting of at least one of an error correction code and an error detection code are added to transmitted information data, and the inputted information data is uncorrectable. When it is detected that the error flag of a predetermined logical value is output, and when the error flag of the predetermined logical value is input,
A digital data output device, comprising: a logical value changing means for changing one of the information data and the redundant bit to a logical value indicating an error and outputting the logical value. 2. The logic value changing means is means for inverting the logic value of at least 1 bit of the error detection code when the error flag having the predetermined logic value is inputted and outputting the inverted logic value of the error detection code. The digital data output device according to claim 1, wherein: 3. The redundancy changing means adds the error flag to the output CRCC during a period in which the CRCC is output from the generation circuit, which generates a CRCC based on the information data. 2. The digital data output device according to claim 1, further comprising an addition means for outputting as a bit.