JPH09162360A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device which exhibits such an I-V characteristic as to show a negative differential resistance characteristic of an RTD and which has such a characteristic that the valley current may be flat over a wide drain voltage range, when the gate voltage becomes a specified level or above. SOLUTION: This device is constituted of a multilayer film wherein a field- effect transistor (HEMT) layer which has an InAlAs/InGaAs selective dope hetero structure that is lattice-matched with InP and an InGaAs resonance tunnel diode layer are deposited in order. The HEMT layer and the resonance tunnel diode layer are electrically connected in series with each other. Between the HEMT layer and the resonance tunnel diode layer, a non-alloy ohmic contact layer consisting of an n<+> -InAlAs layer and an n<+> -InGaAs layer is inserted from the substrate side and then a selective etching stopper layer constituting of an n<+> -InAlAs layer is inserted on the non-alloy ohmic contact layer.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a high-speed and multifunctional semiconductor device, and more particularly to a semiconductor device which is a monolithic integration of a resonant tunneling diode and a HEMT using quantum effect.

[0002]

2. Description of the Related Art In recent years, active research has been conducted on semiconductor electronic devices that apply quantum effects. Among them, the resonant tunneling device composed of a double barrier structure is capable of increasing the number of gates and the number of gate stages of an integrated circuit by utilizing the functionality derived from the negative differential resistance characteristic, and thus has attracted particular attention as a semiconductor functional device. There is. Furthermore, by utilizing the speeding up of the resonant tunneling phenomenon, it is attracting attention as an ultra-high speed analog device such as an oscillator.

The number of dimensions of quantization required for the resonant tunneling device is only one dimension in the vertical direction. Therefore, the molecular beam epitaxial growth technique (MBE) or the metal organic vapor deposition technique capable of controlling the thickness of each atomic layer is used. Phase growth method (MOCV
Since the resonant tunneling structure, which is a quantum structure, can be formed only by using the epitaxial growth technique such as D), it is possible to sufficiently reduce the size of the quantum well. Therefore, the resonance tunnel device can operate at room temperature, and attention is paid also from this point. On the other hand, when considering the use as a device, considering the separation of input and output, the gain, etc., the transistor is much easier to use than the diode. Therefore, various attempts have been made to make the resonant tunnel device three-terminal. ing.

As such a three-terminal resonance tunnel device, a resonance tunnel hot electron transistor (RHET) in which a resonance tunnel diode is inserted between an emitter and a base of a hot electron transistor which is a unipolar type device, or a base of a bipolar transistor is used. Resonant tunnel bipolar transistor (RTBT) in which a resonant tunnel diode is inserted in a part of the resonance tunnel diode, the quantum well of the resonant tunnel diode is doped with a p-type dopant, and the base of the npn-type bipolar transistor is a resonance consisting of this p-type quantum well. A bipolar quantum resonance tunnel transistor (BiQuaRTT) replaced by a tunnel diode can be used.

The device described above seeks to add functionality by incorporating a resonant tunneling diode in the two electrodes of a conventional three terminal device. On the other hand, as a method of constructing a three-terminal resonance tunnel device having a simpler structure, a resonance tunnel diode and a field effect transistor (FET) are connected in series, that is, a resonance tunnel diode is connected to a source electrode of the FET,
Alternatively, there is an attempt to realize a resonance tunnel three-terminal device as a whole by connecting to either one of the drain electrodes.

[0006] The first of these attempts is document 1
(AR Bonnefoi, TC McGill and RD Burnh
am by IEEE Electron Device Letters, Vol. E
DL-6, NO. 12, (1985) pp. 636-638),
It is a transistor (resonance tunnel MESFET) configured to connect an RTD and a Schottky barrier field effect transistor (MESFET) in series. The feature of this device is that F
It seeks to modulate the resistance of the ET channel and through it the peak and valley voltages.

As a conventional example which realizes the most excellent device characteristics in such a transistor having the RTD and FET connected in series, reference 2 [W. De Raedt, M. Van Ho
Ins by ve, C. Van Hoof and M. Van Rossum
titute of Physics Confere-nce Series Number 112, p
p. 477 −481 (Paper presented at Int. Symp. GaAs a
nd Related Compounds, 1990, IOP Publishing Ltd, Br
istol. England)], AlAs-GaAs
-AlAs double barrier RTD and pseudomorphic Al _0.22
Ga _0.78 As-In _0.2 Ga _0.8 As high mobility transistors (HEMTs) connected in series can be raised. The IV characteristics as a function of gate voltage for the device reported in this document are shown in FIG. 1 (a) and FIG.
(B). 1 (a) shows the characteristics of the RTD connected to the source of the HEMT, and FIG. 1 (b) shows the RTD of the HEMT.
This is the characteristic of the one connected to the drain of. As shown in the figure, it can be seen that the gate voltage modulates the peak voltage and the valley voltage to obtain the characteristics as a three-terminal resonance device. Further, the ratio of the peak current and the valley current reported in Document 2 is 2.8: 1. In the above description of the prior art, the semiconductor device in which the RTD and the FET are connected in series has been described. However, as a configuration different from this, conventionally, an N-type negative resistance element capable of controlling the peak current value is connected in series. There is known a logic gate that is connected and takes out the voltage at the connection point as an output (Reference 7, K. Maezawa, T. Akeyoshi and T. Mizutani, IEE).
E Transactions on Electron Devices, Vol.41, No.2 (19
92) pp.148-154). This type of logic gate causes a monostable to a bistable transition when the driving power supply circuit is of a vibration type. In particular, at the time of this transition, since the output voltage "0" or "1" is determined by the slight difference in the peak current value of the negative resistance elements connected in series, multiple inputs and multiple outputs are possible. Various applications have been shown as functional logic gates. Reference 8 (Kevin, J. Chen, T. Akeyoshi, K. Maezawa, Jp) describes a method of realizing an N-type negative resistance element capable of controlling the peak current value which is a constituent element of this logic gate.
nJAppl.Phys., Vol.34 (1995) pp.1199-1203) has a resonant tunnel diode (RTD) and a FET connected in parallel, and controls the current flowing through the FET by the gate voltage to the FET, which is effective. A method of modulating the peak current of a negative differential characteristic type IV characteristic of a parallel circuit has been reported.

As another conventional technique related to the epitaxial layer structure of the semiconductor device of the present invention, there is a document 3 (Y. Watanab
e, Y. Nakasha, K. Imamnishi and M. Takikawa, 1992 IEEE Electron Device Meeting, Technic
al Digest, pp. 475-478), as shown in FIG.
Selectively-doped InAlAs / InGaAsHEMT using a material system lattice-matched to InP, a so-called InGaAsHEMT structure on a P substrate, and InGaAs also matched to InP, which is further stacked thereon, are used as quantum wells and InAlAs is used as a barrier. A laminated structure of an InGaAs resonance tunnel structure composed of a double barrier structure has been reported.

Further, as related to the frequency multiplier using the semiconductor device of the present invention, two resonance tunnel diodes are provided in a part of the base of the bipolar transistor.
A frequency multiplier using a resonant tunneling bipolar transistor (RTBT) with a series connection is disclosed in Reference 4 (S. Sen, F. Capasso, AY Cho, and DLSi).
By vco, IEEE Electron Device Letters, Vol. VO
L. 9, NO. 10, (1988) pp.533-535). FIG. 3 shows a circuit configuration. In FIG. 3, Tr1 is the above RTBT, VBB is a DC bias power source, RB is an input base resistance, Rc is a collector resistance, and Vcc is a collector voltage.

Further, selectively doped InAlAs / InG
As a conventional example of aAsHEMT single non-alloy ohmic contact layer, the upper layer n ⁺ -InGaAs, n ⁺ -InG of 2-layer structure using an n ⁺ type InAlAs layer in the lower layer
The aAs / n ⁺ -InAlAs cap layer is described in Reference 5 (T.
1994 by Enoki, T. kobayashi and Y. Ishii.
IEEE GaAs IC Symposium, Technical Digest, pp.337
-340). In addition, a citric acid-based etching solution that selectively etches only the InGaAs layer using the InAlAs layer as an etching stopper is disclosed in Reference 6 (GC DeSalvo, WF Tseng and
J. Electrochem. Soc., Vol. 139 (1
992) p. 831). The above is the prior art related to the present invention.

[0011]

As shown in the characteristics of FIG. 1, AlAs-GaAs-AlAsRTD and pseudo
Omorphic Al _0.22 Ga _0.78 As-In _0.2 Ga _0.8
In the conventional example of the resonance tunnel transistor in which AsHEMTs are connected in series, the three-terminal characteristic is obtained in that the peak voltage and the valley voltage are modulated by the gate voltage, but it is still not attempted to apply this to a circuit. There are problems that need to be improved. That is, when connecting a load resistor to form a circuit,
In both the characteristics of (a) and FIG. 1 (b), in the valley current region, with respect to the drain-source voltage Vd,
This is to include a region where the drain current Id does not exhibit a flat characteristic and greatly changes with a change in Vd. For this reason,
There are serious drawbacks such that the range of the power supply voltage required to obtain a normal operation of the circuit becomes strict, and the allowable manufacturing range of the load resistor is narrowed. Considering that a load resistor is connected to this resonant tunneling transistor to form a circuit, the drain current Id is partially different from the drain voltage Vd in the valley current region shown in FIG. The configuration in which the RTD is connected to the source of the HEMT, which has flat characteristics, has a larger operation margin.
However, even in this connection, as described above, in consideration of the reason that the valley current region exhibits a characteristic including a region that largely changes with the change of Vd with respect to the drain-source voltage Vd, the transistor is inserted in series with the transistor. This is because the generated parasitic resistance is large. Especially, this parasitic resistance is
This is because the parasitic resistance between the RTD and the RTD, that is, the source resistance of the HEMT is large.

The structure of the epitaxially grown film described in Document 3 is shown in FIG. This is a selective doping InAlAs / using a material system that is lattice-matched to InP on an InP substrate.
InGaAs HEMT, so-called InGaAs HEM
It is an epitaxial layered structure of an InGaAs resonant tunneling structure having a T structure and a double barrier structure in which InGaAs matching with InP is used as a quantum well and InAlAs is used as a barrier, which is further stacked on the T structure, and is described in Document 2. pseudomorphic Al _0.22 Ga _0.78 As-I
Compared to n _0.2 Ga _{0.8 As} HEMTs, the source resistance is reduced, but the RT of the HEMT source, which has the flat valley current region of the present invention, is nevertheless used.
There is a problem that the value of the source resistance is too large for realizing the resonant tunneling transistor in which D is connected. On the other hand, in the conventional example reported in Reference 8 in which the RTD and the FET are connected in parallel to modulate the peak current value of the IV characteristic of the negative differential resistance characteristic type, the FET portion is n-type doped. Undoped A with GaAs layer as channel
Using lGaAs as an insulating barrier layer, so-called D
MT (MIS-like FET with doped channel)
In the RTD portion, GaAs is used as an emitter electrode layer and a collector electrode layer, and AlA is used as a barrier.
s, IN _0.1 G having a composition close to that of GaAs as a quantum well layer
a _0.9 As is used. As a result, the RTD peak current and the FET transconductance values are 1.5 × 10 ³ A / cm ² and 20 m, respectively.
S / mm is a very low value, and these RTD and FE
This is an insufficient value for realizing a high-performance logic gate with the parallel connection of T as a basic element.

In the conventional example of the frequency multiplier using the resonant tunneling transistor according to the reference 4 whose circuit configuration is shown in FIG. 3, frequency-independent multiplication can be obtained without using a phase locked loop, and further three terminals are used. Since the device is used, the output and the input are separated. On the other hand, since the bipolar transistor is basically used, the pn junction between the base and the emitter is forward biased. Therefore, there is a drawback that the circuit configuration becomes complicated, that is, a DC bias power supply VBB is required for the operation, and further, an input resistor RB for converting a signal voltage into a signal current is required. Therefore, the present invention has been made to solve the above-mentioned problems, and its main object is to provide a semiconductor device having a large margin and including a resonant tunnel transistor in which a resonant tunnel diode and a HEMT are connected. It is in.

[0014]

In order to achieve the above object, the present invention is characterized by the following items. That is, (1) a field effect transistor (HEMT) layer having a InAlAs / InGaAs selective doping heterojunction structure lattice-matched with InP on a semi-insulating InP substrate and an I
In a semiconductor device made of a deposited film in which nGaAs-based resonant tunneling diode layers are sequentially laminated, and further, the HEMT and the resonant tunneling diode are connected in series, a substrate is provided between the HEMT layer and the resonant tunneling diode layer, , N ⁺ -InAlAs layer and n ⁺ -InG
HEMT structure cap layer made of aAs layer and n ⁺ -I
A semiconductor device having an epitaxial layer structure in which an nAlAs layer and a stopper layer for selective etching are sequentially stacked. (2) The structure of the HEMT is i-
InAlAs buffer layer, i-InGaAs channel layer, i-InAlAs spacer layer, n ⁺ -InA
The resonance tunnel diode has a structure in which a collector contact layer of n ⁺ -InGaAs, a collector layer of n-InGaAs, and an i-I are formed in this order from the substrate side.
nGaAs first spacer layer, i-AlAs first spacer layer
Barrier layer, i-InGaAs / i-InAs / having a laminated structure in which an i-InAs layer is inserted in the i-InGaAs layer.
A quantum well layer made of i-InGaAs, a second barrier layer of i-AlAs, a second spacer layer of i-InGaAs, an emitter layer of n-InGaAs, and n ⁺ -In.
The semiconductor device according to (1), which comprises an emitter contact layer of GaAs. (3) A field effect transistor (HEMT) layer having an InAlAs / InGaAs selectively doped heterojunction structure lattice-matched to InP on a semi-insulating InP substrate and I
A semiconductor device, in which a HEMT and a resonant tunnel diode are connected in parallel, which is made of a deposited film in which nGaAs-based resonant tunnel diode layers are sequentially stacked,
Between the T layer and the resonance tunnel diode layer, from the substrate side,
A semiconductor device having an epitaxial layer structure in which a cap layer having a HEMT structure composed of an n ⁺ -InAlAs layer and an n ⁺ -InGaAs layer and an n ⁺ -InAlAs layer as a stopper layer for selective etching are sequentially stacked. (4) The structure of the HEMT is i-
InAlAs buffer layer, i-InGaAs channel layer, i-InAlAs spacer layer, n ⁺ -InA
The resonance tunnel diode has a structure in which a collector contact layer of n ⁺ -InGaAs, a collector layer of n-InGaAs, and an i-I are formed in this order from the substrate side.
nGaAs first spacer layer, i-AlAs first spacer layer
Barrier layer, i-InGaAs / i-InAs / having a laminated structure in which an i-InAs layer is inserted in the i-InGaAs layer.
A quantum well layer made of i-InGaAs, a second barrier layer of i-AlAs, a second spacer layer of i-InGaAs, an emitter layer of n-InGaAs, and n ⁺ -In.
The semiconductor device according to (3), which comprises an emitter contact layer of GaAs. (5) The n ⁺ -In of the resonant tunnel diode structure
The source electrode is HE on the GaAs emitter contact layer.
A gate electrode is formed on the i-InAlAs barrier layer of the MT structure, and a drain electrode is formed on the surface of the cap layer of the HEMT structure at a position facing the resonant tunneling diode structure with the gate electrode interposed therebetween. The semiconductor device according to (1) or (2), which is formed. (6) The source electrode is connected to a low-potential power line, the drain electrode is connected to a high-potential power line via a load resistor, and an input signal is applied to the gate electrode (5) ) The semiconductor device as described above.

In the present invention, the RTD is provided on the source side of the HEMT.
In a resonance tunnel transistor having a configuration of connecting
As a non-alloy ohmic contact layer of HEMT,
N ⁺ type InAlAs upper layer n ⁺ -InGaAs, the lower layer
-Layered n ⁺ -InGaAs / n ⁺ -In layer
By using the AlAs cap layer, the parasitic resistance of the resonance tunnel transistor is reduced, and a new device characteristic which has not existed before is realized. That is, below a certain gate voltage, the IV characteristic of the present resonant tunnel transistor shows the gate voltage dependence of the IV characteristic similar to that of the FET, and above a certain gate voltage, the negative differential characteristic type I characteristic of RTD. In addition to the -V characteristic, the drain current Id does not depend on the drain voltage Vd in the valley current region, that is, a flat valley current characteristic.

FIG. 4 is a diagram conceptually showing the structure of the present resonant tunnel transistor (hereinafter referred to as RTT). That is, H
The RTD is connected in series to the source side of the EMT. Further, the present resonance tunnel transistor has a common source arrangement, in which the source electrode connected to the RTD is connected to the ground side potential and the drain electrode connected to the HEMT is connected to the high potential side power supply wiring. S'is a symbol for explaining the IV characteristic of this RTT, and HE
It represents the floating source electrode of MT.

In FIG. 5, the gate voltage is changed from -0.3V to 0.V.
The experimental result of the IV characteristic of RTT of this invention when changing to 6V is shown. That is, the gate voltage VGS
Between −0.3 V and 0.3 V, the current value of the HEMT is lower than the current value of the RTD, so the current value of the RTT is determined by the HEMT. That is, the IV of the FET
It becomes a characteristic. At this time, the voltage across the RTD is below the peak voltage. The gate voltage value is further increased to 0.5
When it reaches V, the current flowing through the FET becomes large enough,
It can be higher than the RTD peak current. But R
Since the TD cannot flow a current larger than the peak current, the RTD transitions from the peak to the valley when the current that can flow in the FET becomes larger than the peak current of the RTD.
Therefore, the current flowing through the RTT drops to a value determined by the valley current of the RTD. On the other hand, at this time, the voltage across the RTD increases from the peak voltage to the value of the valley voltage. If the parasitic resistance of this RTT is small enough,
This increase in the voltage of the RTD returns to the increase in the potential of the floating source electrode S ′ of the HEMT as it is. Therefore, the potential difference between the gate electrode of the HEMT and the floating source electrode S ′ is reduced, and the current that can flow through the HEMT is also reduced. Therefore, the RTD is a driving element,
Considering the load curve when the HEMT is viewed as a load element, when the RTD switches to the valley, the effective gate voltage VGS 'of the HEMT decreases, and the current value at the intersection of the load curves further decreases.

FIG. 6 is a diagram for explaining this situation. That is, the IV characteristic of the RTD that is a constituent element of the resonant tunnel transistor (RTT) that is a series connection of the RTD and the HEMT of the present invention and the HEMT that is the other constituent element are regarded as a load on the RTD. HEMT
4 shows the IV characteristic of In the figure, 1 and 2 are HEMTs of the constituent elements of the present RTT with sufficiently reduced source resistance.
1 is a characteristic immediately before the RTD is switched from the peak to the valley, and 2 is a characteristic after the RTD is switched from the peak to the valley. 1'and 2'are HEMT IVs which are components of a conventional RTT having a large source resistance.
It is a characteristic. If the source resistance of the HEMT is large as in the conventional case, it is necessary to increase the bias voltage in order to obtain the intersection near the peak as shown in the figure. Since the bias voltage becomes large and the source resistance of the HEMT becomes large, the current value at the intersection when the RTD switches from the peak to the valley also becomes high. From the above description, in order to suppress the exponential current increase of the RTD in the valley current region and keep the valley current at a low value and to obtain a flat valley current characteristic, the source resistance is set to Clearly, it is an important point to make it low enough.

The present invention has been made on the basis of the above consideration. Therefore, as a non-alloy ohmic contact layer of HEMT capable of reducing the above-mentioned source resistance, n ⁺ -InGaAs is formed in the upper layer and n ⁺ -InGaAs is formed in the lower layer. ⁺ -InA
Two-layered n ⁺ -InGaAs / n ⁺ using 1As layer
-InAlAs cap layer is used. Another point where a flat valley current is obtained is that as the drain voltage increases in the valley region, the voltage drop at the RTD increases, so that the effective gate voltage VGS 'of the HEMT becomes smaller, as described above. . Therefore, HE
The current flowing through MT becomes small, and as a result, this RTT
This is because a mechanism that suppresses an increase in current flowing through the device works. Also in this case, in order for this mechanism to work effectively,
It goes without saying that the reduction of parasitic resistance is important. As described above, in the present RTT, when the gate voltage exceeds a certain value, the IV characteristic showing the negative differential resistance characteristic of the RTD is obtained, and the valley current region becomes flat in a wide drain voltage range. The characteristics are obtained. For this reason,
When a circuit is constructed by connecting a load resistor to this device, for example, the operation margin is wide.

[0020]

BEST MODE FOR CARRYING OUT THE INVENTION On a semi-insulating InP substrate, In
Field effect transistor (HEM) having InAlAs / InGaAs selectively doped heterostructure lattice-matched to P
T) layer and an InGaAs-based resonant tunneling diode layer are sequentially stacked to form a deposited film.
And a resonance tunnel diode electrically connected in series or in parallel, wherein a HEMT
N ⁺ from the substrate side between the layer and the resonance tunnel diode layer
It is a feature of the invention that a non-alloy ohmic contact layer made of an -InAlAs layer and an n ⁺ -InGaAs layer is inserted, and a selective etching stopper layer made of n ⁺ -InAlAs is inserted thereon.

[0021]

Embodiments of the present invention will be described below in detail with reference to the drawings. (Embodiment 1) FIG. 7 schematically shows a sectional structure of a semiconductor device according to a first embodiment of the present invention. Table 1 shows the epitaxial layer structure. The important point is to reduce HE source resistance, HE
As a non-alloy ohmic contact layer of MT structure,
N ⁺ type InAlAs upper layer n ⁺ -InGaAs, the lower layer
-Layered n ⁺ -InGaAs / n ⁺ -In layer
That is, the AlAs cap layer was used. This allows
The value of the non-alloy ohmic contact resistance is determined by
^{+ −} 0.9 Ωm when using InGaAs cap layer
It was possible to reduce from m to 0.08 Ωmm to 1/10 or less. Further, in this embodiment, in order to increase the reproducibility and uniformity of Vth of HEMT, the above n ⁺ -InG is used.
aAs / n ⁺ -InAlAs cap layer and the above InG
A second n ⁺ -InAlAs layer highly doped with Si, which is an n-type dopant, was interposed as a selective etch stopper between the aAs resonant tunneling structures. FIG. 5 already described is an experimental result of the IV characteristic when the gate voltage is changed from -0.3V to 0.6V in the semiconductor device according to the first embodiment. (For the explanation of the experimental results and the mechanism, refer to the above explanation)

[0022]

[Table 1]

(Embodiment 2) FIG. 8 shows a circuit configuration of a semiconductor device according to a second embodiment of the present invention. That is, the InGaAs HEMT and the InGa according to claim 2
For a semiconductor device (hereinafter referred to as a resonance tunnel HEMT) including a series connection of As resonance tunnel diodes,
A load resistance is inserted in series between the drain electrode and the high-potential-side power supply wiring, and an output terminal is connected to a connection point between the drain electrode and the load resistance. This is a semiconductor device in which a gate voltage as an input signal is applied to the electrodes.

FIG. 9 is a diagram for explaining the operation when the semiconductor device according to the second embodiment is used as a frequency multiplier. A frequency doubler and a frequency tripler can be realized simply by changing the magnitude of the input amplitude. This frequency multiplier has a feature that the circuit configuration on the input side is simplified because the input is directly connected to the gate. That is, the bias power supply and the bias resistor are unnecessary on the input side. Similarly, input directly to the gate,
It has a feature that a power gain can be obtained because it is configured to be connected.

FIG. 10 is a diagram showing an experimental result of an operation when the semiconductor device according to the second embodiment is used as a frequency multiplier. The figure (a) shows the operation as a frequency doubler, and the figure (b) shows the operation as a frequency tripler. In the second embodiment shown in FIG. 9, the case where a resistor is used as an element interposed between the drain electrode and the high-potential power supply line has been described, but when used as a frequency multiplier, it is more general. It goes without saying that this is done through an element having multiple impedances.

(Embodiment 3) The characteristics shown in FIG. 9 of the semiconductor device according to the second embodiment can be directly applied to the construction of a literal which is one of the basic gates of multivalued logic.

FIG. 11A is a diagram schematically showing an example of a literal operation. In this example, "0",
For the input V _in that takes three values of “1” and “2”, the input V
Only when _in is "1", "1" is obtained as the output V _literal , and in other cases, "0" is obtained as the output V _literal.
Has been obtained. FIG. 11B is a diagram showing an experimental result of the operation when the semiconductor device according to the second embodiment is used as a literal, more accurately as an inverted literal. An inverted literal operation is obtained as the operation. That is, "0", "1", to the input V _in taking the three values of "2", only when the input V _in is "1", "0" is obtained as an output V _literal, otherwise To the output V _literal
“1” is obtained as It is needless to say that the inverted literal is a logic gate which is significant in the multi-valued logic as it is, and a literal can be easily realized by inverting this output by an inverter using a HEMT. A feature of using the semiconductor device according to the second embodiment as a literal is that a simple circuit configuration is possible. FIG. 12 schematically shows a sectional structure of a semiconductor device according to a third embodiment of the present invention. In this embodiment, as shown in FIG. 12, basically n ⁺ -InAlA is used.
In consisting of s carrier supply layer and InGaAs channel
A quantum well of a layered structure in which a HEMT having a lattice matching with a P substrate and InGaAs used as a collector and an emitter, AlAs as a barrier layer, and an i-InAs layer inserted in an i-InGaAs layer are stacked on the HEMT structure It is a semiconductor device in which RTDs composed of are connected in parallel. The detailed epitaxial layer structure is the same as that shown in Table 1, and the detailed description is omitted. The semiconductor device in which the RTD is connected to the source side of the HEMT shown in FIG. 7 and in which the HEMT and the RTD are connected in series is different in that the HEMT and the RTD are connected in parallel in this embodiment. Particularly important points are 1) n ⁺ -InGaAs / n ⁺ -from the upper layer side as a layer immediately above the i-InAlAs Schottky barrier layer.
The parasitic resistance of the parallel circuit is reduced by using the laminated non-orloy ohmic contact layer made of InAlAs, and 2) the above n ⁺ -InGa is used.
The use of a selective etching stopper made of an n ⁺ -InAlAs layer immediately above the As / n ⁺ -InAlAs non-orloy ohmic contact layer significantly improves the controllability and uniformity of VTH of HEMT. .
Therefore, there is a feature that the operation margin of various functional logic circuits using the parallel connection of HEMT and RTD is increased. The points of the parallel configuration are shown in FIG.
To explain, first, a gate electrode is formed in the i-InAlAs Schottky barrier layer of HEMT. Also,
N ⁺ -InGaAs on top of RTD, and HEMT
On the surface of the n ⁺ -InGaAs / n ⁺ -InAlAs non-orloy ohmic contact layer, and at a position facing the RTD structure with the gate electrode interposed therebetween.
An electrode made of Ti / Pt / Au is formed at each position, these two electrodes are connected in parallel to form a drain electrode, and further, n ⁺ -InGaAs / n of HEMT is formed.
A parallel connection of HEMT and RTD is realized by forming a source electrode on the surface of the ⁺ -InAlAs non-orloy ohmic contact layer at a position between the gate electrode and the RTD. The first embodiment (RTD and HEMT connected in series) shown in FIG. 7 and the second embodiment (RTD and HEMT connected in parallel) shown in FIG. 12 have the same epitaxial layer structure. , In
It is also characterized by the monolithic integration of HEMTs and RTDs using P-based materials. On this monolithically integrated wafer, the peak current of the RTD is 6.2 × 10 ⁴ A / cm with respect to the peak current / valley current ratio of 7.8.
^A large value of ² was obtained. Regarding the HEMT transconductance gm, 850 mS / mm was obtained for a gate length of 0.7 μm. Comparing these values with the results of Document 3 or Document 8 of the conventional example, it can be seen that the values are significantly improved. In a monolithically integrated wafer, the gm of HEMT is
Compared to the case where only T was produced on the wafer, the excellent value was comparable to that of HE using InP-based material.
In the monolithic integration of MT and RTD, n ⁺ -In
It is shown that good controllability of gm was obtained by using the selective etching stopper made of the AlAs layer. FIG. 13 shows an experimental result of the IV characteristic of the semiconductor device in which the HEMT and the RTD are connected in parallel according to the third embodiment. Specifically, one RTD has a gate width of 2.5μ.
The gate voltage dependence of the IV characteristic of the element which connected three types of HEMT of m, 5 micrometers, and 10 micrometers in parallel is shown. In order to make the display of the figure easier to see, the origin of the x-axis is shifted by 0.6 V and 1.2 V for gate widths of 5 μm and 10 μm, respectively. As shown in FIG. 13, the IV characteristic of the parallel circuit is a negative differential type, the peak current is modulated by the gate voltage applied to the gate electrode of the HEMT, and the degree of modulation is gated. You can see that it is proportional to the width.

[0028]

As described above, according to the semiconductor device of the present invention, when the gate voltage exceeds a certain value, the IV characteristic showing the negative differential resistance characteristic of the RTD can be obtained and the valley current region can be obtained. However, it is possible to obtain the characteristic that it becomes flat in a wide drain voltage range. Therefore, when a circuit is configured by connecting a load resistor to this device, for example, it has a great feature that the operation margin is widened. Further, with a very simple circuit configuration, it is possible to realize a literal of a frequency multiplier and a basic gate in multivalued logic.

[Brief description of the drawings]

FIG. 1 shows a conventional example of an IV characteristic as a function of gate voltage of a transistor in a RTD and FET series configuration. (A) shows the characteristics of the RTD connected to the HEMT source, and (b) shows the characteristics of the RTD connected to the HEMT drain.

FIG. 2 shows a conventional example of an epitaxial structure in which an InGaAs HEMT structure and an InGaAs resonance tunnel structure are stacked.

FIG. 3 shows a conventional example of a circuit configuration of a frequency multiplier using a resonant tunnel transistor. A frequency multiplier using a resonant tunneling bipolar transistor (RTBT) in which two resonant tunneling diodes connected in series are inserted in a part of the base of the bipolar transistor.

FIG. 4 conceptually shows the configuration of the present resonant tunnel transistor. In this configuration, the RTD is connected in series on the source side of the HEMT. Further, the present resonance tunnel transistor has a common source arrangement, in which the source electrode connected to the RTD is connected to the ground side potential and the drain electrode connected to the HEMT is connected to the high potential side power supply wiring.

FIG. 5 is an IV when the gate voltage of the resonance tunnel transistor of the present invention is changed from −0.3V to 0.6V.
It is an experimental result of characteristics.

FIG. 6 is an IV characteristic of an RTD that is a component of a resonant tunnel transistor (RTT) that is a series connection of an RTD and a HEMT of the present invention, and HE that is the other component.
HEMT IV when MT is seen as load on RTD
Characteristic. In the figure, 1 and 2 are the IV characteristics of the HEMT of the constituent elements of the present RTT with sufficiently reduced source resistance,
1 is the characteristic before the RTD switches from peak to valley, and 2 is the characteristic after the RTD switches from peak to valley. 1'and 2'are conventional RTs with large source resistance
HEMT IV characteristics of T components.

FIG. 7 schematically shows a cross-sectional structure of a semiconductor device according to a first embodiment of the present invention.

FIG. 8 shows a circuit configuration of a semiconductor device according to a second embodiment of the present invention. That is, I according to claim 2
A load resistance is inserted in series between the drain electrode and the high-potential-side power supply wiring for a semiconductor device (hereinafter referred to as a resonance tunnel HEMT) including a series connection of an nGaAs HEMT and an InGaAs resonance tunnel diode. An output terminal is connected to a connection point between the drain electrode and the load resistor, and a semiconductor device is obtained by applying a gate voltage as an input signal to the gate electrode.

FIG. 9 is a diagram illustrating an operation when the semiconductor device according to the second embodiment is used as a frequency multiplier.

FIG. 10 is a diagram showing an experimental result of an operation when the semiconductor device according to the second embodiment is used as a frequency multiplier.
(A) shows an operation as a frequency doubler, and (b) shows an operation as a frequency tripler.

FIG. 11 is a diagram showing an experimental result of an operation when the semiconductor device according to the second embodiment is used as a literal. The operation is an inverted literal operation in which the literal output is inverted.

FIG. 12 schematically shows a sectional structure of a semiconductor device according to a third embodiment of the present invention. HEMT and RTD
Are connected in parallel.

FIG. 13 is a HEMT and RT according to a third embodiment of the present invention.
The experimental result of the IV characteristic of the semiconductor device of the parallel connection of D is shown. Specifically, one RTD has a gate width of 2.
The gate voltage dependence of the IV characteristic of the element which connected in parallel 3 types of HEMT of 5 micrometers, 5 micrometers, and 10 micrometers is shown. Gate width of 5 μm for easy viewing
And the gate width of 10 μm, the origin of the x-axis is shifted by 0.6 V and 1.2 V, respectively.

[Explanation of symbols]

 Tr1 RTBT VBB DC bias power supply RB Input base resistance Rc Collector resistance Vcc Collector voltage

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Internal reference number FI technical display location H01L 21/338 29/812 29/88

Claims (6)

[Claims] 1. A field effect transistor (HEMT) having an InAlAs / InGaAs selectively doped heterojunction structure lattice-matched to InP on a semi-insulating InP substrate.
Between a HEMT layer and a resonant tunneling diode layer in a semiconductor device made of a deposited film in which a layer and an InGaAs-based resonant tunneling diode layer are sequentially stacked, and further the HEMT and the resonant tunneling diode are electrically connected in series. to, from the substrate side, a cap layer of n ⁺ type InAlAs layer and n ⁺ -InGaAs layer than made HEMT structure with n ⁺ type InAlAs
A semiconductor device having an epitaxial layer structure in which a layer is sequentially laminated with a selective etching stopper layer. 2. The structure of the HEMT comprises an i-InAlAs buffer layer and an i-InGaAs in order from the substrate side.
Channel layer, i-InAlAs spacer layer, n ⁺
-InAlAs carrier supply layer and i-InAl
The barrier layer is made of As, and the structure of the resonant tunneling diode is such that the collector contact layer of n ⁺ -InGaAs and n-
InGaAs collector layer, i-InGaAs first spacer layer, i-AlAs first barrier layer, i-In
A quantum well layer composed of i-InGaAs / i-InAs / i-InGaAs having a laminated structure in which an i-InAs layer is inserted in a GaAs layer, a second barrier layer of i-AlAs, i-
InGaAs second spacer layer, n-InGaAs
2. The semiconductor device according to claim 1, wherein the semiconductor device comprises an emitter layer of n ⁺ -InGaAs and an emitter contact layer of n ⁺ -InGaAs. 3. A field effect transistor (HEMT) having an InAlAs / InGaAs selectively doped heterojunction structure lattice-matched to InP on a semi-insulating InP substrate.
Between a HEMT layer and a resonant tunnel diode layer in a semiconductor device made of a deposited film in which a layer and an InGaAs-based resonant tunnel diode layer are sequentially stacked, and further the HEMT and the resonant tunnel diode are electrically connected in parallel. to, from the substrate side, a cap layer of n ⁺ type InAlAs layer and n ⁺ -InGaAs layer than made HEMT structure with n ⁺ type InAlAs
A semiconductor device having an epitaxial layer structure in which a layer is sequentially laminated with a selective etching stopper layer. 4. The structure of the HEMT is such that an i-InAlAs buffer layer and an i-InGaAs are sequentially arranged from the substrate side.
Channel layer, i-InAlAs spacer layer, n ⁺
-InAlAs carrier supply layer and i-InAl
The barrier layer is made of As, and the structure of the resonant tunneling diode is such that the collector contact layer of n ⁺ -InGaAs and n-
InGaAs collector layer, i-InGaAs first spacer layer, i-AlAs first barrier layer, i-In
A quantum well layer composed of i-InGaAs / i-InAs / i-InGaAs having a laminated structure in which an i-InAs layer is inserted in a GaAs layer, a second barrier layer of i-AlAs, i-
InGaAs second spacer layer, n-InGaAs
4. The semiconductor device according to claim 3, comprising an emitter layer of n ⁺ -InGaAs and an emitter contact layer of n ⁺ -InGaAs. 5. The resonant tunneling diode structure of said n ⁺
A source electrode on the emitter contact layer of InGaAs, a gate electrode on the barrier layer of the i-InAlAs having a HEMT structure, and a surface of the cap layer of the HEMT structure with the gate electrode sandwiched therebetween; The semiconductor device according to claim 1 or 2, wherein a drain electrode is formed at a position facing the tunnel diode structure. 6. The source electrode is connected to a low potential power line, the drain electrode is connected to a high potential power line through an element having a plurality of impedances, and an input signal is applied to the gate electrode. The semiconductor device according to claim 5, which is characterized in that.