JPH0916121A - Artificial half-tone image display device for display panel - Google Patents

Abstract

PURPOSE: To make an artificial half-tone display as to all input signal levels and make a display having no lack of linearity even when the gradation differences of the display panel are not constant. CONSTITUTION: The device which displays an artificial half-tone image on a display panel is provided with a threshold point setting circuit 22 which sets intersections S0-S3 of the straight line connecting the maximum point and minimum point of an input level and respective m-bit (m<=n-1) display levels as threshold points by using the characteristic diagram of the display panel showing the relation of the display levels to an (n)-bit input video signal, and also provided with a comparing circuit 24 which outputs a lower display level (k) between the display levels corresponding to the set threshold points on both the sides of the input video signal; and an artificial half-tone processing circuit 32 adds the display level 1 to the display level (k) at the ratio D1/D2 of the arithmetic values D1 and D2 of an arithmetic circuit 28 to perform artificial half-tone processing. The artificial half-tone processing can be performed as to all the display levels and even if the gradation differences are not constant, the artificial half-tone display can be made without spoiling the linearity.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a plasma display panel (PDP) and a liquid crystal display panel (LCD).
P) and the like, the present invention relates to a display device for displaying a pseudo halftone image. More specifically, the present invention relates to a display device that displays a pseudo-halftone image on a display panel having a display level of m bits (m ≦ n−1) by performing pseudo-halftone processing on an n-bit input video signal.

[0002]

2. Description of the Related Art Recently, as a thin and lightweight display device, P
Attention is paid to DP display devices. The drive system of this PDP display device is completely different from the conventional CRT drive system, and is a direct drive system by a digitized video input signal. Therefore, the luminance gradation emitted from the panel surface is determined by the number of bits of the signal to be handled. PDPs are divided into two types, AC type and DC type, which have different basic characteristics. Among these, AC type PDPs have sufficient characteristics in brightness and life, but in gradation display, they are prototype level. However, there was only a report of displaying up to 64 gradations.
Recently, a future 256-gradation method based on the address / display separation type driving method (ADS subfield method) has been proposed.

This is because one frame has a relative luminance ratio of 1,
It consists of eight subfields of 2, 4, 8, 16, 32, 64, and 128, and 25 combinations of luminance of eight screens
6-gradation display is performed. Each subfield is composed of an address period for writing refreshed data for one screen and a sustain period for determining the brightness level of the subfield. In the address period, first, wall charges are initially formed on each pixel at the same time for the entire screen, and then a sustain pulse is applied to the entire screen to perform display.
The brightness of the subfield is proportional to the number of sustain pulses and is set to a predetermined brightness. In this way, 256 gradation display is realized.

In the above-described AC driving method, as the number of gradations increases, the number of bits in an address period as a preparation period for lighting and emitting a panel within one frame period increases. The period becomes relatively short, and the maximum luminance decreases. In this way, if the number of bits of the signal to be handled is increased, the image quality is improved, but the light emission luminance is lowered. Conversely, if the number of bits of the signal to be handled is reduced, the light emission luminance is increased, but gradation display is reduced. This causes deterioration of image quality.

Therefore, a display device has been proposed which displays a pseudo-halftone image on a display panel having a display level of m bits (m≤n-1) by performing pseudo-halftone processing on an n-bit input video signal. There is. In a display device displaying such a pseudo halftone image, the pseudo halftone processing as shown in FIG. 4 or FIG. 5 has been conventionally performed.

In the pseudo halftone processing shown in FIG. 4, n = 4,
This shows a case of a display panel in which m = 2 and a constant gradation difference, and pseudo halftone processing is performed at display levels “0” and “1” while the input level of the video signal is “0000” and “0011”. Input level "0100" and "011".
Pseudo-halftone processing is performed at display levels "1" and "2" between 1 "and pseudo-halftone processing at display levels" 2 "and" 3 "between input levels" 1000 "and" 1011 ". It is something to do. Further, in the pseudo halftone processing shown in FIG. 5, n =
4 shows the case of a display panel in which m = 2 and the gradation difference is not constant, and the pseudo halftone processing method is the same as in the case of FIG.

[0007]

However, in the display device performing the pseudo halftone processing shown in FIG. 4, the pseudo halftone processing is performed when the input signal level is the highest from "1100" to "1111". There is a problem that the tone processing cannot be performed. Further, in the display device performing the pseudo halftone processing shown in FIG. 5, the input signal level is "11".
In addition to being unable to perform pseudo halftone processing between "00" and "1111", the linearity of the characteristics between the input signal level and the display level is impaired because the gradation difference is not constant,
There is a problem that the change in display gradation is not smooth.

The present invention has been made in view of the above-mentioned problems, and it is possible to perform pseudo halftone processing on an input signal of any level, and moreover, the linearity of the characteristic between the input signal level and the display level is obtained. It is an object of the present invention to provide a pseudo halftone image display device for a display panel that is not damaged.

[0009]

According to the present invention, a pseudo halftone image is displayed on a display panel having a display level of m bits (m≤n-1) by performing pseudo halftone processing on an n-bit input video signal. In the display device for displaying, the n
Using the characteristic diagram of the display panel showing the relation of the display level of m bits to the input video signal of bits,
A threshold point setting circuit that sets a threshold point at a point where a straight line connecting the minimum level point and the maximum level point of the input video signal intersects each of the m-bit display levels, and the setting of the input video signal and the threshold point setting circuit On the basis of the display level k output by this comparison circuit, a comparison circuit that compares the threshold level and outputs the lower display level k of the display levels corresponding to the set threshold points on both sides of the input video signal. A threshold point selection circuit that selects setting threshold points on both sides of the input video signal from among the setting threshold points of the threshold point setting circuit; and a low-level selection threshold point of the input video signal and the threshold point selection circuit. A display level k output from a calculation circuit that calculates the difference D1 and the difference D2 between the selection threshold points and a comparison circuit.
And a pseudo-halftone processing circuit for performing a pseudo-halftone processing by adding the display level 1 at the ratio D1 / D2 of the calculated values of the calculation circuit.

[0010]

The threshold point setting circuit uses the characteristic diagram of the display panel showing the relation of the m-bit display level to the n-bit input video signal, and the straight line connecting the minimum level point and the maximum level point of the input video signal is m bits. A point that intersects each display level of is set as a threshold point. For example, for a display panel, a luminance level characteristic representing a relationship between an m-bit display level and an n-bit input video signal is actually measured,
In this measured characteristic diagram, a point where a straight line connecting the minimum level point and the maximum level point of the input video signal level intersects each m-bit display level is set as a threshold point. The comparison circuit compares the input video signal with the set threshold point of the threshold point setting circuit, and outputs the lower display level of the display levels corresponding to the set threshold points on both sides of the input video signal.

The threshold point selection circuit selects the set threshold points on both sides of the input video signal from the set threshold points of the threshold point setting circuit based on the display level output from the comparison circuit. The arithmetic circuit calculates the difference D1 between the input video signal and the low-level selection threshold point of the threshold point selection circuit, and also calculates the difference D2 between the selection threshold points. The pseudo halftone processing circuit has a ratio D1 / D of the operation values of the operation circuit to the display level output from the comparison circuit.
In step 2, the display level 1 is added to perform the pseudo halftone process.

Therefore, in a display panel having an m-bit display level, pseudo halftone display can be performed for all input levels of an n-bit input video signal. Moreover, even if the gradation difference of the m-bit display level of the display panel is not constant, the pseudo halftone display can be performed without impairing the linearity.

[0013]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below with reference to FIGS. In FIG. 1, 20 is an n-bit (for example, 4-bit) video signal input terminal, and 22 is a threshold point setting circuit. The threshold point setting circuit 22 sets the threshold point of the input video signal corresponding to each display level of m bits (for example, 2 bits) of the display panel (for example, PDP) as follows. First, regarding the display panel, a 4-bit input level “0000” of the video signal
2-bit display level "0" for "1111"
The characteristic of "3" is actually measured to obtain the luminance level characteristic as shown by the one-dot chain line P in FIG.

Next, the minimum level point "00" of the input level
A straight line Q (displayed by a dotted line) connecting "00" and the maximum level point "1111" is a 2-bit display level "0", "1",
Points S0, S1, S that intersect with "2" and "3", respectively
2 and S3 are set as threshold points. In FIG. 2, these set threshold points S0, S1, S2, and S3 are “0000” and “0”.
101 ”,“ 1010 ”, and“ 1111 ”. The solid line R in FIG. 2 represents the brightness level characteristic using the set threshold points S0, S1, S2, S3.

Reference numeral 24 is a comparison circuit.
The video signal (Dat input to the video signal input terminal 20
a) and the set threshold points S0 and S of the threshold point setting circuit 22
Input video signal (Data) by comparing 1, S2, S3
Setting threshold points S on both sides of (for example, S2 ≦ Data <S3)
The lower display level “k” of the display levels “k” and “k + 1” (eg, display levels “2” and “3”) corresponding to [k] and S [k + 1] (eg, S2 and S3).
(For example, display level “2”) is output.

Reference numeral 26 is a threshold point selection circuit, and this threshold point selection circuit 26 sets threshold points S0, S1, S2 of the threshold point setting circuit 22 based on the display level "k" output from the comparison circuit 24. , S3, set threshold points S [k] and S [k + on both sides of the input video signal (Data).
1] (for example, S2 and S3) are selected and output.

28 is an arithmetic circuit, and this arithmetic circuit 28 is
Selection threshold point S [k] selected by the threshold point selection circuit 26
And S [k + 1] of the lower selection threshold point S
A coefficient unit 30 that multiplies [k] by a coefficient of -1, and an output value of the coefficient unit 30 is added to the input video signal (Data), and the added value D1 (D1 = Data-S [k]) is pseudo-halftone processed. The first adder 34 that outputs to the circuit 32, and the selected threshold points S [k] and S [k + 1] selected by the threshold point selection circuit 26.
Of the high-level selection threshold points S [k + 1], the output of the coefficient unit 30 is added to obtain an added value D2 (D2 = S [k +
1] -S [k]) to the pseudo-halftone processing circuit 32 and a second adder 36.

The pseudo halftone processing circuit 32 adds the added value D1 of the first adder 34 of the arithmetic circuit 28 to the added value D2 of the second adder 36 at the display level "k" output from the comparison circuit 24. Display level "1" with ratio D1 / D2 divided by
Is added for pseudo halftone display, and video signal output terminal 3
It is configured to output a display signal to a display panel (for example, PDP) via 8.

Next, the operation of the above embodiment will be described with reference to FIG. For convenience of explanation, an input video signal is represented by 4 bits (n = 4, 16 gradations), a display panel (for example, P
The display capability of DP) is set to 2 bits (m = 2, 4 gradations). Further, the threshold point setting circuit 22 sets threshold points S0 (= “0000”) and S1 (= “0 which are obtained by using the brightness level characteristic indicated by the alternate long and short dash line P and the straight line indicated by the dotted line Q in FIG.
101 "), S2 (=" 1010 "), S3 (=" 11 ")
11 ”) is output.

(A) The comparison circuit 24 is configured to compare the video signal Data input to the video signal input terminal 20 with the threshold point setting circuit 2
2 set threshold points S0, S1, S2, S3 are compared, and D
The lower display level “k” of the display levels “k” and “k + 1” corresponding to the set threshold points S [k] and S [k + 1] on both sides of ata is output. When Data is between S2 and S3 (S2 ≦ Data <S3), the display level “2” (k = 2, which is the case where k is the binary number display “10” in FIG. 3) is output. .

(B) The threshold point selection circuit 26 selects the setting threshold points S0, S1, S2 and S3 of the threshold point setting circuit 22 from the setting threshold points S [k] and S [k + on both sides of Data.
1] is selected and output. When Data is between S2 and S3, S2 and S3 (k of S [k] is 2, S [k
(When k + 1 of [+1] is 3) is selected and output.

(C) The arithmetic circuit 28 performs the following arithmetic operations. The coefficient unit 30 uses the S selected by the threshold point selection circuit 26.
The lower level S [k] of [k] and S [k + 1] is multiplied by a coefficient of −1, and the first adder 34 adds the output of the coefficient unit 30 to Data to add value D1 (D1 = Data). -S
[K]) to the pseudo-halftone processing circuit 32, and the second adder 36 selects S [k] and S selected by the threshold point selection circuit 26.
The output of the coefficient unit 30 is added to the higher level S [k + 1] of [k + 1] to obtain the added value D2 (D2 = S [k + 1]
-S [k]) is output to the pseudo halftone processing circuit 32.

When Data is between S2 and S3, D1 = Data-S2 and D2 = S3-S2.
When Data is "1100" in binary display,
As shown in, D1 is “010” in binary notation (D1 =
1100-1010), D2 is a binary number display "101"
(D2 = 1111-1010).

(D) The pseudo halftone processing circuit 32 adds the added value D1 of the first adder 34 of the arithmetic circuit 28 to the added value D2 of the second adder 36 at the display level "k" output from the comparison circuit 24. The display level "1" is added by the ratio D1 / D2 divided by to perform the pseudo halftone process, and the display signal is output to the display panel (for example, PDP) via the video signal output terminal 38 to perform the pseudo halftone display. . When Data is "1100" in binary notation, k is "10" (decimal 2), D1 is "010" (decimal 2), and D2 is "101" (10
Since the decimal number is 5), the pseudo halftone processing circuit 32 changes the display level to "2" (corresponding to k = 2) by 2/5 (D1 / D).
The pseudo halftone process of adding the display level "1" at a ratio of 2) is performed.

(E) When Data is between S0 and S1 (S0≤Data <S1) or between S1 and S2 (S1≤Data <S2), the above-mentioned Data is also used.
Is between S2 and S3 (S2 ≦ Data <S3)
Works in the same way as That is, when Data is between S0 and S1, k is “00”, as shown in FIG.
D1 is “000” to “100”, D2 is “101”, and when Data is between S1 and S2, k is “01” and D1 is “000” to “000” as shown in FIG. 10
0 ”and D2 are“ 101 ”.

For example, when Data is "0001", the pseudo halftone processing circuit 32 displays the display level "0" (k
Pseudo-halftone processing of adding the display level "1" to a ratio of 1/5 (corresponding to D1 / D2) is performed. When Data is “1000”, the pseudo halftone processing circuit 32 changes the display level to “1” (corresponding to k = 1).
Display level "1" at a ratio of 3/5 (corresponding to D1 / D2)
Pseudo halftone processing for adding is performed.

Although the display panel having a constant gradation difference has been described in the above embodiments, the present invention is not limited to this, and a display panel having a constant gradation difference can also be used.

In the above-mentioned embodiment, the threshold point setting circuit is as shown in FIG.
As shown in, the luminance level characteristic of the display panel is measured, and in this measured characteristic diagram, the point where the straight line connecting the minimum level point and the maximum level point of the input video signal level intersects each display level is set as the threshold point. However, the present invention is not limited to this, and the minimum level point and the maximum level point of the input video signal are connected using the characteristic diagram of the display panel showing the relationship of the m-bit display level to the n-bit input video signal. What is necessary is just to set a point where a straight line intersects each display level of m bits as a threshold point.

In the above embodiment, the arithmetic circuit is composed of the coefficient unit and the first and second adders, but the present invention is not limited to this, and the input video signal and the threshold point selecting circuit are not limited to this. The difference D1 from the low-level selection threshold point is calculated, and
What is necessary is just to calculate the difference D2 between the selection threshold points.

In the above embodiment, the case where the display panel is a PDP has been described, but the present invention is not limited to this, and it can be applied to the case of a display panel other than the PDP (for example, LCDP (liquid crystal display panel)). .

[0031]

As described above, according to the present invention, in the pseudo halftone image display device for a display panel, the characteristic diagram of the display panel showing the relation of the m-bit display level to the n-bit input video signal is used. A line connecting the minimum level point and the maximum level point of the input video signal (Data) intersects each display level of m bits (for example, S0 to S0).
A threshold point setting circuit that sets S3) as a threshold point is provided, and a comparison circuit that outputs the lower display level k corresponding to the set threshold points on both sides of the input video signal is provided. , The ratio D1 / D2 of the operation values D1 and D2 of the operation circuit to the display level k output from the comparison circuit.
Then, the display level 1 is added to perform the pseudo halftone process.

Therefore, it is possible to perform display in which pseudo halftone processing has been performed for all input levels of the n-bit input video signal. For example, in the conventional example, the place where the input level is the highest where the pseudo-halftone processing cannot be performed (for example, the input signal level in FIG.
Even up to 11 ”), pseudo halftone processing can be performed. Moreover, even if the gradation difference of the m-bit display level of the display panel is not constant, the pseudo halftone display can be performed without impairing the linearity.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of a pseudo halftone image display device for a display panel according to the present invention.

FIG. 2 is an explanatory diagram showing a method of setting a set threshold point in the threshold point setting circuit of FIG.

FIG. 3 is an explanatory view showing the operation of FIG.

FIG. 4 shows a display panel with a constant gradation difference,
It is explanatory drawing which shows the pseudo halftone process of a prior art example.

FIG. 5 is an explanatory diagram showing pseudo halftone processing of a conventional example in a display panel in which gradation differences are not constant.

[Explanation of symbols]

20 ... Video signal input terminal, 22 ... Threshold point setting circuit,
24 ... Comparison circuit, 26 ... Threshold point selection circuit, 28 ... Arithmetic circuit, 30 ... Coefficient unit, 32 ... Pseudo halftone processing circuit,
34 ... First adder, 36 ... Second adder, 38 ... Video signal output terminal, Data ... Input video signal, D1 ... Calculation value (= Data-S [k]), D2 ... Calculation value (= S [k +
1] -S [k]), k ... Display level, S0-S3 ... Setting threshold point, S [k] ... Selection threshold point (lower), S [k
+1] ... Selection threshold point (higher).

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification number Internal reference number FI Technical indication location G09G 5/02 G06F 15/68 310J (72) Inventor Junichi Onodera 1116 Suenaga, Takatsu-ku, Kawasaki-shi, Kanagawa In stock company Fujitsu General (72) Inventor Masayuki Kobayashi, 1116 Suenaga, Takatsu-ku, Kawasaki City, Kanagawa Prefecture In general company, Fujitsu (72) 1116 Suinaga, Takatsu-ku, Kawasaki City, Kanagawa Prefecture In-house, Fujitsu General (72) Inventor Toru Aida 1116 Suenaga, Takatsu-ku, Kawasaki-shi, Kanagawa Prefecture Fujitsu General Limited

Claims (3)

[Claims] 1. A display level is m bits (m ≦ n−) by performing pseudo halftone processing on an input video signal of n bits.
In the display device for displaying a pseudo-halftone image on the display panel of 1), the minimum level of the input video signal is used by using the characteristic diagram of the display panel showing the relationship of the m-bit display level with respect to the n-bit input video signal. Comparing a threshold point setting circuit that sets a point where a straight line connecting a point and a maximum level point intersects each of the m-bit display levels as a threshold point with the set threshold point of the input video signal and the threshold point setting circuit; A comparator circuit that outputs the lower display level k of the display levels corresponding to the set threshold points on both sides of the input video signal, and the setting of the threshold point setting circuit based on the display level k output by the comparator circuit. A threshold point selection circuit that selects set threshold points on both sides of the input video signal from threshold points, and a low-level selection threshold of the input video signal and the threshold point selection circuit While calculating the difference D1 between the point,
Display level 1 is added to the display level k output by the arithmetic circuit for calculating the difference D2 between the selection threshold points and the comparator circuit at the ratio D1 / D2 of the arithmetic values of the arithmetic circuit to perform pseudo halftone processing. A pseudo-halftone image display device for a display panel, comprising: a pseudo-halftone processing circuit. 2. A threshold point setting circuit actually measures a luminance level characteristic of a display panel showing a relationship of an m-bit display level with respect to an n-bit input video signal, and in the actually measured characteristic chart, a minimum level point of the input video signal is shown. 2. The pseudo halftone image display device for a display panel according to claim 1, wherein a point where a straight line connecting the maximum level points intersects each m-bit display level is set as a threshold point. 3. An arithmetic circuit adds a coefficient multiplier for multiplying a selected threshold point having a lower level among the selected threshold points selected by the threshold point selection circuit by a coefficient of -1, and an output of the coefficient multiplier to an input video signal. Then, the output of the coefficient unit is added to the first adder that outputs the added value D1 to the pseudo-halftone processing circuit and the high-level selection threshold point of the selection threshold points selected by the threshold point selection circuit. The pseudo halftone image display device for a display panel according to claim 1 or 2, comprising a second adder for outputting the added value D2 to the pseudo halftone processing circuit.