JP3353555B2 - Pseudo halftone image display device for display panel - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a plasma display panel (PDP) and a liquid crystal display panel (LCD).
The present invention relates to a display device for displaying a pseudo halftone image on a display panel such as P). More specifically, the present invention relates to a display device that displays a pseudo halftone image on a display panel having a display level of m bits (m ≦ n−1) by performing pseudo halftone processing on an n-bit input video signal.

[0002]

2. Description of the Related Art Recently, as a thin and lightweight display device, P
Attention has been paid to DP display devices. The drive system of this PDP display device is completely different from the conventional CRT drive system, and is a direct drive system using digitized video input signals. Therefore, the luminance gradation emitted from the panel surface is determined by the number of bits of the signal to be handled. PDPs are classified into two types, AC type and DC type, which have different basic characteristics. Among them, the AC type PDP has sufficient characteristics in terms of luminance and life, but for gradation display, it has a prototype level. Reported only up to 64 gradation display.
Recently, a 256-gray scale method using a separate address / display driving method (ADS subfield method) has been proposed.

[0003] This is because one frame has a relative luminance ratio of 1,
It consists of eight subfields of 2, 4, 8, 16, 32, 64, and 128, and 25 combinations of luminance of eight screens
Display of 6 gradations is performed. Each subfield includes an address period in which data for one refreshed screen is written, and a sustain period for determining a luminance level of the subfield. In the address period, first, wall charges are initially formed on each pixel at the same time for the entire screen, and then a sustain pulse is applied to the entire screen to perform display.
The brightness of the subfield is proportional to the number of sustain pulses and is set to a predetermined brightness. In this way, 256 gradation display is realized.

In the above-described AC driving method, as the number of gradations increases, the number of bits in an address period as a preparation period for lighting and emitting a panel within one frame period increases. The period becomes relatively short, and the maximum luminance decreases. In this way, if the number of bits of the signal to be handled is increased, the image quality is improved, but the light emission luminance is reduced. Conversely, if the number of bits of the signal to be handled is reduced, the light emission luminance is increased, but the gradation display is reduced, This leads to lower image quality.

Therefore, a display device has been proposed which displays a pseudo halftone image on a display panel having a display level of m bits (m ≦ n−1) by performing pseudo halftone processing on an n-bit input video signal. I have . In the display device for displaying a halftone image such as this it has traditionally been carried out halftone processing as shown in FIG. 4 or 5.

In the pseudo halftone processing shown in FIG. 4, n = 4,
This shows the case of a display panel in which m = 2 and the gradation difference is constant. The display level is “0” and “1” when the input level of the video signal is “0000” and “0011”, and pseudo halftone processing is performed. And the input levels are “0100” and “011”.
During "1", pseudo halftone processing is performed at display levels "1" and "2", and between input levels "1000" and "1011", pseudo halftone processing is performed at display levels "2" and "3". Is what you do. In the pseudo halftone process shown in FIG.
4 shows a case of a display panel where m = 2 and the gradation difference is not constant, and the method of pseudo halftone processing is the same as that of FIG.

[0007]

However, in the display device which performs the pseudo halftone processing shown in FIG. 4, the pseudo halftone processing is performed when the input signal level is highest from "1100" to "1111". There is a problem that the tone processing cannot be performed. In the display device that performs the pseudo halftone process shown in FIG. 5, the input signal level is “11”.
In addition to not being able to perform pseudo halftone processing between "00" and "1111", the linearity of the characteristic between the input signal level and the display level is impaired because the gradation difference is not constant,
There is a problem that the change in display gradation is not smooth.

The present invention has been made in view of the above-described problems, and can perform pseudo halftone processing with an input signal of any level, and furthermore, the linearity of characteristics between an input signal level and a display level is improved. It is an object of the present invention to provide a pseudo halftone image display device for a display panel that is not damaged.

[0009]

According to the present invention, pseudo halftone processing is performed on an n-bit input video signal, so that a pseudo halftone image is displayed on a display panel having a display level of m bits (m ≦ n−1). In the display device for displaying, the n
In the characteristic diagram of the display panel showing the relationship between the m-bit display level and the m-bit input video signal, a straight line connecting the minimum level point and the maximum level point of the input video signal corresponds to each of the m-bit display levels. Input image of intersection
A threshold point setting circuit that outputs a value of the image signal as a threshold point,
A comparison circuit that compares the input video signal with a set threshold point of the threshold point setting circuit, and outputs a lower display level k of display levels corresponding to the set threshold points on both sides of the input video signal; A threshold point selection circuit for selecting a set threshold point on both sides of the input video signal from among the set threshold points of the threshold point setting circuit based on a display level k output from the comparison circuit; while calculating the difference D1 between the lower level of the selected threshold point of the point selection circuit, an arithmetic circuit for calculating a difference D2 between the selected threshold point, the display level k to the output of the comparator circuit, the operation of the prior SL arithmetic circuit Display level output by the comparison circuit according to the value ratio D1 / D2
a pseudo halftone processing circuit for performing pseudo halftone processing by adding 1 to k .

[0010]

In the characteristic diagram of the display panel showing the relationship between the display level of m bits with respect to the input video signal of n bits, a straight line connecting the minimum level point and the maximum level point of the input video signal is represented by m bits. The value of the input video signal at the point that intersects the display level is output as a threshold point.
For example, for a display panel, a luminance level characteristic representing a relationship between an m-bit display level and an n-bit input video signal is measured, and a straight line connecting the minimum level point and the maximum level point of the input video signal level is m in this measured characteristic diagram. Of the input video signal at the point where
Output the value as the threshold point. The comparison circuit compares the input video signal with the set threshold point of the threshold point setting circuit, and outputs the lower one of the display levels corresponding to the set threshold points on both sides of the input video signal.

The threshold point selection circuit selects the set threshold points on both sides of the input video signal from among the set threshold points of the threshold point setting circuit based on the display level output from the comparison circuit. The arithmetic circuit calculates a difference D1 between the input video signal and a low-level selection threshold point of the threshold point selection circuit, and calculates a difference D2 between the selection threshold points. Halftoning circuitry, according to the ratio D1 / D2 of the arithmetic value of the arithmetic circuit, the comparison circuit outputs Table
Pseudo halftone processing is performed by adding 1 to the indicated level k .

Therefore, a pseudo halftone display can be performed for all input levels of an n-bit input video signal on a display panel having an m-bit display level. In addition, even if the gradation difference of the m-bit display level of the display panel is not constant, pseudo halftone display can be performed without impairing linearity.

[0013]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below with reference to FIGS. In FIG. 1, reference numeral 20 denotes an n-bit (for example, 4 bits) video signal input terminal, and reference numeral 22 denotes a threshold point setting circuit. The threshold point setting circuit 22 is, for example, a display panel (for example, a PDP) obtained as follows.
And outputs the threshold point of the input video signal corresponding to each display level of the m-bit (e.g. 2 bits). First, regarding the display panel, a 4-bit input level “0
The characteristics of the 2-bit display levels "0" to "3" with respect to "000" to "1111" are actually measured, and the luminance level characteristics as shown by the one-dot chain line P in FIG.

Next, the minimum level point of the input level "00"
A straight line Q (indicated by a dotted line) connecting “00” and the maximum level point “1111” is a 2-bit display level “0”, “1”,
Points S0, S1, S that intersect each of "2" and "3"
2, S3 to the threshold point. In FIG. 2, these set threshold points S0, S1, S2, S3 are “0000”, “010”.
1 "," 1010 ", and" 1111 ". The solid line R in FIG. 2 represents the luminance level characteristics using the set threshold points S0, S1, S2, S3.

Reference numeral 24 denotes a comparison circuit.
The video signal (Dat) input to the video signal input terminal 20
a) and the set threshold points S0, S of the threshold point setting circuit 22
1, S2, and S3, and input video signal (Data)
(For example, the set threshold point S on both sides of S2 ≦ Data <S3)
Lower display level “k” of display levels “k” and “k + 1” (eg, display levels “2” and “3”) corresponding to [k] and S [k + 1] (eg, S2 and S3)
(For example, display level “2”).

Reference numeral 26 denotes a threshold point selection circuit. The threshold point selection circuit 26 sets the threshold points S0, S1, S2 of the threshold point setting circuit 22 based on the display level "k" output from the comparison circuit 24. , S3, the set threshold points S [k] and S [k +] on both sides of the input video signal (Data).
1] (for example, S2 and S3) are selected and output.

Reference numeral 28 denotes an arithmetic circuit.
The selection threshold point S [k] selected by the threshold point selection circuit 26
And the low-level selection threshold point S of S [k + 1]
A coefficient unit 30 for multiplying [k] by a coefficient of -1; and an output value of the coefficient unit 30 added to an input video signal (Data), and an added value D1 (D1 = Data-S [k]) is subjected to pseudo halftone processing. A first adder 34 for outputting to the circuit 32, and the selected threshold points S [k] and S [k + 1] selected by the threshold point selection circuit 26
, The output of the coefficient unit 30 is added to the high-level selection threshold point S [k + 1] to obtain an addition value D2 (D2 = S [k +
1] -S [k]) to the pseudo halftone processing circuit 32.

[0018] The pseudo-halftone processing circuit 32, an addition value D1 of the first adder 34 before Symbol arithmetic circuit 28 the second adder 3
The ratio D1 / D2 divided by the added value D2 of 6 Accordingly, the
The display level “k” output from the comparison circuit 24 is added to “1” to perform pseudo halftone display, and a display signal is output to a display panel (for example, a PDP) via the video signal output terminal 38. ing.

Next, the operation of the above embodiment will be described with reference to FIG. For convenience of explanation, an input video signal is composed of 4 bits (n = 4, 16 gradations) and a display panel (for example, P
The display capability of DP) is 2 bits (m = 2, 4 gradations). The threshold point setting circuit 22 sets the set threshold points S0 (= “0000”), S1 (= “0”) obtained using the luminance level characteristic indicated by the dashed-dotted line P and the straight line indicated by the dotted line Q in FIG.
101 ”), S2 (=“ 1010 ”), S3 (=“ 11
11 ") is output.

(A) The comparison circuit 24 is provided with the video signal Data input to the video signal input terminal 20 and the threshold point setting circuit 2
2 are compared with the set threshold points S0, S1, S2, and S3, and D
The lower display level “k” of the display levels “k” and “k + 1” corresponding to the set threshold points S [k] and S [k + 1] on both sides of “ata” is output. When Data is between S2 and S3 (S2 ≦ Data <S3), a display level “2” (k = 2, in FIG. 3, k is a binary number “10”) is output. .

(B) The threshold point selection circuit 26 selects, from among the set threshold points S0, S1, S2, S3 of the threshold point setting circuit 22, the set threshold points S [k] and S [k +
1] and output. When Data is between S2 and S3, k of S2 and S3 (S [k] is 2, S [k
+1] when k + 1 is 3).

(C) The operation circuit 28 performs the following operation. The coefficient unit 30 selects the S selected by the threshold point selection circuit 26.
The low-level S [k] of [k] and S [k + 1] is multiplied by a coefficient of −1, and the first adder 34 adds the output of the coefficient unit 30 to Data to obtain an addition value D1 (D1 = Data). -S
[K]) to the pseudo halftone processing circuit 32, and the second adder 36 selects S [k] and S [k] selected by the threshold point selection circuit 26.
The output of the coefficient unit 30 is added to the high level S [k + 1] of [k + 1] to obtain an addition value D2 (D2 = S [k + 1]).
−S [k]) to the pseudo halftone processing circuit 32.

When Data is between S2 and S3, D1 = Data-S2 and D2 = S3-S2.
When Data is “1100” in binary notation, FIG.
As shown in D1, D1 is “010” in binary notation (D1 =
1100-1010), D2 is “101” in binary notation
(D2 = 1111-1010).

[0024] (d) pseudo halftone processing circuit 32, an addition value D1 of the first adder 34 of the arithmetic circuit 28 second adder 36
Comparison circuit according to the ratio D1 / D2 divided by the sum D2 of
24 is added to the display level "k" output by "1" .
Performs halftoning by a video signal output terminal 38
And outputs a display signal to a display panel (for example, a PDP) via the PDP to perform pseudo halftone display. When Data is "1100" in binary notation, k is "10" (2 in decimal) and D1 as shown in binary notation in FIG.
Is "010" (2 in decimal) and D2 is "101" (1
Since it is 5) in the base 0, the pseudo halftone processing circuit 32
The display level is adjusted according to the ratio of 2/5 (corresponding to D1 / D2).
To "1" is added to the le "2" (equivalent to k = 2)
Perform the pseudo halftone processing Ri.

(E) When Data is between S0 and S1 (S0 ≦ Data <S1) or between S1 and S2 (S1 ≦ Data <S2), the above-mentioned Data
Is between S2 and S3 (S2 ≦ Data <S3)
Works in the same way as That is, when Data is between S0 and S1, k is “00”, as shown in FIG.
D1 is “000” to “100”, D2 is “101”, and when Data is between S1 and S2, k is “01” and D1 is “000” to “000” as shown in FIG. 10
“0” and D2 are “101”.

For example, when Data is "0001"
Indicates that the pseudo halftone processing circuit 32 has 1/5 (D1 / D2
Equivalent) ratio, The display level "0" (k = 0)
This)Add "1"By doingPerform pseudo halftone processing
U. When Data is “1000”, the simulation is being performed.
The halftone processing circuit 32 has a ratio of 3/5 (corresponding to D1 / D2).
rateTo display level "1" (equivalent to k = 1)
Add "1"By doingPerform pseudo halftone processing.

In the above embodiment, a display panel having a constant gradation difference has been described. However, the present invention is not limited to this, and can be applied to a display panel having a non-constant gradation difference.

In the above-described embodiment, the threshold point setting circuit is configured as shown in FIG.
As shown in, the luminance level characteristic of the display panel is actually measured, and a point where a straight line connecting the minimum level point and the maximum level point of the input video signal level intersects with each display level in this measured characteristic diagram is output as a threshold point. However, the present invention is not limited to this, and a straight line connecting the minimum level point and the maximum level point of the input video signal in the characteristic diagram of the display panel showing the relationship between the display level of m bits and the input video signal of n bits is What is necessary is just to output the value of the point which intersects each display level of m bits as a threshold point.

In the above embodiment, the arithmetic circuit is constituted by the coefficient unit and the first and second adders. However, the present invention is not limited to this. While calculating the difference D1 from the low-level selection threshold point,
What is necessary is just to calculate the difference D2 between the selection threshold points.

In the above embodiment, the case where the display panel is a PDP has been described. However, the present invention is not limited to this, and the present invention can be used for a display panel other than a PDP (for example, an LCDP (liquid crystal display panel)). .

[0031]

As described above, according to the present invention, in the pseudo halftone image display device for a display panel , the input video signal is shown in the characteristic diagram of the display panel showing the relationship between the n-bit input video signal and the m-bit display level. The point at which a straight line connecting the minimum level point and the maximum level point of (Data) intersects each display level of m bits (for example, S0 to S
A threshold point setting circuit for outputting the value of 3) as a threshold point is provided, and a comparison circuit for outputting a lower display level k corresponding to a set threshold point on both sides of the input video signal is provided. Circuit, the operation value D of the operation circuit
Output from the comparison circuit according to the ratio D1 / D2 of 1, D2
The pseudo halftone process is performed by adding 1 to the display level k .

Therefore, it is possible to perform display in which pseudo halftone processing is performed for all input levels of the n-bit input video signal. For example, in the conventional example, the highest input level where the pseudo halftone processing could not be performed (for example, when the input signal level in FIG.
11 "), the pseudo halftone process can be performed. In addition, even if the gradation difference of the m-bit display level of the display panel is not constant, pseudo halftone display can be performed without impairing linearity.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of a pseudo halftone image display device for a display panel according to the present invention.

FIG. 2 is an explanatory diagram showing a method of setting a set threshold point in a threshold point setting circuit of FIG. 1;

FIG. 3 is an explanatory diagram showing the operation of FIG. 1;

FIG. 4 shows a display panel with a constant gradation difference.
FIG. 9 is an explanatory diagram showing a pseudo halftone process of a conventional example.

FIG. 5 is an explanatory diagram showing a pseudo halftone process of a conventional example in a display panel in which the gradation difference is not constant.

[Explanation of symbols]

20: video signal input terminal, 22: threshold point setting circuit,
Reference numeral 24: comparison circuit, 26: threshold point selection circuit, 28: arithmetic circuit, 30: coefficient unit, 32: pseudo halftone processing circuit,
34: first adder, 36: second adder, 38: video signal output terminal, Data: input video signal, D1: calculated value (= Data-S [k]), D2: calculated value (= S [k +
1] -S [k]), k: display level, S0 to S3: set threshold point, S [k]: selected threshold point (lower), S [k
+1]... Selection threshold point (higher one).

──────────────────────────────────────────────────の Continuing on the front page (51) Int.Cl. ⁷ Identification symbol FI G09G 5/02 G09G 5/00 520J (72) Inventor Junichi Onodera 1116 Suenaga, Takatsu-ku, Kawasaki-shi, Kanagawa Prefecture Fujitsu General Limited ( 72) Inventor Masayuki Kobayashi 1116 Suenaga, Takatsu-ku, Kawasaki, Kanagawa Prefecture Inside Fujitsu General Limited (72) Inventor Hayato Denda 1116 Suenaga, Takatsu-ku, Kawasaki City, Kanagawa Prefecture Inside Fujitsu General Limited (72) Inventor Toru Aida 1116 Suenaga, Takatsu-ku, Kawasaki City, Kanagawa Prefecture Inside Fujitsu General Limited (56) References JP-A-6-161400 (JP, A) (58) Fields studied (Int. Cl. ⁷ , DB name) G09G 3 / 28 G09G 3/36 G09G 3/20 G09G 5/00 G06T 5/00

Claims (3)

(57) [Claims] A display level is set to m bits (m ≦ n−1) by performing pseudo halftone processing on an n-bit input video signal.
1) A display device for displaying a pseudo halftone image on a display panel according to 1), wherein a characteristic diagram of the display panel showing a relationship between a display level of m bits and an input video signal of n bits is provided.
A point where a straight line connecting the minimum level point and the maximum level point of the input video signal intersects each of the m-bit display levels.
A threshold point setting circuit that outputs the value of the input video signal as a threshold point, and compares the input video signal with a set threshold point of the threshold point setting circuit, and corresponds to a set threshold point on both sides of the input video signal. A comparison circuit that outputs the lower display level k of the display levels; and setting of both sides of the input video signal from among the set threshold points of the threshold point setting circuit based on the display level k output by the comparison circuit. A threshold point selection circuit for selecting a threshold point, and a calculation circuit for calculating a difference D1 between the input video signal and a low-level selection threshold point of the threshold point selection circuit and calculating a difference D2 between the selection threshold points When, according to the ratio D1 / D2 of the arithmetic value before Symbol arithmetic circuit, comparison
A pseudo halftone image display device for a display panel, comprising: a pseudo halftone processing circuit that performs pseudo halftone processing by adding 1 to a display level k output by a circuit . 2. A luminance level characteristic diagram of a display panel showing a relationship between an m-bit display level and an n-bit input video signal created by actual measurement .
At a point where a straight line connecting the minimum level point and the maximum level point of the input video signal intersects each display level of m bits .
2. The method according to claim 1, wherein a value of the input video signal is output as a threshold point.
A pseudo halftone image display device for a display panel according to any one of the preceding claims. An arithmetic circuit for multiplying a low-level selected threshold point among the selected threshold points selected by the threshold point selecting circuit by a coefficient of -1, and adding an output of the coefficient unit to an input video signal; A first adder that outputs the sum D1 to the pseudo halftone processing circuit, and adds the output of the coefficient unit to a high-level selection threshold point among the selection threshold points selected by the threshold point selection circuit. 3. The pseudo halftone image display device for a display panel according to claim 1, further comprising a second adder that outputs the addition value D2 to the pseudo halftone processing circuit.