JPH0916114A - Means for detecting number of vertical lines - Google Patents

Abstract

PURPOSE: To provide a display device which uses digital arithmetic control and can make a proper screen display with small variation by detecting the number of vertical lines having no accidental error without reference to the phase difference between a horizontal and a vertical synchronizing signal. CONSTITUTION: Means 102 and 103 which delay the vertical synchronizing signal, a means which counts the horizontal synchronizing signal inputted in a vertical synchronizing period as to the vertical synchronizing signals before and after the delay, i.e., a means 101 which counts the number of vertical lines, and a means 110 which compares and decides the count result are provided. Then the vertical synchronizing signal is delayed and the detected values of the numbers of vertical lines before and after the delay are compared and decided to detect the number of vertical lines having no accidental error in a short time without reference to the phase difference between the horizontal synchronizing signal and vertical synchronizing signal. Consequently, the digital arithmetic control is performed by using the detection result to make the proper screen display with small variation.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to vertical line number detecting means.

[0002]

2. Description of the Related Art In a multi-scan display, in order to deal with various signal specifications, the horizontal frequency and the vertical frequency of an input signal are detected, and it is determined whether the display is a corresponding signal or not according to the detection result. It controls the deflection circuit and the video circuit. Further, since the detection operation is performed using a digital circuit and the deflection circuit and the video circuit are controlled by digital operation control based on the detection result, it is possible to obtain flexible control characteristics with respect to the specifications of each circuit. A high-quality display can be provided at low cost.

The operation of the conventional multi-scan display will be described below with reference to FIG. In FIG.
Is a sync separation circuit, 202 is a video circuit, 203 is a deflection circuit, 204 is a cathode ray tube and a deflection yoke, 205 is horizontal frequency detection means, 206 is vertical frequency detection means, 20
Reference numeral 7 is a digital arithmetic control means. Separate sync signal (H
(S and VS), or the composite sync signal (CS), or the composite sync signal superimposed on the video signal is input to the display, the sync separation circuit 201 separates the horizontal and vertical sync signals, and further the horizontal frequency detecting means. 20
5 and vertical frequency detecting means 206 respectively obtain horizontal frequency information and vertical frequency information. The digital operation means 207 controls the deflection circuit and the video circuit by digital operation control based on the detection result (for example, operation / stop control of the circuit, control of screen display size, position, distortion correction, etc. according to the synchronization frequency). ).

As described above, the method of detecting the horizontal frequency and the vertical frequency of the input signal by using the digital circuit is as follows.
As described in JP-A-5-88635,
There is a method in which the number of horizontal synchronization signals between vertical periods, that is, the number of vertical lines is counted as horizontal frequency information, and the number of vertical periods is counted using a reference clock as vertical frequency information.

An embodiment of the vertical line number detecting means according to the prior art will be described below with reference to FIG. In FIG. 4, 401 is a horizontal synchronizing signal counting means (counter),
Reference numerals 402 and 403 are means for holding the count value. Counter 4
01 continues counting the input horizontal synchronizing signal. When the vertical synchronizing signal is input, the current horizontal synchronizing signal count value is held in the holding unit 402, and the holding unit 403 holds the previous horizontal synchronizing signal count value. Therefore, the holding means 40
The difference between the contents of 2 and 403 is the vertical line number detection value FH.
Becomes

Here, since the horizontal synchronizing signal and the vertical synchronizing signal are synchronized, the vertical line number detection value is theoretically uniquely determined, and the detection value does not include a random error. However, in reality, when the vertical synchronizing signal is input, that is, when the horizontal synchronizing signal is input at the start and end of counting the number of vertical lines, a slight phase fluctuation of the horizontal synchronizing signal and the vertical synchronizing signal, and vertical line Due to instability factors such as setup time and hold time in the number counting means, an accidental error of ± 1 occurs in the detected value of the number of vertical lines.

[0007]

In the prior art, the vertical line number detection value has an accidental error of ± 1. Therefore, when digital detection control of the screen display is performed using the detection value, the calculation result is also the same. Fluctuates. Thus, for example,
Even if the same signal is received, there is a problem that the screen display state changes greatly each time it is received. In addition, when trying to eliminate this error by averaging, a processing time that is an integral multiple of the vertical period is required, which causes a problem that the response becomes poor.

SUMMARY OF THE INVENTION An object of the present invention is to provide a display device capable of displaying an appropriate and less variable screen using digital arithmetic control by detecting the vertical line number without accidental error in a short time. It is in.

[0009]

In order to achieve the above object, according to the present invention, a means for delaying a vertical synchronizing signal and a horizontal synchronizing signal which is input during a vertical period for each of the vertical synchronizing signal before and after the delay. A means for counting the signals, that is, a means for counting the number of vertical lines and a means for comparing and discriminating the counting results are provided.

[0010]

According to the present invention, the vertical synchronizing signal is delayed, and the vertical line number detection values before and after the delay are compared and discriminated, so that the vertical synchronizing signal is randomly detected regardless of the phase difference between the horizontal synchronizing signal and the vertical synchronizing signal. Since it is possible to detect the number of vertical lines that does not include a physical error in a short time, it is possible to perform digital arithmetic control using the detection result and display an appropriate screen with little fluctuation.

[0011]

An embodiment of the present invention will be described below.

FIG. 1 is a block diagram showing an embodiment of the present invention, and FIG. 3 is a vertical line number detection timing chart according to the present invention.

In FIG. 1, 101 is a horizontal synchronizing signal counting means (counter), 102 and 103 are delay means, and 104.
Numerals 109 are holding means for counting values, and 110 is a comparing and judging means.

The counter 101 keeps counting the input horizontal synchronizing signal. When the vertical synchronizing signal is input, the current horizontal synchronizing signal count value is held in the holding means 104, and the holding means 105 holds the previous horizontal synchronizing signal count value. Therefore, the difference between the contents of the holding means 104 and the contents of the same means 105 becomes the vertical line number detection value FH0, which is input to the comparison / determination means 110.

Similarly, the holding means 106 to 109 obtain the vertical line number detection values FH1 and FH2 and input them to the comparison / determination means 110.
The vertical synchronizing signals input to 107, 108, and 109 are delayed by the delay units 102 and 103, respectively.
It is delayed by t, 2Δt. Therefore, the detection timing of the vertical line number detection values FH0, FH1, and FH2 is shown in FIG.
become that way.

In FIG. 3 (a), FH0 is ±± due to the fluctuation of the phase difference between the horizontal synchronizing signal and the vertical synchronizing signal as described above.
However, FH1 and FH2 have a detection start point and an end point of Δt, 2 with respect to FH0, respectively.
Since it is delayed by Δt, it is not affected by the phase difference fluctuation, and no accidental error occurs in the detected value. Further, even if FH1 or FH2 is in a state in which an accidental error occurs as shown in FIGS. 3B and 3C due to the frequency characteristics of the sync separation circuit, the other two detection values are accidentally errored. Does not occur.

From the above, the vertical line number detection values FH0, F
By making a majority decision with respect to H1 and FH2 in the comparison and determination means 110 of FIG. 2, it is possible to obtain the vertical line number detection value FH that does not include an accidental error, regardless of the phase difference between the horizontal synchronization signal and the vertical synchronization signal. it can.

[0018]

According to the present invention, since it is possible to obtain a vertical line number detection value that does not include a random error, digital arithmetic control of the screen display state is performed using this, and the screen fluctuation occurs each time a signal is received. It is possible to provide a high-quality display screen with less waste.

[Brief description of the drawings]

FIG. 1 is a block diagram of one embodiment of the present invention.

FIG. 2 is a block diagram of a display device.

FIG. 3 is a timing chart of vertical line number detection according to the present invention.

FIG. 4 is a block diagram of a conventional vertical line number detecting means.

[Explanation of symbols]

101 ... Horizontal sync signal counting means, 102, 103 ... Delay means, 104-109 ... Count value holding means, 110 ... Vertical line number detection value comparison / determination means.

Claims (1)

[Claims] 1. A means for delaying a vertical synchronizing signal, a means for counting horizontal synchronizing signals between vertical periods for each of the vertical signal before delaying and the vertical synchronizing signal after delaying, and counting of the horizontal synchronizing signal. A vertical line number detecting means for providing a result comparing means for obtaining the number of vertical lines which does not include a random error by the comparing means.