JPH09160076A - Array substrate for display device and its production - Google Patents

Abstract

PROBLEM TO BE SOLVED: To make it possible to form auxiliary capacitors and to attain a higher opening rate by superposing scanning lines and pixel electrodes without lowering the yield of production. SOLUTION: This substrate is composed of the scanning lines 111, first insulating films 115, 117 thereon, semiconductor films 120 thereon, thin-film transistors(TFTs) including source electrodes 126b and drain electrodes 126b electrically connected to these semiconductor films 120, signal lines 110 led out of these drain electrodes 126a and intersected approximately with the scanning lines 111 and pixel electrodes 131 electrically connected to the source electrodes 126b. In such a case, the pixel electrodes 131 are electrically connected to the source electrodes 126b via second insulating films 127 arranging on at least the signal lines 110. The pixel electrodes 131 are overlapped on the regions extended from the adjacent scanning lines 111 via the first and second insulating films 115, 117, 127.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a display device array substrate used in a flat display device such as a liquid crystal display device and a method for manufacturing the same.

[0002]

2. Description of the Related Art In recent years, flat-panel display devices that replace CRT displays have been actively developed, and liquid crystal display devices have attracted particular attention because of their advantages such as light weight, thin thickness, and low power consumption.

For example, a light transmission type active matrix type liquid crystal display device in which a switch element is arranged for each display pixel will be described as an example. The active matrix type liquid crystal display device includes a liquid crystal layer held between an array substrate and a counter substrate with an alignment film interposed therebetween. In the array substrate, a plurality of signal lines and scanning lines are arranged in a grid on a transparent insulating substrate such as glass or quartz, and amorphous silicon (hereinafter abbreviated as a-Si: H) is provided at each intersection. (Hereinafter abbreviated as TFT) using a semiconductor thin film of the above. The gate electrode of the TFT is electrically connected to the scanning line, the drain electrode is electrically connected to the signal line, and the source electrode is electrically connected to the transparent conductive material forming the pixel electrode, for example, ITO (Indium-Tin-Oxide). Has been done.

The counter substrate is formed by arranging a counter electrode made of ITO on a transparent insulating substrate such as glass, and arranging a color filter layer if color display is realized.

[0005]

In the liquid crystal display device described above, the potential of the pixel electrode fluctuates due to the parasitic capacitance of the TFT, the leak current generated between the pixel electrode and the counter electrode, and the like. Pixel capacitance (CLc) by overlapping auxiliary capacitance lines through the insulating film
It is known that an auxiliary capacitance (Cs) is provided in parallel with the above to suppress variation in pixel potential.

However, this auxiliary capacitance line is often made of a light-impermeable material which is the same material as the scanning line material or the like in order to prevent an increase in the number of manufacturing steps, and therefore, the area where the auxiliary capacitance line is arranged. Becomes opaque and reduces the aperture ratio.

From the above, the variation of the pixel potential is suppressed by forming an auxiliary capacitance between the pixel electrode and the scanning line adjacent to the pixel electrode and devising the scanning pulse applied to the scanning line. However, it is known to maintain a high aperture ratio (Japanese Patent Publication No. 1-34392, US Pat. No. 46212).
No. 60).

However, in such a structure, an interlayer short circuit is apt to occur in the overlapping portion of the scanning line and the pixel electrode, resulting in a reduction in manufacturing yield.

Further, according to this structure, by devising the scanning line shape so as to overlap the peripheral region of the pixel electrode, the pixel region contributing to the display of the pixel electrode can be well defined, but The auxiliary capacitance (Cs) formed by the overlapping portion of the electrode and the scanning line increases beyond the capacitance value required to suppress the fluctuation of the pixel potential. Therefore, the scanning pulse is delayed, writing to the pixel electrode is insufficient, and the contrast ratio is lowered. It is possible to increase the scanning line width in order to suppress the delay of the scanning pulse, but in that case, the aperture ratio is lowered.

The present invention has been made in view of the above technical problems, and relates to an array substrate for a display device in which a scanning line and a pixel electrode are overlapped to form a storage capacitor, which is excellent in manufacturing yield and further. It is an object of the present invention to provide an array substrate for a display device that achieves a high aperture ratio and a manufacturing method thereof.

Another object of the present invention is to provide an array substrate for a display device and a method of manufacturing the same, which can secure high productivity with a small number of masks and without lowering the manufacturing yield.

[0012] On the other hand, an array substrate for a display device and a method of manufacturing the same have been proposed which ensure high productivity with a small number of masks without lowering the manufacturing yield (JP-A-6-202153 and JP-A-6-202153). -208137, U.S. Pat. No. 5,483,082). This array substrate has the following structure.

The gate terminal portion includes a gate terminal lower electrode,
From the gate terminal upper electrode, which is laminated on the gate terminal lower electrode through the contact hole opened in the insulating film and the passivation film which are common to the gate insulating film, and which is made of the transparent electrode of the same material as the pixel electrode. Composed,
The auxiliary capacitance section is composed of a Cs electrode, a dielectric film made of an insulating film and an i-type semiconductor layer on the Cs electrode, and a counter electrode made of an n + type semiconductor layer and a metal layer on the Cs electrode.

However, the array substrate having this structure has a problem that it is difficult to apply the same potential to the auxiliary capacitance portion when applying the voltage.

In view of the above problems, the present invention provides an array substrate having a structure in which the auxiliary capacitors are easily applied at the same potential.

[0016]

According to a first aspect of the present invention, there is provided a scanning line arranged on a substrate, a first insulating film arranged on the scanning line, a semiconductor film arranged on the first insulating film, A thin film transistor including a source electrode and a drain electrode electrically connected to a semiconductor film, a signal line derived from the drain electrode and substantially orthogonal to the scanning line, and a pixel electrode electrically connected to the source electrode. And a pixel electrode electrically connected to the source electrode through at least a second insulating film disposed on the signal line, and the pixel electrode is adjacent to the scanning electrode. In the array substrate for a display device, the line and the line overlap with each other through the first and second insulating films.

According to a fourth aspect of the present invention, the scanning line arranged on the substrate, the first insulating film arranged on the scanning line, the semiconductor film arranged on the first insulating film, and the channel arranged on the semiconductor film. A thin film transistor including a protective film and a source electrode and a drain electrode electrically connected to the semiconductor film, a signal line derived from the drain electrode and substantially orthogonal to the scanning line, and electrically connected to the source electrode A method of manufacturing an array substrate for a display device including a pixel electrode, the step of forming a first wiring layer including the scanning line on the substrate, and the step of depositing the first insulating film and the semiconductor film. A metal thin film is deposited, and at least the metal thin film and the semiconductor film are patterned based on the same mask to form a second wiring layer including the signal line, the source electrode and the drain electrode. A step of depositing a second insulating film and forming a first contact hole in the second insulating film corresponding to the source electrode, and electrically connecting to the source electrode through the contact hole And a step of forming the pixel electrode that overlaps the scanning line with the first and second insulating films interposed therebetween, in the method for manufacturing the array substrate for a display device.

According to the display device array substrate and the method of manufacturing the same, the pixel electrodes are arranged at least with respect to the scanning lines and the signal lines through the insulating film. It can be placed sufficiently close to each wiring, and thereby a high aperture ratio can be achieved. Further, for example, since the pixel electrode is arranged so as to overlap with the extension region from the adjacent scanning line via at least two insulating films of the first and second insulating films, the overlapping region with the pixel electrode is increased. However, the yield will not decrease due to poor insulation.

Further, with the above-mentioned structure, even if the overlapping area of the pixel electrode and the scanning line is increased, it is possible to prevent the auxiliary capacitance from being significantly increased. That is, when forming the auxiliary capacitance by overlapping the scanning line and the pixel electrode,
If the auxiliary capacitance is sufficiently large, the capacitance added to the scanning line increases, which causes an increase in power consumption, a writing shortage due to the delay of the scanning pulse, and a deterioration in display characteristics such as a decrease in contrast ratio. However, according to the present invention, even if the periphery of the pixel electrode and the extending region of the scanning line are configured to overlap with each other in order to determine the opening portion of the pixel electrode, the pixel electrode extends from the adjacent scanning line. Since it overlaps with the existing region via at least the two insulating films of the first and second insulating films, the auxiliary capacitance is not significantly increased.

According to a ninth aspect of the invention, the scanning line arranged on the substrate, the first insulating film arranged on the scanning line, the semiconductor film arranged on the first insulating film, and the semiconductor film electrically Display device including a thin film transistor including a source electrode and a drain electrode connected to each other, a signal line derived from the drain electrode and substantially orthogonal to the scanning line, and a pixel electrode electrically connected to the source electrode In the method of manufacturing an array substrate for use in manufacturing, a first step of forming the scanning line, a second step of depositing the first insulating film and the semiconductor film, a metal thin film is deposited, and the metal thin film and the semiconductor film are the same. A third step of patterning based on a mask to form the signal line, the source electrode and the drain electrode;
A fourth step of depositing a second insulating film and forming a first contact hole in the second insulating film corresponding to the source electrode; and electrically connecting to the source electrode through the contact hole, A fifth method of forming the pixel electrode overlapping the scanning line via the first and second insulating films.
And the first insulating film and the semiconductor film at the same time as the second step, at a position other than the thin film transistor and across the pixel electrode and the adjacent scanning line or another scanning line. Depositing the
Simultaneously with the third step, a step of depositing the metal thin film and patterning the metal thin film and the semiconductor film based on the mask to form the light shielding layer; and simultaneously with the fourth step, the second step. An array substrate for a display device, comprising: a step of depositing an insulating film; and a step of forming the pixel electrode so as to cover a part of the one or other scanning lines at the same time as the fifth step. In the manufacturing method.

According to a tenth aspect of the present invention, a plurality of scanning lines which are arranged on the substrate and include a gate electrode region, an auxiliary capacitance line which is substantially parallel to the scanning lines, and a first insulating layer which is arranged on the auxiliary capacitance lines are provided. A film, a semiconductor film disposed at least on the gate electrode region, a thin film transistor including a source electrode and a drain electrode electrically connected to the semiconductor film, a second insulating film disposed on the thin film transistor, A signal line that is substantially orthogonal to the scanning line electrically connected to the drain electrode via the second insulating film, and a pixel electrode electrically connected to the source electrode via the second insulating film. In the provided array substrate for a display device, each of the auxiliary capacitance lines includes a bundled wiring that is wired in a direction substantially orthogonal to each of the auxiliary capacitance lines via the first and second insulating films,
The array substrate for a display device is characterized in that each of the auxiliary capacitance lines and the bundled wiring include an auxiliary capacitance line connecting portion electrically connected through a conductive layer.

According to a fourteenth aspect of the present invention, the scanning line arranged on the substrate and the first insulating film arranged on the scanning line,
A thin film transistor including a semiconductor film disposed on the semiconductor film, a source electrode and a drain electrode electrically connected to the semiconductor film, a signal line derived from the drain electrode and substantially orthogonal to the scanning line, and the source In a display device array substrate including a pixel electrode electrically connected to an electrode, a scanning line lead-out portion that draws out the scanning line is arranged at a scanning line terminal portion located at a peripheral portion of the substrate, and The scanning line lead-out portion has a first conductive layer made of the same material as the scanning line and a second conductive layer made of the same material as the signal line via the first conductive layer and an insulating layer. Then, the first conductive layer and the second conductive layer are electrically connected to each other by a connection layer made of the same material as the pixel electrode.

According to a fifteenth aspect of the present invention, the scanning line arranged on the substrate and the first insulating film arranged on the scanning line,
A thin film transistor including a semiconductor film disposed on the semiconductor film, a source electrode and a drain electrode electrically connected to the semiconductor film, a signal line derived from the drain electrode and substantially orthogonal to the scanning line, and the source In a display device array substrate including a pixel electrode electrically connected to an electrode, a signal line lead-out portion for drawing out the signal line is arranged at a signal line terminal portion located at a peripheral portion on the substrate, The signal line lead-out portion has a first conductive layer made of the same material as the scanning line and a second conductive layer made of the same material as the signal line via the first conductive layer and an insulating layer. Then, the first conductive layer and the second conductive layer are electrically connected to each other by a connection layer made of the same material as the pixel electrode.

According to a sixteenth aspect of the present invention, the scanning line arranged on the substrate, the first insulating film arranged on the scanning line, the semiconductor film arranged on the first insulating film, and electrically connected to the semiconductor film. A thin film transistor including a source electrode and a drain electrode, and a second film disposed on the thin film transistor.
An insulating film, and a signal line that is electrically connected to the drain electrode through the second insulating film and that is substantially orthogonal to the scanning line,
A pixel electrode electrically connected to the source electrode through the second insulating film, a signal line terminal portion electrically connected to the signal line through a signal line lead-out portion, and a scan line for scanning In a display device array substrate including a scanning line terminal portion electrically connected through a line drawing portion, the signal line terminal portion and the scanning line terminal portion are formed of the same material as the scanning line. An array substrate for a display device comprising a first conductive layer and a second conductive layer formed of the same material as the pixel electrode arranged on the first conductive layer.

[0025]

BEST MODE FOR CARRYING OUT THE INVENTION First Embodiment A liquid crystal display device (1) according to a first embodiment of the present invention will be described below with reference to FIGS. 1 to 13.

This liquid crystal display device (1) is a light-transmissive type capable of color display, and as shown in FIG.
An alignment film (1) made of a polyimide resin between the (100) and the counter substrate (200) and subjected to an alignment treatment in directions orthogonal to each other.
Twisted nematic (TN) liquid crystals are held via 41) and (241). Polarizing plates (311) and (313) are attached to the outer surfaces of the array substrate (100) and the opposing substrate (200), respectively.

FIG. 1 is a schematic plan view of the array substrate (100). The lower side of the drawing is located above the screen of the liquid crystal display device (1). The scanning lines are sequentially selected toward.

The array substrate (100) has 480 scanning lines (1) made of Al-Y alloy arranged on the glass substrate (101).
11), and one end of each scanning line (111) is connected to a glass substrate (10).
1) is pulled out to one end side (101a) side, and the oblique wiring part (150)
And is electrically connected to the scanning line pad (152). Here, the scanning line (111) is made of an Al-Y alloy,
-Ta alloy, Mo-W alloy, Al, or an alloy thereof may be used.

The array substrate (100) includes, on the glass substrate (101), 1920 signal lines (110) made of Mo-W alloy which are substantially orthogonal to the scanning lines (111), and each signal line (110) is It is drawn out to the other end side (101b) side of the glass substrate (101) and is electrically connected to the signal line pad (162) via the diagonal wiring portion (160). Here, the signal line (110) is made of a Mo-W alloy, but may be made of a Mo-Ta alloy, Al, or an alloy thereof.

A TFT (112) is arranged near the intersection of the scanning line (111) and the signal line (110). Also,
Pixel electrode made of ITO connected to this TFT (112)
(131) is arranged on the scanning line (111) and the signal line (110) via the interlayer insulating film (127). This interlayer insulating film (12
As 7), it can be composed of an inorganic insulating film such as a silicon nitride film or a silicon oxide film, or an organic resin film such as an acrylic resin, but it can be composed of a multilayer film of these inorganic insulating film and organic resin film. , Surface smoothness and interlayer insulation are further improved.

(Structure of TFT Area) The structure of the TFT (112) area will be described.

Each scanning line (111) has a pixel electrode (13) adjacent to it.
The extended region (113) is extended in a thin line shape so as to overlap with the side edges (131a) and (131b) along the signal line (110) in (1). The pixel electrode (131) and the scan line (11) corresponding to the pixel electrode (131)
1), the overlapping region (OS) with the extending region (113) from the scanning line (111) in the previous stage is, as shown in FIG. 6, a first gate insulating film (115) and a second gate insulating film. (117) and interlayer insulating film
Overlapping each other via (127), this overlapping area (OS)
The auxiliary capacitance (Cs) is constituted by Further, in this embodiment, the pixel electrode (131) and the scanning line (111) of the previous stage are mutually connected via the first gate insulating film (115), the second gate insulating film (117) and the interlayer insulating film (127). They are overlapped, and auxiliary capacitance (Cs) is also configured in this overlap region.

A counter substrate facing the array substrate (100)
(200) is placed on the glass substrate (201) and TFT (12
1) Region, signal line (110), scan line (111) and pixel electrode (13
1) Matrix-like resinous light-shielding film that shields the gap between and
Including (211). In addition, red (R), green (G) and blue (B) color filters (221) are arranged in regions corresponding to the pixel electrodes (131), respectively, and a counter electrode (transparent electrode material) made of a transparent electrode material 231) are arranged and configured.

As described above, according to the array substrate (100) of the liquid crystal display device (1), the signal line (110) and the scanning line (11)
1) between the pixel electrode (131) and the interlayer insulating film (127),
Alternatively, since the first and second gate insulating films (115) and (117) and the interlayer insulating film (127) are respectively arranged, the pixel electrode (131) is sufficient for each wiring (110) and (111). Can be arranged close to or overlapping with each other, and thereby a high aperture ratio can be realized.

Further, according to this embodiment, the auxiliary capacitance (C
s) is formed between the pixel electrode (131) and the extension region (113) extending from the pixel electrode (131) and the scanning line (111) adjacent to the pixel electrode (131). It is not necessary to dispose, and the aperture ratio can be further increased. Particularly, in this embodiment, the TFT (112) is connected from the scanning line (111) to the signal line (110).
The pixel electrode (131) can be overlapped with the scanning line (111) itself in the preceding stage because the region led out along with is configured as a gate electrode. As a result, a sufficient auxiliary capacitance (Cs) is secured and a high aperture ratio is achieved at the same time.

Three types of insulating films (115), (1) are provided between the pixel electrode (131) and the scanning line (111) and the extension region (113).
Since 17) and (127) are respectively laminated, the occurrence of interlayer short circuit and the like due to the structure of this embodiment is significantly reduced.

By the way, in this embodiment, the pixel area is
The scanning line (111) and its extension area (113) on the array substrate (100) instead of the light shielding film (211) arranged on the counter substrate (200).
Is defined by Therefore, regardless of the alignment accuracy between the array substrate (100) and the counter substrate (200), the first mask pattern for patterning the scanning line (111) and the pixel electrode (131).
Since it is determined only by the alignment accuracy with the fifth mask pattern for patterning, the light-shielding film (211) in consideration of the misalignment between the array substrate (100) and the counter substrate (200).
Since it is not necessary to provide a margin for the width, it is possible to realize a higher aperture ratio.

Further, in order to define the pixel area, the scan line
The extension region (113) of the (111) is connected to the signal line (11) of the pixel electrode (131).
Even if the edges (131a) (131b) along (0) are sufficiently extended, according to this embodiment, the pixel electrode (131) and the scan line (11
The first gate insulating film (115) is formed between the extended region (113) of 1).
In addition to the second gate insulating film (117), an interlayer insulating film (127)
Are arranged, it is possible to suppress a large increase in the auxiliary capacitance (Cs) without impairing the productivity.

Further, as shown in FIG. 5, the contours of the signal line (110) and the contours of the low resistance semiconductor film (124a) and the semiconductor film (120) coincide with each other. More specifically, at the intersection of the signal line (110) and the scanning line (111), in addition to the first and second gate insulating films (115) and (117), a low-resistance semiconductor film (124a) and a semiconductor are required. Membranes (120) are laminated. Therefore, even if mask misalignment occurs during each patterning, the signal line (110) and the scanning line
Since there is no capacitance variation with (111), variations in scanning line capacitance or signal line capacitance between products can be reduced. Also,
Static electricity at the intersection of the signal line (110) and the scanning line (111), dust in the process, or each insulating film (115), (11
Interlayer short circuit caused by 7) pinhole is also suppressed,
This ensures a high manufacturing yield.

Further, as shown in FIG. 6, the signal line (110)
Since the contour of the low resistance semiconductor film (124a) and the contour of the semiconductor film (120) are the same as the contour of the pattern, unlike the conventional patterning in a separate process, even if a mask shift occurs in each pattern, the signal It is possible to sufficiently suppress the capacitance fluctuation that occurs between the line (110) and the extension region (113) of the scanning line (111).

Further, the signal line (110) and the extending region (113) of the scanning line (111) are overlapped with each other, that is, the extending region (113) arranged adjacent to each other via the signal line (111) in FIG. ) To the signal line (11
1) Even in the structure to be connected below, each insulating film (11) is provided between the signal line (110) and the extension region (113) of the scanning line (111).
In addition to 5) and (117), the semiconductor film (120) is always placed, so static electricity, dust in the process, or each insulating film (1
Interlayer shorts caused by pinholes (15) and (117) can also be suppressed, and a high manufacturing yield can be secured. Then, in this way, the pixel electrode (131) adjacent to the signal line (111)
The signal line (111) is formed by arranging the extension region (113) below.
The capacitive coupling between the pixel electrode (131) and the pixel electrode (131) is shielded by the extension region (113), and the potential of the pixel electrode (131) is changed to the signal line (1
The effect of the potential of 11) can be reduced. Moreover,
The contour lines of the semiconductor film (120) and the low-resistance semiconductor film (124a) arranged between the signal line (111) and the insulating films (115) and (117) match the contour line of the signal line (111). ing. For these reasons, the signal line (111) and the pixel electrode (131) can be arranged sufficiently close to each other, thereby achieving a higher aperture ratio.

(Structure near the outer periphery of the scanning line)
The structure near the outer peripheral portion of 1) will be described with reference to FIGS. 1 and 3.

The scanning line (111) made of an Al-Y alloy is drawn out to one side (101a) side of the glass substrate (101) and guided to the diagonal wiring part (150) and the scanning line pad (152). The part (111a) is formed.

In the diagonal wiring section (150), the scanning line (11
On the lower wiring portion (111a) extending from (1), two layers of insulating films (115) and (117) are laminated. On the two insulating films (115) and (117), Mo-W, which is the same material as the semiconductor film (119), the low-resistance semiconductor film (123) and the signal line (110) in the same step, is used. Upper layer wiring section made of alloy film (125a)
Are laminated, and an interlayer insulating film (127) is arranged on the upper wiring portion (125a).

At the base of the diagonal wiring part (150), a pair of the first contact hole (153) and the second contact hole (153) are formed.
The contact holes (154) are arranged close to each other along the wiring direction, and are extended from the scanning lines (111) by a scanning line connection layer (131) made of the same material as ITO in the same process as the pixel electrodes (131). The existing lower wiring portion (111a) and upper wiring portion (125a) are electrically connected to each other through the first contact hole (153) and the second contact hole (154). The second contact hole (154) is used for the lower wiring part.
A two-layer insulating film (1
15), (117), semiconductor film (119), low resistance semiconductor film (12
3) and the upper wiring portion (125a), and the first contact hole (153) penetrates the interlayer insulating film (127) so as to expose a part of the main surface of the upper wiring portion (125a). It is an opening to do.

Further, in the scanning line pad (152), the pair of first contact hole (155) and second contact hole (156) are arranged close to each other in the wiring direction, and the pixel electrode ( Scanning line by the scanning line connection layer (131) made of the same material as ITO
The lower wiring portion (111a) of the (111) and the upper wiring portion (125a) of the first contact hole (155) and the second contact hole (1
56) electrically connected via. The second contact hole (156) is the second contact hole described above.
Similar to (154), the two layers of insulating films (115) and (117) and the semiconductor film (1) are formed so as to expose a part of the main surface of the lower wiring section (111a).
19), low-resistance semiconductor film (123) and upper wiring (125a)
The first contact hole (15
Reference numeral 5) is an opening penetrating the interlayer insulating film 127 so as to expose a part of the main surface of the upper wiring portion 125a similarly to the above-mentioned first contact hole 153.

As a result, the oblique wiring portion (1) of the scanning line (111) is
50) are signal lines (11) which are patterned in separate steps.
0) and an upper wiring part (125a) made of a Mo-W alloy film and made of the same material as the above (0) and a lower wiring part (111a) extending from the scanning line (111) made of an Al-Y alloy film. And the scanning line pad (152) is electrically connected to the base of the oblique wiring part (150).

Therefore, in the diagonal wiring portion (150), even if one of the upper layer wiring portion (125a) and the lower layer wiring portion (111a) is disconnected, the other is connected, and therefore the diagonal wiring portion (15)
Disconnection failure at 0) is greatly reduced.

Further, since the diagonal wiring portion (150) includes the lower wiring portion (111a) made of an Al--Y alloy film which is a low resistance material mainly containing Al, the resistance can be sufficiently reduced.

In this embodiment, the region of the second contact hole (156), that is, the lower wiring portion (111a) and the scanning line connecting layer is formed.
The stacked region with (131) mainly functions as a connection region for the scanning line pad (152).

(Structure near the outer periphery of the signal line) Signal line (11
The structure near the outer peripheral portion of (0) will be described with reference to FIGS. 1 and 4.

A lower wiring portion (111b) made of an Al--Y alloy film made of the same material as that of the scanning line (111) corresponds to each signal line (110) on one side () of the glass substrate (101). 101b)
Side signal line (110) diagonal wiring section (160) and signal line pad
It is located at (162).

In the diagonal wiring portion (160), the lower wiring portion
Two layers of insulating films (115) and (117) are arranged on the (111b). In addition, a semiconductor film (119), a low resistance semiconductor film (123), and a Mo-W alloy film extending from the signal line (110) are formed on the two-layer insulating films (115) and (117). The upper layer wiring part (125b) (signal line (110)) is laminated, and the interlayer insulating film (127) is arranged on the upper layer wiring part (125b).

At the base of the oblique wiring part (160), a pair of first contact hole (163) and second pair of contact holes (163) are formed.
Contact holes (164) are arranged close to each other along the wiring direction, and extend from the signal line (110) by a signal line connection layer (131) made of ITO which is the same material as the pixel electrode (131) in the same step. The existing upper wiring portion (125b) and lower wiring portion (111b) are electrically connected. The second contact hole (164) has two layers of insulating films (115) and (117), a semiconductor film (119), a low resistance semiconductor so as to expose a part of the main surface of the lower layer wiring part (111b). The first contact hole (163) is an opening penetrating the film (123) and the upper wiring part (125b), and the interlayer insulating film (127) is formed so as to expose a part of the main surface of the upper wiring part (125b). Is an opening passing through.

In the signal line pad (162), the pair of first contact hole (165) and second contact hole (166) are arranged close to each other in the wiring direction, and the pixel electrode (131) The same material in the same process as I
Signal line (110) by signal line connection layer (131) made of TO
The upper wiring portion (125b) extending from the lower wiring portion (111b) is electrically connected. The second contact hole (166), like the above-mentioned second contact hole (164), has two layers of insulating films (115), so as to expose a part of the main surface of the lower wiring portion (111b). (117), the semiconductor film (119), the low-resistance semiconductor film (123), and the upper wiring portion (125b) through the opening, the first contact hole (165) and the second contact hole (163) described above. Similarly, upper wiring section (125b)
Is an opening penetrating the interlayer insulating film (127) so as to expose a part of the main surface of the.

As a result, in the oblique wiring portion (160), the upper wiring portion (125b) extending from the signal line (110) made of the Mo--W alloy film and the scanning line (111) are formed by the same material in the same step. And the lower wiring portion (111b) made of the Al-Y alloy film, which is the
And the signal line pad (162) are electrically connected.

Therefore, in the diagonal wiring portion (160), M
Upper wiring part (125b) made of an o-W alloy film or Al-
Even if one of the lower layer wiring parts (111b) made of a Y alloy film is broken, the other is connected, and therefore, the disconnection failure in the diagonal wiring part (160) is reduced.

Further, since the diagonal wiring portion (160) includes the lower wiring portion (111b) made of an Al-Y alloy film which is a low resistance material mainly containing Al, the resistance can be sufficiently lowered.

In this embodiment, the region of the second contact hole (166), that is, the lower wiring portion (111b) and the scanning line connecting layer is formed.
The stacked region with (131) mainly functions as a connection region for the signal line pad (162).

According to the above structure, the bumps of the driving IC, the electrodes of the FPC (flexible printed circuit) and the TCP (tape carrier package), etc. are used as the signal line pad (162) and the scanning line pad (152). When electrically connecting through a connection layer such as ACF (anisotropic conductive film), the signal line pad (162) and the scanning line pad (152) have substantially the same configuration, and therefore the signal line pad Even if the connection conditions of (162) and the scanning line pad (152) are the same, the heat, pressure, etc. applied to the connection layer can be made substantially the same, which enables manufacture under the same conditions. That is, in this embodiment, the connection region of the scanning line pad (152) is mainly formed by the lower wiring portion (111a) made of an Al-Y alloy film derived from the scanning line (111).
And a pixel electrode (131) and a scanning line connection layer (131) made of the same material as ITO, and a connection area of the signal line connection pad (162) is mainly formed simultaneously with the scanning line (111). The lower wiring portion (1) made of the Al-Y alloy film to be formed
11b) and a signal line connection layer (131) made of ITO, which is the same material as the pixel electrode (131), and has a substantially identical structure.

(Manufacturing Process of Array Substrate) Next, the manufacturing process of the array substrate (100) will be described in detail with reference to FIGS. 7 to 13.

(1) First Step As shown in FIG. 7, an Al—Y alloy film and a Mo film are sputtered on a glass substrate (101) to a thickness of 200 nm, respectively.
Deposited continuously with a thickness of 30 nm, exposed using a first mask pattern, developed and patterned (first patterning).

As a result, 480 is formed on the glass substrate (101).
Make one scanning line (111) and one side (101a)
On the side, the lower wiring portion (111a) forming the diagonal wiring portion (150) of the scanning line (111) and the scanning line pad (152), one end side (101
In b), the diagonal wiring portion (160) of the signal line (110) and the lower layer wiring portion (111b) forming the signal line pad (162) are simultaneously produced.

Further, in the TFT region, a gate electrode is formed integrally with the scanning line (111) and led out in a direction orthogonal to the scanning line (111). Further, an extension region (113) for forming the auxiliary capacitance (Cs), which is derived in a direction orthogonal to the scanning line (111) at the time of patterning the scanning line (111), is also prepared at the same time (FIG. 1). reference).

(2) Second Step After the first step, as shown in FIG. 8, after the first gate insulating film (115) made of a silicon oxide film having a thickness of 150 nm is deposited by the plasma CVD method, a further 150 nm thickness is deposited. Second gate insulating film (117) consisting of a silicon nitride film of 50 nm
Thick a-Si: H semiconductor coating (119) and 200
channel protective film (12 nm thick silicon nitride film)
1) is deposited without continuously exposing it to the atmosphere.

(3) Third Step After the second step, as shown in FIG. 9, the channel protective film (121) is self-aligned with the scanning line (111) by the backside exposure technique using the scanning line (111) as a mask. ), And then T
Exposure, development, and patterning (second patterning) using a second mask pattern so as to correspond to the FT region
Then, an island-shaped channel protection film (122) is produced.

(4) Fourth Step After the third step, as shown in FIG. 10, a semiconductor film (119) exposed so as to obtain a good ohmic contact.
The surface is treated with a hydrofluoric acid (HF) -based solution, and a 30 nm-thick n + a-S
A low resistance semiconductor film (123) made of i: H is deposited, and a 300 nm thick Mo-W alloy film (125) is further deposited by sputtering.

(5) Fifth Step After the fourth step, as shown in FIG. 11, exposure and development are performed using a third mask pattern to form a Mo--W alloy film (125) and a low resistance semiconductor film (123). ) And the semiconductor film (119) are collectively formed by controlling the etching selection ratio of the first gate insulating film (115) or the second gate insulating film (117) and the channel protective film (122) made of a silicon nitride film. Patterning by plasma etching (third patterning).

As a result, in the TFT region, the resistance semiconductor film (124a) and the source electrode (126b) are integrally formed,
The drain electrode (126a) is formed integrally with the low resistance semiconductor film (124b) and the signal line (110).

The scanning line pad (152) and the oblique wiring portion (150)
At the base of Mo- along the lower wiring portion (111a).
Patterning of W alloy film (125) and upper wiring part (125a)
And the low-resistance semiconductor film (123) and the semiconductor film (119) are collectively patterned along the upper wiring portion (125a). At the same time, openings (154a), (156a) penetrating the upper wiring portion (125a) corresponding to the above-mentioned second contact holes (154), (156), the low resistance semiconductor film (123) and the semiconductor film (119). ) Is produced.

Similarly, at the bases of the signal line pad (162) and the diagonal wiring portion (160), the Mo--W alloy film (125) is patterned along the lower wiring portion (111b) to form the signal line (11).
0), and a low-resistance semiconductor film (123) is formed along the upper wiring portion (125b).
Then, the semiconductor film (119) is collectively patterned. At the same time, the second contact holes (164), (16)
An opening (164) penetrating the upper wiring portion (125b), the low resistance semiconductor film (123) and the semiconductor film (119) in a region corresponding to (6).
a) and (166a) are prepared.

Although the Mo—W alloy film (125), the low resistance semiconductor film (123) and the semiconductor film (119) are patterned by dry etching here, wet etching may be used.

(6) Sixth Step After the fifth step, an interlayer insulating film 127 made of a silicon nitride film having a thickness of 200 nm is deposited on the fifth step.

Then, as shown in FIG. 12, exposure and development are performed using a fourth mask pattern to remove a part of the interlayer insulating film (127) in a region corresponding to the source electrode (126b) and dry etching is performed. To form a contact hole (129a).

Scan line pad (152) and diagonal wiring part (150)
At the base of the, the first corresponding to the openings (154a), (156a)
And the interlayer insulating film (127) together with the second gate insulating film (117) to form the second contact holes (154) and (156) (fourth patterning), and at the same time, the second contact hole. The interlayer insulating film (127) in the vicinity of (154) and (156) is removed to form first contact holes (153) and (155) which form a pair with the second contact holes (154) and (156).

At the same time, at the bases of the signal line pad (162) and the diagonal wiring portion (160), the interlayer insulating film is formed together with the first and second gate insulating films (117) corresponding to the openings (164a), (166a).
The second contact hole (164),
At the same time that the (166) is formed, the second contact hole (16
The interlayer insulating film (127) in the vicinity of (4) and (166) is removed to form first contact holes (163) and (165) respectively paired with the second contact holes (164) and (166).

(7) Seventh Step After the sixth step, as shown in FIG.
An m-thick ITO film is deposited by sputtering, and is exposed, developed, and patterned by dry etching using a fifth mask pattern (fifth patterning) to produce a pixel electrode (131). The patterning of the ITO film may be wet etching instead of dry etching.

Scan line pad (152) and diagonal wiring part (150)
At the base of the, the first contact holes (153), (155)
And the second contact holes (154) and (156) are electrically connected to each other to form a scanning line connection layer (131), and the scanning line (111) and the scanning line pad (152) are thereby formed. , The lower wiring portion (111a) and the upper wiring portion (125a) are electrically connected by the diagonal wiring portion (150) having a two-layer structure.

Signal line pad (162) and diagonal wiring part (160)
Also at the base of the first contact hole (163), (165)
A signal line connection layer (131) for electrically connecting the second contact holes (164) and the second contact holes (166) to each other is formed at the same time, and thereby the signal line (110) and the signal line connection pad (162) are formed.
Are electrically connected to each other by a diagonal wiring portion (160) having a two-layer structure of a lower wiring portion (111b) and an upper wiring portion (125b).

(Effects of the First Embodiment) As described above, according to the array substrate of this embodiment, the array substrate can be manufactured by using the five basic masks. That is,
The pixel electrode is arranged in the uppermost layer, and along with this, the semiconductor film and the like are collectively patterned based on the same mask pattern together with the signal line, the source, and the drain electrode, and
By simultaneously making a contact hole for connecting the source electrode and the pixel electrode and making a contact hole for exposing the connection end of the signal line or the scanning line, the productivity can be improved with a small number of masks. It does not lower the manufacturing yield.

Further, in each diagonal wiring portion of the signal line and the scanning line, there are provided an upper wiring portion made of a Mo—W alloy film forming a signal line and a lower wiring portion made of an Al—Y alloy film forming a scanning line. It is constituted by layers and electrically connects the base of each diagonal wiring portion and each pad. Therefore, in the diagonal wiring portion, even if one of the upper layer wiring portion and the lower layer wiring portion is broken, since the other is connected, the diagonal wiring portion is not broken.

Furthermore, since the diagonal wiring portion includes at least a wiring layer composed mainly of Al and made of a low resistance material, the resistance can be sufficiently lowered.

Further, since the signal line pads and the scanning line pads for connecting the bumps of the driving IC and the electrodes such as TCP have substantially the same structure, it is possible to connect them under the same conditions.

(Other Modifications) In this embodiment, the case where the semiconductor film is made of a-Si: H has been described, but it goes without saying that it may be a polycrystalline silicon film or the like. Further, the drive circuit portion may be integrally formed in the peripheral region.

Further, when the pixel electrodes are arranged so as to partially overlap with each other on the signal lines or the scanning lines, the shield electrodes are arranged at least between the pixel electrodes and the signal lines with a metal film or the like via an insulating layer. Then, the pixel electrode can reduce the influence of the potential from the signal line.

(Modification Example of Structure near Peripheral Area of Signal Line and Scan Line) As shown in FIG. 14, a modification example of structure near the peripheral area of the signal line (110) will be described.

The lower wiring portion (111b) made of an Al—Y alloy film made of the same material in the same process as the scanning line (111) corresponds to each signal line (110) at one end side () of the glass substrate (101). 101b) side signal line (110) diagonal wiring section (160) and signal line pad (1
62).

In the diagonal wiring portion (160), the lower wiring portion
Two layers of insulating films (115) and (117) are arranged on the (111b). In addition, a semiconductor film (119), a low resistance semiconductor film (123), and a Mo-W alloy film extending from the signal line (110) are formed on the two-layer insulating films (115) and (117). An upper layer wiring part (125b) (signal line (110)) is laminated, and an interlayer insulating film (127) is arranged on the upper layer wiring part (125b).

The base of the diagonal wiring portion (160) is similar to that of the above-described embodiment, and the signal line pad (1
62), a pair of the first contact hole 175 and the second contact hole 176 are respectively arranged, and the signal line connection layer 131 made of ITO which is the same material as the pixel electrode 131 in the same step. ) Electrically connects the upper wiring portion (125b) and the lower wiring portion (111b) extending from the signal line (110). The first contact hole (175)
Is a two-layer insulating film (115), (117), a semiconductor film (119), a low resistance semiconductor film (123) and an upper layer wiring part (so as to expose a part of the main surface of the lower wiring part (111b). The second contact hole (176) is an opening penetrating through the interlayer insulating film (1) so as to expose a part of the main surface of the upper wiring portion (125b).
It is an opening that passes through 27).

As described above, in this modified example, the signal line pad (162) is different from the above-described embodiment mainly in the lower wiring portion.
(111b) two-layer insulating films (115) and (117), a semiconductor film (119) disposed on the two-layer insulating films (115) and (117), a low-resistance semiconductor film (123), M extending from the signal line (110)
Upper wiring part (125b) made of an o-W alloy film (signal line (110)
) And the signal line connection layer (131) made of ITO that constitutes the pixel electrode (131), and the difference is that it is the same as the above-described embodiment.

The structure near the outer periphery of the scanning line (111) is preferably the same as that on the signal line side.

[0092] The second embodiment below, a liquid crystal display device of light transmission type according to a second embodiment of the present invention (1) will be described with reference to FIG. 26 from FIG. 15.

As shown in FIG. 16, the liquid crystal display device (1) is made of a polyimide resin between the array substrate (100) and the counter substrate (200), and has an alignment film in which alignment treatments are performed in directions orthogonal to each other. Twisted nematic liquid crystal is held through (141) and (241). In addition, polarizing plates (311) (313) are provided on the outer surfaces of the array substrate (100) and the counter substrate (200), respectively.
Is pasted and configured.

FIG. 15 shows the array substrate (100) of this embodiment.
Fig. 2 is a schematic plan view showing that the lower side of the figure is located on the upper side of the screen of the liquid crystal display device (1), and the scanning lines are sequentially selected from the lower side to the upper side of the figure. Is.

The array substrate (100) has 480 scanning lines (1) made of Al-Y alloy arranged on the glass substrate (101).
11), and one end of each scanning line (111) is connected to a glass substrate (10).
1) is pulled out to one end side (101a) side, and the oblique wiring part (150)
Then, the scanning line pad (152) is formed. The structure of the oblique wiring part (150) and the scanning line pad (152) is the same as that of the first embodiment, and the manufacturing process can be similarly manufactured.

The array substrate (100) includes, on the glass substrate (101), 1920 signal lines (110) made of Mo-W alloy which are substantially orthogonal to the scanning lines (111), and each signal line (110) is One end of the glass substrate (101) is drawn out to the other end side (101b) side, and the signal line pad (162) is formed through the diagonal wiring portion (160). The structure of the diagonal wiring portion (160) and the signal line pad (162) is the same as that of the first embodiment.
Further, the manufacturing process can be similarly performed.

A TFT (112) is arranged at the intersection of the scanning line (111) and the signal line (110). Further, the pixel electrode (131) of the TFT (112) is arranged on the scanning line (111) and the signal line (110) via the interlayer insulating film (127). The interlayer insulating film (127) can be composed of an inorganic insulating film such as a silicon nitride film, but by being composed of a multilayer film of these inorganic insulating film and organic resin film,
Surface smoothness and interlayer insulation are further improved.

(Structure of TFT Area) The structure of the TFT (112) area will be described.

Each scanning line (111) has an adjacent pixel electrode (13
The extended region (113) is extended in a thin line shape so as to overlap with the side edges (131a) and (131b) along the signal line (110) in (1). The overlap region (O) between the extension region (113) and the pixel electrode (131)
S) is, as shown in FIG. 4, a first gate insulating film (115),
A storage capacitor (Cs) is formed by being overlapped with each other through the second gate insulating film (117) and the interlayer insulating film (127).

Between the position other than the TFT region (121) and the position of the upper end side along the scanning line (111) of the pixel electrode (131) and the position across the scanning line (111), a planar rectangular shape is formed. A light blocking layer (170) is provided. This light shielding layer (170) is
It is made of the same material as the signal line (110).

Counter substrate facing this array substrate (100)
(200) is placed on the glass substrate (201) and TFT (12
1) Region, signal line (110), scan line (111) and pixel electrode (13
1) Matrix-like resinous light-shielding film that shields the gap between and
Including (211). In addition, red (R), green (G) and blue (B) color filters (221) are arranged in regions corresponding to the pixel electrodes (131), respectively, and a counter electrode (transparent electrode material) made of a transparent electrode material 231) are arranged and configured.

As described above, the liquid crystal display device of this embodiment
According to the array substrate (100) of (1), between the signal line (110) and the scanning line (111) and the pixel electrode (131), the interlayer insulating film (1
27) or the first and second gate insulating films (115), (117)
And the interlayer insulating film (127) are respectively arranged,
The pixel electrode (131) can be arranged sufficiently close to or superposed on the wirings (110) and (111), whereby a high aperture ratio can be realized.

Moreover, the auxiliary capacitance (Cs) is
1) and the extended region (113) extending from the scan line (111) adjacent to the pixel electrode (131),
It is not necessary to dispose an auxiliary capacitance line or the like separately, and it is possible to further increase the aperture ratio. And the pixel electrode (131) and the extension area
Three types of insulating films (115), (117), (127) are provided between (113) and
Since the arrangement is provided, the occurrence of interlayer short circuit and the like due to the structure of the present embodiment is significantly reduced.

By the way, in this embodiment, the pixel area is
It is defined by the extension region (113) on the array substrate (100) rather than the light blocking film (211) disposed on the counter substrate (200).
In addition, the light shielding layer (170) is the upper edge of the pixel electrode (131),
Since the light shielding layer (170) is provided between the pixel electrode (131) and the scanning line (111) corresponding to the pixel electrode (131), the light shielding layer (170) also serves to define the upper end side of the pixel region end. Therefore, regardless of the alignment accuracy between the array substrate (100) and the counter substrate (200), the first mask pattern for patterning the scanning line (111) and the fifth mask pattern for patterning the pixel electrode (131) are formed. Since it is determined only by the alignment accuracy,
Since it is not necessary to provide a margin for the width of the light shielding film (211) in consideration of misalignment between the array substrate (100) and the counter substrate (200), it is possible to realize a higher aperture ratio.

Further, in order to define the pixel area, the scan line
The extension region (113) of the (111) is connected to the signal line (11) of the pixel electrode (131).
Even if the edges (131a) (131b) along (0) are sufficiently extended, according to this embodiment, the pixel electrode (131) and the scan line (11
The first gate insulating film (115) is formed between the extended region (113) of 1).
In addition to the second gate insulating film (117), an interlayer insulating film (127)
Are arranged, it is possible to suppress a large increase in the auxiliary capacitance (Cs) without impairing the productivity.

Further, according to this embodiment, as shown in FIG. 17, the contours of the signal line (110) and the contours of the low-resistance semiconductor film (124a) and the semiconductor film (120) coincide with each other. More specifically, at the intersection of the signal line (110) and the scanning line (111), in addition to the first and second gate insulating films (115) and (117), a low-resistance semiconductor film (124a) and a semiconductor are required. Membranes (120) are laminated. Therefore, even if mask misalignment occurs in each patterning, there is no capacitance variation between the signal line (110) and the scanning line (111), which reduces variation in the scanning line capacitance or the signal line capacitance between products. It Also, the signal line (110) and the scanning line (111)
Interlayer shorts due to static electricity at the intersection with, dust during the process, or pinholes in the two-layer insulating films (115) and (117) can be suppressed, and a high manufacturing yield can be secured.

Further, according to this embodiment, as shown in FIG. 18, the contours of the signal line (110) and the contours of the low resistance semiconductor film (124a) and the semiconductor film (120) coincide with each other. At this time, even if a mask shift occurs, it is possible to sufficiently suppress the capacitance fluctuation that occurs between the signal line (110) and the extension region (113) of the scanning line (111).

Further, the signal line (110) and the extension region (113) of the scanning line (111) are superposed, that is, in FIG.
The extension region (113) that is placed adjacent to the signal line (1
11) Even in the structure to be connected below, each insulating film (1) is provided between the signal line (110) and the extension region (113) of the scanning line (111).
Since the semiconductor film (120) is always arranged in addition to (15) and (117), static electricity, dust in the process, or each insulating film (1
Interlayer shorts caused by pinholes (15) and (117) can also be suppressed, and a high manufacturing yield can be secured. Then, in this way, the pixel electrode (131) adjacent to the signal line (111)
Due to the arrangement of the extension area (113) below, the signal line (111)
The capacitive coupling between the pixel electrode (131) and the pixel electrode (131) is shielded by the extension region (113), and the potential of the pixel electrode (131) is changed to the signal line (1
The effect of the potential of 11) can be reduced. Moreover,
The contour lines of the semiconductor film (120) and the low-resistance semiconductor film (124a) arranged between the signal line (111) and the insulating films (115) and (117) coincide with the contour line of the signal line (111). ing. For these reasons, the signal line (111) and the pixel electrode (131) can be arranged sufficiently close to each other, thereby achieving a higher aperture ratio.

(Manufacturing Process of Array Substrate) Next, the manufacturing process of the array substrate (100) will be described in detail with reference to FIGS. 20 to 26.

(1) First Step As shown in FIG. 20, at the position of the AA ′ line cross section, a Mo film is formed on the Al—Y alloy film by sputtering to a thickness of 200 nm on the glass substrate (101), respectively. Deposited to a thickness of 30 nm, exposed using the first mask pattern, developed,
Through patterning (first patterning), 480 scanning lines (111) are produced. The extended region (113) is also formed at the same time when the scanning line (111) is patterned (see FIG. 15).

At the position of the DD ′ line cross section, the scanning line (111) is formed on the glass substrate (101) in the same manner as above.

(2) Second Process After the first process, as shown in FIG. 21, the first gate insulating film made of a silicon oxide film having a thickness of 150 nm is formed by plasma CVD at the position of the AA ′ line cross section. After depositing (115), a second gate insulating film (117) made of a silicon nitride film having a thickness of 150 nm and a-Si: H having a thickness of 50 nm are further formed.
A semiconductor film (119) made of and a channel protective film (121) made of a silicon nitride film having a thickness of 200 nm are continuously formed without exposure to the atmosphere.

Also in the position of the DD ′ line cross section, similarly to the above, the first gate insulating film (115) and the second gate insulating film (1
17) and a channel protective film (121) are prepared.

(3) Third Step After the second step, as shown in FIG. 22, at the position of the AA ′ line cross section, the scanning line (111) is formed by the backside exposure technique using the scanning line (111) as a mask. Patterning the channel protective film (121) in a self-aligned manner, and then exposing and developing using a second mask pattern so as to correspond to the TFT region,
An island-shaped channel protective film (122) is produced through patterning (second patterning).

At the position of the DD ′ line cross section, the channel protective film (121) is removed by patterning.

(4) Fourth Step After the third step, as shown in FIG. 23, at the position of the AA ′ line cross section, the surface of the semiconductor film (119) exposed so that a good ohmic contact can be obtained. Hydrofluoric acid (HF)
After processing with a system solution, a low resistance semiconductor film (123) made of n + a-Si: H having a thickness of 30 nm containing phosphorus as an impurity is deposited by a plasma CVD method, and a M having a thickness of 300 nm is further deposited.
An OW alloy film (125) is deposited by sputtering.

At the position of the DD ′ line cross section, similarly to the above, after the low resistance semiconductor film (123) is deposited, the Mo−
A W alloy film (125) is deposited.

(5) Fifth Step After the fourth step, as shown in FIG. 24, exposure is performed using the third mask pattern at the position of the AA ′ line cross section.
Developed, Mo-W alloy film (125), low resistance semiconductor film (12
3) and the semiconductor film (119) are collectively patterned by plasma etching by controlling the etching selectivity of the second gate insulating film (117) made of a silicon nitride film and the channel protective film (122). Patterning) to form a semiconductor film (120), low resistance semiconductor films (124a), (12
4b), source electrode (126b), signal line (110) and signal line (11
0) and the connection end (110a) (see FIG. 15) and the signal line (11
A drain electrode (126a) integrated with 0) is produced.

Also at the position of the DD ′ line cross section, the semiconductor film (120), the low resistance semiconductor film (124b) and the Mo—W alloy film (125) are patterned in the shape of islands in the same manner as above. . As a result, the position of the Mo-W alloy film (125) forms the light shielding layer (170). In this case, the light shielding layer (170)
However, the scanning line (111) is not entirely covered but is partially covered.

(6) Sixth Step After the fifth step, an interlayer insulating film (127) made of a silicon nitride film having a thickness of 200 nm is deposited, and as shown in FIG.
At the position of the A'line cross section, the contact hole (129a) is formed by exposing and developing using the fourth mask pattern to remove the interlayer insulating film (127) corresponding to the source electrode (126b). Further, the interlayer insulating film (127) corresponding to the connection end (110a) (see FIG. 15) of the signal line (110) is removed to form a contact hole (129c) (fourth patterning).

The interlayer insulating film (127) is formed also at the position of the DD ′ line cross section in the same manner as above.

(7) Seventh Step After the sixth step, as shown in FIG. 26, at the position of the AA ′ line cross section, an ITO film having a thickness of 100 nm is deposited on the ITO film by sputtering, and the fifth step is performed. A pixel electrode (131) is produced through exposure, development, and patterning (fifth patterning) using a mask pattern (see FIG. 15).

At the position of the DD ′ line cross section, the pixel electrode (131) is provided on the interlayer insulating film (127) in the same manner as above. In this case, the light shielding layer (170) is
Straddle the pixel electrode (131).

(Effect of Second Embodiment) As described above, according to the array substrate of this embodiment, the array substrate can be manufactured by using the five masks as the basic structure. That is,
The pixel electrode is arranged in the uppermost layer, and along with this, the semiconductor film and the like are collectively patterned based on the same mask pattern together with the signal line, the source, and the drain electrode, and
By simultaneously making a contact hole for connecting the source electrode and the pixel electrode and making a contact hole for exposing the connection end of the signal line or the scanning line, the productivity can be improved with a small number of masks. It does not lower the manufacturing yield.

Further, in the above manufacturing process, the light shielding layer (170) can be formed at the same time at the position across the pixel electrode (131) and the scanning line (111) corresponding to the pixel electrode (131). In this case, it is not necessary to increase the manufacturing process.

In this embodiment, the light shielding layer (170) is arranged at the position across the scanning line (111) corresponding to the pixel electrode (131) and the pixel electrode (131). Electrode (1
The light shielding layer (170) may be arranged at a position extending over the scanning line (111) in the previous stage or the next stage of the scanning line (111) corresponding to 31).

(Modification Example of Light Shielding Layer) FIG. 27 shows a modification example of the light shielding layer. The difference from the second embodiment is that the light shielding layer (180) includes the pixel electrode (131) and the pixel electrode (131). (13
It is located so as to cover the lower side of the scanning line (111) and the pixel electrode (131) in front of the scanning line (111) corresponding to (1),
The light shield layer (170) is electrically insulated. The light shielding layer (170) and the light shielding layer (180) may be integrated without being insulated.

According to such a structure, the opening of the pixel region can be defined on the array substrate, and thus the high aperture ratio can be realized.

(Other Modifications) In this embodiment, the case where the semiconductor film is made of a-Si: H has been described, but it goes without saying that it may be a polycrystalline silicon film or the like. Further, the drive circuit portion may be integrally formed in the peripheral region.

Further, when the pixel electrodes are arranged so as to partially overlap with each other on the signal lines and the scanning lines, the shield electrodes should be arranged at least between the pixel electrodes and the signal lines with a metal film or the like via an insulating layer. Then, the pixel electrode can reduce the influence of the potential from the signal line.

Third Embodiment Hereinafter, a liquid crystal display device (1) according to a third embodiment of the present invention will be described with reference to FIGS. 28 to 38.

As shown in FIG. 29, the liquid crystal display device (1)
Is a twisted nematic liquid crystal through alignment films (141) and (241) that are made of a polyimide resin between the array substrate (100) and the counter substrate (200) and have been subjected to an alignment treatment in directions orthogonal to each other. A liquid crystal layer (400) consisting of is held. Polarizing plates (311) and (313) are attached to the outer surfaces of the array substrate (100) and the counter substrate (200), respectively.

The array substrate (100) is composed of 480 scanning lines (1) made of Al-Y alloy arranged on the glass substrate (101).
11), an auxiliary capacitance line (113) made of the same material as this scanning line (111) and substantially parallel to the scanning line (111) manufactured in the same process.
A first gate insulating film (115) made of a silicon oxide film arranged on the scanning line (111) and the auxiliary capacitance line (113), and a second gate insulating film made of a silicon nitride film deposited thereon.
(117) inclusive.

The array substrate (100) has 480 scanning lines (1) made of Al-Y alloy arranged on the glass substrate (101).
11), and one end of each scanning line (111) is connected to a glass substrate (10).
1) Pulled out to the side piece (101a) side of one side, diagonal wiring part (150)
Then, the scanning line pad (152) is formed. The structure of the diagonal wiring part (150) and the scanning line pad (152) is as follows.
The structure is the same as that of the first embodiment, and the manufacturing process can be similarly manufactured.

The array substrate (100) includes, on the glass substrate (101), 1920 signal lines (110) made of Mo—W alloy which are substantially orthogonal to the scanning lines (111), and each signal line (110) is One end of the glass substrate (101) is drawn out to the other end side (101b) side, and the signal line pad (162) is formed through the diagonal wiring portion (160). The structure of the diagonal wiring portion (160) and the signal line pad (162) is the same as that of the first embodiment.
Further, the manufacturing process can be similarly performed.

A TFT (112) is arranged at the intersection of the scanning line (111) and the signal line (110). Further, the pixel electrode (131) of the TFT (112) is arranged on the scanning line (111) and the signal line (110) via the interlayer insulating film (127). The interlayer insulating film (127) can be composed of an inorganic insulating film such as a silicon nitride film, but by being composed of a multilayer film of these inorganic insulating film and organic resin film,
Surface smoothness and interlayer insulation are further improved.

A counter substrate facing this array substrate (100)
(200) is placed on the glass substrate (201) and TFT (12
1) Region, signal line (110), scan line (111) and pixel electrode (13
1) Matrix-like resinous light-shielding film that shields the gap between and
Including (211). In addition, red (R), green (G) and blue (B) color filters (221) are arranged in the areas corresponding to the pixel electrodes (131), respectively, and a counter electrode made of a transparent electrode material ( 231) are arranged and configured.

(Structure of TFT Area) The structure of the TFT (112) area will be described.

In the array substrate (100), as shown in FIG. 29, the pixel electrode (131) has a first gate insulating film (115), a second gate insulating film (117) and a scanning line (111). It is also arranged via the interlayer insulating film (127) and also to the signal line (110) via the interlayer insulating film (127). Therefore,
Even if the pixel electrode (131) is arranged sufficiently close to the signal line (110) or the scanning line (111), short-circuit defects do not occur each other.
Enables high definition and high aperture ratio design. That is, the pixel electrode (1
31) may be superposed on the signal line (110) or the scanning line (111).

Moreover, as shown in FIG. 30, the signal line (11
0) outline and low resistance semiconductor film (124a) and semiconductor film (120)
The contours of are the same. More specifically, signal line (110)
The low resistance semiconductor film (124a) and the semiconductor film (120) are always laminated in addition to the first and second gate insulating films (115) and (117) at the intersection of the scanning line (111) and the scanning line (111). . Therefore, even if mask misalignment occurs in each patterning, the step created on the signal line (110) is sufficiently reduced, and there is no capacitance variation between the signal line (110) and the scanning line (111). Variation in scanning line capacitance or signal line capacitance between products is reduced. In addition, static electricity at the intersection of the signal line (110) and the scanning line (111), dust during the process, or each insulating film (115), (1
Interlayer shorts caused by the pinholes 17) and (127) can also be suppressed, and a high manufacturing yield can be secured. The same applies to between the signal line (110) and the auxiliary capacitance line (113).

(Wiring Structure of Auxiliary Capacitance Line) Each auxiliary capacitance line (1
Since it is necessary to uniformly apply the same voltage to each of 13), for example, when applied to the counter electrode, this embodiment adopts the following configuration. About the wiring structure
8 and FIG. 31.

As described above, the auxiliary capacitance line (113) is A
It is made of the same material as the scanning line (111) made of an I-Y alloy, and is arranged substantially parallel to the scanning line (111).

Therefore, as shown in FIG. 28, the auxiliary capacitance line connecting portion (190) is formed so as to be orthogonal to the auxiliary capacitance line (113) at the end of each auxiliary capacitance line (113). The structure of the auxiliary capacitance line connecting portion (190) is shown in FIG.

The structure of the auxiliary capacitance line connecting portion (190) will be described.

Storage capacitance lines (11
3) and the scan line (111), a first gate insulating film (115) made of a silicon oxide film and a second gate insulating film (117) made of a silicon nitride film deposited on the first gate insulating film (115) are stacked. To be done. A semiconductor film (119), a low resistance semiconductor film (123) and a signal line which are substantially orthogonal to the auxiliary capacitance line (113) and the scanning line (111) are formed on the two-layer insulating films (115) and (117). (1
In the same step as 10), bundled wirings (125) made of Mo-W alloy film made of the same material are laminated. Then, the auxiliary capacitance is penetrated through a part of the two-layer insulating films (115) and (117), the semiconductor film (119), the low resistance semiconductor film (123), the bundled wiring (125) and the interlayer insulating film (127). First to expose part of the line (113)
A contact hole (191) is formed. In addition, in the wiring direction of the bundled wiring (125), it is close to the first contact hole (191), part of the interlayer insulating film (127) is removed, and the bundled wiring is formed.
A first contact hole (191) exposing a part of (125) and a second contact hole (192) forming a pair are arranged. The auxiliary capacitance line connection layer (193) made of ITO, which is the same material as the pixel electrode (131) in the same step, is provided with a pair of first electrodes.
Contact hole (191) and second contact hole (192)
And is stacked between the storage capacitor and each storage capacitor line (113)
And the bundled wiring (125) are electrically connected by the auxiliary capacitance line connection layer (193).

The end portion of the auxiliary capacitance line connecting portion (190) is similar to the scanning line pad (152) in the glass substrate (101).
Of the auxiliary capacitance line pad (19a).
4) form. The structure of the auxiliary capacitance line pad (194) may be the same as that of the scanning line pad (152) or the signal line pad (162).

When a voltage is applied to the auxiliary capacitance line pads (194), all the auxiliary capacitance lines (113) can have the same potential. Further, when the auxiliary capacitance line connecting portion (190) is manufactured, it can be performed at the same time as the manufacturing process of the array substrate (100) shown below, and therefore the manufacturing process is not complicated.

In this embodiment, the auxiliary capacitance line connection layer (193) made of ITO is laminated only between the pair of first contact holes (191) and second contact holes (192), but the bundled wiring ( It does not matter even if it is wired along (125). As a result, disconnection defects of the bundled wires (125) are reduced.

(Manufacturing Process of Array Substrate) Next, the manufacturing process of the array substrate (100) will be described in detail with reference to FIGS. 32 to 38.

(1) First Step As shown in FIG. 32, an Al—Y alloy film is deposited on the glass substrate (101) by sputtering, and a Mo film is deposited on the Al—Y alloy film to a thickness of 200 nm and a thickness of 30 nm, respectively. , Exposure using the first mask pattern, development, patterning (first
Patterning) to form 480 scanning lines (111) and 480 auxiliary capacitance lines (113).

(2) Second Step After the first step, as shown in FIG. 33, after depositing a first gate insulating film (115) made of a silicon oxide film having a thickness of 150 nm by a plasma CVD method, a further thickness of 150 nm is formed. Second gate insulating film (117) made of a silicon nitride film of 50n
m-thick a-Si: H semiconductor coatings 119 and 20
A channel protective film made of a 0-nm thick silicon nitride film (1
21) is deposited without continuously exposing it to the atmosphere.

(3) Third Step After the second step, as shown in FIG. 34, the back surface exposure technique using the scanning line (111) as a mask is performed so as to self-align with the scanning line (111) to form a channel protective film ( 121) is patterned, further exposed using a second mask pattern so as to correspond to the TFT region, and developed and patterned (second patterning) to form an island-shaped channel protective film (122).

(4) Fourth Step After the third step, as shown in FIG. 35, the semiconductor film (119) exposed so as to obtain a good ohmic contact.
The surface is treated with a hydrofluoric acid (HF) -based solution, and 30 nm-thick n + a-S containing phosphorus as an impurity by the plasma CVD method.
A low resistance semiconductor film (123) made of i: H is deposited, and a 300 nm thick Mo-W alloy film (125) is further deposited by sputtering.

(5) Fifth Step After the fourth step, as shown in FIG. 36, the Mo--W alloy film (125) and the low resistance semiconductor film (123) are exposed and developed using a third mask pattern. ) And the semiconductor film (119) with the second gate insulating film (117) made of a silicon nitride film and the channel protective film (122) by controlling the etching selection ratio, thereby performing patterning by plasma etching all at once (the third Patterning) to form a semiconductor film (120), low resistance semiconductor films (124a) and (124b), a source electrode (126b), a signal line (1
10) and the connection end (110a) integrated with the signal line (110) (see FIG. 1), and the drain electrode (126a) integrated with the signal line (110).
Is prepared.

At this time, the auxiliary capacitance line connecting portion (19
(0) patterning the bundled wiring (125), and at the same time, the auxiliary capacitance line (191) corresponding to the first contact hole (191) for electrically connecting the auxiliary capacitance line (113) and the bundled wiring (125). 113) A part of the upper bundle wiring 125, the low resistance semiconductor film 123 and the semiconductor film 119 is removed by penetrating to form an opening (not shown).

(6) Sixth Step After the fifth step, an interlayer insulating film (127) made of a silicon nitride film having a thickness of 200 nm is deposited, and as shown in FIG.
Exposure and development using the mask pattern of
The interlayer insulating film (127) corresponding to 26b) is removed to form a contact hole (129a) (fourth patterning).

At the same time, the interlayer insulating film (127) corresponding to the above-mentioned opening is removed to expose a part of the auxiliary capacitance line (113) to form the first contact hole (191) and the first contact hole (191).
A second contact hole (192) is formed by removing a part of the interlayer insulating film (127) so as to expose a part of the bundled wiring (125) in the vicinity of the contact hole (191).

(7) Seventh Step After the sixth step, as shown in FIG.
An m-thick ITO film is deposited by sputtering, and exposure, development, and patterning (fifth patterning) are performed using a fifth mask pattern to form a pixel electrode (131).

At the same time, an auxiliary capacitance line connection layer (193) is formed which connects the auxiliary capacitance line (113) and the bundled wiring (125) through the first contact hole (191) and the second contact hole (192). .

(Effect of Third Embodiment) As described above, according to the array substrate of this embodiment, the array substrate can be manufactured by using the five masks as the basic structure. That is,
The pixel electrode is arranged in the uppermost layer, and along with this, the semiconductor film and the like, together with the signal line, the source, and the drain electrode, are collectively patterned based on the same mask pattern.
The contact hole for connecting the source electrode and the pixel electrode is made at the same time as the making of the contact hole for exposing the connection end of the signal line and the scanning line. This is an optimal process that simultaneously fulfills different requirements such as preventing the above and improving productivity with a small number of masks.

(Other Modifications) In this embodiment, the case where the semiconductor film is made of a-Si: H has been described, but a microcrystalline silicon film, a polycrystalline silicon film, a single crystal silicon film, or the like may be used. It goes without saying that it is also good. Further, the drive circuit portion may be integrally formed in the peripheral region.

Further, when the pixel electrodes are partially overlapped on the signal lines or the scanning lines, the shield electrode should be arranged at least between the pixel electrode and the signal line with a metal film or the like via an insulating layer. Then, the pixel electrode can reduce the influence of the potential from the signal line.

Further, in the above-mentioned embodiments, the light transmission type liquid crystal display device is used, and the case where the pixel electrode is made of the transparent conductive film, for example, ITO has been described. For this reason, the electrical connection between the lower layer wiring portion and the upper layer wiring portion is made of ITO that is arranged through the pair of contact holes.
Through a connection layer consisting of. Since this ITO has a relatively high resistance, it is desirable that the gap between the pair of contact holes is short, for example, 20 microns or less, and further 15 microns or less. A low resistance material can be used if this connection layer is manufactured in a process different from that of the pixel electrode. Further, in the case of the reflection type, since the pixel electrode can be formed of a low resistance material such as aluminum, the gap between the pair of contact holes is not greatly limited.

As the liquid crystal layer, various materials such as polymer dispersion type liquid crystal, ferroelectric liquid crystal, antiferroelectric liquid crystal and the like can be applied other than TN liquid crystal.

[0165]

As described above in detail, according to the array substrate for a display device and the manufacturing method thereof of the present invention, the auxiliary capacitance is formed by overlapping the scanning line and the pixel electrode without lowering the manufacturing yield. It is possible to achieve higher aperture ratio.

Further, according to the present invention, it is possible to secure high productivity with a small number of masks without lowering the manufacturing yield.

Further, according to the array substrate for a display device of the present invention, when a voltage is applied to the auxiliary capacitance line connecting portion, all the auxiliary capacitance lines can have the same potential.

Further, according to the array substrate for a display device of the present invention, it is difficult for the scanning line lead-out portion and the signal line lead-out portion to be disconnected.

[Brief description of the drawings]

FIG. 1 is a partial schematic plan view of an array substrate according to an embodiment of the present invention.

FIG. 2 is a schematic cross-sectional view of the liquid crystal display device taken along the line AA ′ in FIG.

3 is a schematic cross-sectional view of the liquid crystal display device taken along line BB ′ in FIG.

4 is a schematic cross-sectional view of the liquid crystal display device taken along the line CC 'in FIG.

5 is a schematic cross-sectional view of the liquid crystal display device taken along line DD 'in FIG.

6 is a schematic cross-sectional view of the liquid crystal display device taken along line EE ′ in FIG.

FIG. 7 is a diagram for explaining a first step of manufacturing the array substrate in FIG.

FIG. 8 is a diagram for explaining a second step of manufacturing the array substrate in FIG.

9 is a diagram for explaining a third step of manufacturing the array substrate in FIG. 1. FIG.

10 is a diagram for explaining a fourth step of manufacturing the array substrate in FIG. 1. FIG.

FIG. 11 is a view for explaining a fifth step of manufacturing the array substrate in FIG.

12 is a diagram for explaining a sixth step of manufacturing the array substrate in FIG. 1. FIG.

FIG. 13 is a diagram for explaining a seventh step of manufacturing the array substrate in FIG. 1.

FIG. 14 is a diagram showing a modification example of the structure near the outer peripheral portion of the signal line.

FIG. 15 is a partial schematic plan view of an array substrate according to a second embodiment of the present invention.

16 is a schematic cross-sectional view of the liquid crystal display device taken along the line AA ′ in FIG.

FIG. 17 is a schematic cross-sectional view of the liquid crystal display device taken along the line BB ′ in FIG.

FIG. 18 is a schematic cross-sectional view of the liquid crystal display device taken along the line CC ′ in FIG. 15.

19 is a schematic cross-sectional view of the liquid crystal display device taken along the line DD ′ in FIG.

FIG. 20 is a diagram for explaining a first step of manufacturing the array substrate in FIG. 15.

FIG. 21 is a diagram for explaining a second step of manufacturing the array substrate in FIG. 15.

22 is a diagram for explaining a third step of manufacturing the array substrate in FIG. 15. FIG.

FIG. 23 is a diagram for explaining a fourth step of manufacturing the array substrate in FIG. 15.

FIG. 24 is a diagram for explaining a fifth step of manufacturing the array substrate in FIG. 15.

FIG. 25 is a diagram for explaining a sixth step of manufacturing the array substrate in FIG. 15.

FIG. 26 is a diagram for explaining a seventh step of manufacturing the array substrate in FIG. 15.

FIG. 27 is a partial schematic plan view of an array substrate of a modification of the second embodiment.

FIG. 28 is a partial schematic plan view of an array substrate according to a third embodiment of the present invention.

29 is a schematic cross-sectional view of the liquid crystal display device taken along the line AA ′ in FIG. 28.

30 is a schematic cross-sectional view of the liquid crystal display device taken along the line BB ′ in FIG. 28.

31 is a schematic cross-sectional view of the liquid crystal display device taken along the line CC ′ in FIG. 28.

32 is a diagram for explaining a first step of manufacturing the array substrate in FIG. 28. FIG.

FIG. 33 is a diagram for explaining the second step of manufacturing the array substrate in FIG. 28.

34 is a diagram for explaining a third step of manufacturing the array substrate in FIG. 28. FIG.

FIG. 35 is a diagram for explaining a fourth step of manufacturing the array substrate in FIG. 28.

FIG. 36 is a diagram for explaining a fifth step of manufacturing the array substrate in FIG. 28.

37 is a diagram for explaining the sixth step of manufacturing the array substrate in FIG. 28. FIG.

FIG. 38 is a diagram for explaining the seventh step of manufacturing the array substrate in FIG. 28.

[Explanation of symbols]

 110 signal line 111 scanning line 112 thin film transistor 113 extension region 115 first insulating film 117 first insulating film 120 semiconductor film 126a drain electrode 126b source electrode 131 pixel electrode

Front page continuation (72) Inventor Kazunari Mori 33, Shinisogo-cho, Isogo-ku, Yokohama-shi, Kanagawa Prefectural Institute of Industrial Science and Technology, Ltd. In the company's Toshiba Himeji Plant (72) Inventor Makoto Shibusawa 50 Kamimabe, Yobu Ward, Himeji City, Hyogo Prefecture Engineering Co., Ltd.

Claims (17)

[Claims] 1. A scanning line arranged on a substrate, a first insulating film arranged on the scanning line, a semiconductor film arranged on the scanning line, a source electrode and a drain electrode electrically connected to the semiconductor film. An array substrate for a display device, comprising: a thin film transistor including; a signal line derived from the drain electrode and substantially orthogonal to the scanning line; and a pixel electrode electrically connected to the source electrode, wherein the pixel electrode Is electrically connected to the source electrode through at least a second insulating film disposed on the signal line, and the pixel electrode overlaps with the adjacent scanning line through the first and second insulating films. An array substrate for a display device, which is characterized by: 2. The scanning line extends between the signal line and the pixel electrode, and includes an extending region that overlaps the pixel electrode via the first and second insulating films. The array substrate for a display device according to claim 1. 3. A semiconductor layer made of the same material as the semiconductor film, which substantially matches the contour line of the signal line, is interposed between the signal line and the first insulating film. Item 2. An array substrate for a display device according to item 1. 4. A scanning line arranged on a substrate, a first insulating film arranged on the scanning line, a semiconductor film arranged on the scanning line, a channel protective film arranged on the semiconductor film, and the semiconductor film. A thin film transistor including a source electrode and a drain electrode electrically connected to the pixel electrode, a signal line derived from the drain electrode and substantially orthogonal to the scanning line, and a pixel electrode electrically connected to the source electrode. In the method of manufacturing an array substrate for a display device, comprising: a step of forming a first wiring layer including the scanning line on the substrate; a step of depositing the first insulating film and a semiconductor film; and a metal thin film depositing step. A second pattern including at least the signal line, the source electrode and the drain electrode by patterning at least the metal thin film and the semiconductor film based on the same mask.
Forming a wiring layer, depositing a second insulating film and forming a first contact hole in the second insulating film corresponding to the source electrode, and electrically connecting to the source electrode through the contact hole. And a step of forming the pixel electrode that is connected to the scanning line and that overlaps with the scanning line via the first and second insulating films. 5. The second and third contact holes exposing a part of the first wiring layer and a part of the second wiring layer are formed at the same time when the first contact hole is formed. The method for manufacturing an array substrate for a display device according to claim 4. 6. The pixel electrode has a first overlapping region that overlaps with an extending region from the adjacent one scanning line via the first and second insulating films, and one or more adjacent to the pixel electrode. A light-shielding layer made of the same material as the signal line, which is partially overlapped with the adjacent scan line so as to block light leakage from a gap between the scan line and another scan line, and the signal line. The array substrate for a display device according to claim 1, further comprising a second overlapping region that overlaps with the second insulating film. 7. The array substrate for a display device according to claim 6, wherein the extending region of the scanning line extends between the signal line and the pixel electrode. 8. A semiconductor layer made of the same material as that of the semiconductor film is arranged between the light shielding layer and the first insulating film so as to substantially match the contour of the light shielding layer. The array substrate for a display device according to claim 6. 9. A scan line arranged on a substrate, a first insulating film arranged on this, a semiconductor film arranged on this, a source electrode and a drain electrode electrically connected to the semiconductor film. In a method of manufacturing an array substrate for a display device, which includes a thin film transistor including, a signal line that is derived from the drain electrode and is substantially orthogonal to the scanning line, and a pixel electrode that is electrically connected to the source electrode, A first step of forming the scan line; a second step of depositing the first insulating film and a semiconductor film; a metal thin film is deposited; and the metal thin film and the semiconductor film are patterned based on the same mask. A third step of forming a signal line, the source electrode and the drain electrode; and a step of depositing a second insulating film and forming a first contact hole in the second insulating film corresponding to the source electrode. 4 steps, and 5 step of forming the pixel electrode electrically connected to the source electrode through the contact hole and overlapping with the scan line through the first and second insulating films. In addition, at the position other than the thin film transistor and across the pixel electrode and the adjacent one or another scanning line, the first insulating film and the semiconductor film are deposited simultaneously with the second step. A step of depositing the metal thin film at the same time as the third step, and patterning the metal thin film and the semiconductor film based on the mask to form the light shielding layer; and simultaneously with the fourth step, A step of depositing the second insulating film; and a step of forming the pixel electrode so as to cover a part of the one scanning line or another scanning line simultaneously with the fifth step. Method of manufacturing shows apparatus for the array substrate. 10. A plurality of scanning lines arranged on a substrate and including a gate electrode region, an auxiliary capacitance line substantially parallel to the scanning line, a first insulating film arranged on the auxiliary capacitance line, and at least on the gate electrode region. A thin film transistor including a semiconductor film disposed on the thin film transistor, a source electrode and a drain electrode electrically connected to the semiconductor film, a second insulating film disposed on the thin film transistor, and the second insulating film on the drain electrode. In a display device array substrate, comprising: a signal line that is substantially orthogonal to the scanning line electrically connected through a pixel electrode; and a pixel electrode electrically connected through the source electrode and the second insulating film. , Each of the auxiliary capacitance lines includes a bundled wire that is wired in a direction substantially orthogonal to each of the auxiliary capacitance lines through the first and second insulating films, and each of the auxiliary capacitance lines and the bundled wire are conductive. Layers Display device for an array substrate, which comprises a storage capacitance line connection portion electrically connected to. 11. The display device according to claim 10, wherein in the auxiliary capacitance line connecting portion, the bundled wiring is made of the same material as the signal line, and the conductive layer is made of the same material as the pixel electrode. Array substrate. 12. A low resistance semiconductor film is interposed between the semiconductor film and the source electrode and the drain electrode, and the low resistance semiconductor film is interposed between the signal line and the semiconductor layer in the intersection region. 11. The array substrate for a display device according to claim 10, further comprising a low resistance semiconductor layer made of the same material as that of FIG. 13. The array substrate for a display device according to claim 10, wherein the semiconductor film is mainly composed of amorphous silicon. 14. A scanning line arranged on a substrate, a first insulating film arranged on the scanning line, a semiconductor film arranged on the first insulating film,
A thin film transistor including a source electrode and a drain electrode electrically connected to the semiconductor film, a signal line derived from the drain electrode and substantially orthogonal to the scanning line, and a pixel electrically connected to the source electrode In an array substrate for a display device including an electrode, a scanning line lead-out portion that draws out the scanning line is arranged at a scanning line terminal portion located at a peripheral portion on the substrate, and the scanning line lead-out portion is the scanning line. A first conductive layer formed of the same material as the above, and a second conductive layer formed of the same material as the signal line via the first conductive layer and an insulating layer, and the first conductive layer and the above An array substrate for a display device, which is electrically connected to the second conductive layer by a connection layer formed of the same material as the pixel electrode. 15. A scanning line arranged on a substrate, a first insulating film arranged on the scanning line, a semiconductor film arranged on the first insulating film,
A thin film transistor including a source electrode and a drain electrode electrically connected to the semiconductor film, a signal line derived from the drain electrode and substantially orthogonal to the scanning line, and a pixel electrically connected to the source electrode In an array substrate for a display device including electrodes, a signal line lead-out portion that draws out the signal line is arranged at a signal line terminal portion located at a peripheral portion on the substrate, and the signal line lead-out portion is the scanning line. A first conductive layer formed of the same material as the above, and a second conductive layer formed of the same material as the signal line via the first conductive layer and an insulating layer, and the first conductive layer and the above An array substrate for a display device, which is electrically connected to the second conductive layer by a connection layer formed of the same material as the pixel electrode. 16. A scanning line disposed on a substrate, a first insulating film disposed on the scanning line, a semiconductor film disposed on the scanning line, and a source electrode and a drain electrode electrically connected to the semiconductor film. A thin film transistor including: a second insulating film disposed on the thin film transistor; a signal line electrically connected to the drain electrode via the second insulating film; and a signal line substantially orthogonal to the scanning line; and the source electrode. A pixel electrode electrically connected to the signal line via the second insulating film, a signal line terminal portion electrically connected to the signal line via a signal line lead portion, and a scanning line lead portion to the scan line. In the array substrate for a display device, which includes a scanning line terminal portion electrically connected to each other via a scanning line terminal portion, the signal line terminal portion and the scanning line terminal portion are formed of the same material as the scanning line. Layer and placed on this first conductive layer And a second conductive layer made of the same material as the pixel electrode. 17. The signal line lead-out portion and the scan line lead-out portion include the first conductive layer formed of the same material as the scan line, and the signal via the first conductive layer and the first insulating film. And a third conductive layer formed of the same material as the wire, wherein the first conductive layer and the third conductive layer are electrically connected via the second conductive layer. The array substrate for a display device according to claim 16.