JPH0915642A - Liquid crystal display device - Google Patents

Liquid crystal display device

Info

Publication number
JPH0915642A
JPH0915642A JP16435695A JP16435695A JPH0915642A JP H0915642 A JPH0915642 A JP H0915642A JP 16435695 A JP16435695 A JP 16435695A JP 16435695 A JP16435695 A JP 16435695A JP H0915642 A JPH0915642 A JP H0915642A
Authority
JP
Japan
Prior art keywords
pixel electrode
liquid crystal
gate
bus line
display device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP16435695A
Other languages
Japanese (ja)
Other versions
JP2716004B2 (en
Inventor
Susumu Oi
進 大井
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP7164356A priority Critical patent/JP2716004B2/en
Publication of JPH0915642A publication Critical patent/JPH0915642A/en
Application granted granted Critical
Publication of JP2716004B2 publication Critical patent/JP2716004B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Abstract

PURPOSE: To prevent after image, burning and the drop of a contrast ratio owing to designations by enlarging superposition between a pixel electrode forming a gate storage and a prestage gate bus line in the area easy to cause an orient defect owing to horizontal direction electric field in a pixel periphery compared with the area except that area. CONSTITUTION: The gate storage formed between the pixel electrode 14 and the prestage gate bus line 11 is used as storage capacity. On the other hand, a thin film transistor(TFT) substrate is rubbed in the right downward direction, and a color filter(CF) substrate is rubbed in the left upward direction. A superposition amount (a) of the pixel electrode onto the gate bus line 11 in the vicinity of left upward corner of the pixel electrode 14 opposite to the rubbing direction of the TFT substrate side is made larger than the superposition amount (b) of the pixel electrode onto the gate line in the vicinity of right upward corner of the pixel electrode. Thus, since the superposition of the gate storage in the area that the invasion distance of the disclination is large in the vicinity of left upward corner of the pixel is large, the invasion of the disclination onto the pixel area is suppressed.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、前段のゲートバス配線
と画素電極間に蓄積容量を形成した薄膜トランジスタ駆
動のアクティブマトリックス型液晶表示装置に関し、特
に、横方向電界による配向不良を低減した高視認性の液
晶表示装置に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an active matrix type liquid crystal display device driven by a thin film transistor in which a storage capacitor is formed between a preceding gate bus line and a pixel electrode. Liquid crystal display device.

【0002】[0002]

【従来の技術】液晶ディスプレイ(以下、LCDと記
す)はコンパクト性、低消費電力性により、その需要は
拡大している。また機能的にも大画面化、高精細化、多
階調化が進められている。パネルの高精細化に伴い、画
素サイズの縮小化、あるいは配線と画素電極間の距離の
減少により画素電極周囲での横方向電界が強くなり、横
方向電界に起因する配向不良が問題となってきている。
これは更に高視野角化が期待される、画素内に複数の配
向状態を持つマルチドメイン型の液晶表示装置では、配
向ドメインの縮小化や不安定化でそれが顕著となってい
る。
2. Description of the Related Art Demand for liquid crystal displays (hereinafter, referred to as LCDs) is expanding due to their compactness and low power consumption. Functionally, a large screen, high definition, and multiple gradations are being promoted. As the definition of the panel becomes higher, the horizontal electric field around the pixel electrode becomes stronger due to the reduction of the pixel size or the distance between the wiring and the pixel electrode, resulting in a problem of poor alignment caused by the horizontal electric field. ing.
This is remarkable in a multi-domain liquid crystal display device having a plurality of alignment states in a pixel, which is expected to have a higher viewing angle, due to a reduction in the alignment domain and instability.

【0003】薄膜トランジスタ(以下、TFTと記す)
をアドレス素子とするアクティブマトリックス型液晶表
示装置はコントラスト比、視野角、応答性などの表示性
能が単純マトリックス型液晶表示装置に比べ優れている
ため、その需要が高まってきている。
A thin film transistor (hereinafter, referred to as TFT)
An active matrix type liquid crystal display device having an address element as an address element has a higher display performance such as a contrast ratio, a viewing angle, and a response than a simple matrix type liquid crystal display device, and thus the demand thereof is increasing.

【0004】TFTアクティブマトリックス型液晶表示
装置は、ゲート線を線順次走査で高電位にすることで選
択し、それにつながるTFTをオン状態にして、データ
線に表示すべき輝度に対応した電圧を印加する事で画素
電極に所定の電圧を書き込む。画素電極には液晶容量と
蓄積容量が付随しており、画素電位を次の書き込みが行
われるまでの1フレーム期間書き込み電圧を保持する。
この保持された画素電極電圧と対向電極電圧との差電圧
が液晶層に印加され、その差電圧に応じた輝度表示を行
うことになる。ここで画素電極に付加される蓄積容量
は、保持期間でのTFTのリーク電流起因の画素電極の
変動を抑えたり、TFTがオン状態からオフ状態に遷移
する際に画素電極とゲート電極間の容量結合(TFTの
ゲートとオースとのオーバーラップ容量が主)により画
素電極電位が変移(フィードスルー)する量を低減する
ことを目的としている。フィードスルー量は液晶の誘電
率異方性により、階調により異なるが、フィードスルー
量が大きいと階調によっては直流電圧(液晶は焼き付き
防止のため交流駆動されている)が印加され、液晶の焼
き付きなどの信頼性上の問題を引き起こすとされてい
る。
A TFT active matrix type liquid crystal display device selects a gate line by setting a high potential by line-sequential scanning, turns on a TFT connected to the gate line, and applies a voltage corresponding to the luminance to be displayed on the data line. Then, a predetermined voltage is written to the pixel electrode. The pixel electrode is provided with a liquid crystal capacitance and a storage capacitance, and holds the pixel potential at a writing voltage for one frame period until the next writing is performed.
The difference voltage between the held pixel electrode voltage and the counter electrode voltage is applied to the liquid crystal layer, and a luminance display corresponding to the difference voltage is performed. Here, the storage capacitance added to the pixel electrode suppresses the fluctuation of the pixel electrode due to the leakage current of the TFT during the holding period, or the capacitance between the pixel electrode and the gate electrode when the TFT changes from the on state to the off state. The purpose is to reduce the amount of change (feedthrough) of the pixel electrode potential due to coupling (mainly the overlap capacitance between the gate of the TFT and the aus). The feedthrough amount differs depending on the gradation due to the dielectric anisotropy of the liquid crystal. However, if the feedthrough amount is large, a DC voltage (the liquid crystal is driven by an alternating current to prevent image sticking) is applied depending on the gradation, and It is said to cause reliability problems such as burn-in.

【0005】蓄積容量には、従来、コモンストレージ型
の蓄積容量が用いられていた。図6(a),(b),
(c)にコモンストレージ型の液晶表示装置の上面図、
断面図及び等価回路をそれぞれ示す。図6において、ゲ
ート線11と同じ層に容量線23を形成し、この容量線
と画素電極14間に容量を形成し、容量線23に低電圧
(例えば対向電極と同じ電圧)を印加する事で蓄積容量
18として動作させている。表示ノイズを防止するため
の容量線の低インビーダンス化や、容量線自体ゲート線
と同層で形成されている(工程数を増やさないため)た
め、容量線が画素電極(透明電極)を横切る領域は光が
透過できず、表示輝度が低下すると言う問題がある。
Conventionally, a common storage type storage capacity has been used as the storage capacity. 6 (a), (b),
(C) is a top view of a common storage type liquid crystal display device,
A sectional view and an equivalent circuit are shown, respectively. 6, a capacitor line 23 is formed in the same layer as the gate line 11, a capacitor is formed between the capacitor line and the pixel electrode 14, and a low voltage (for example, the same voltage as the counter electrode) is applied to the capacitor line 23. Are operated as storage capacitors 18. Since the capacitance line for preventing display noise is lowered and the capacitance line itself is formed in the same layer as the gate line (in order to avoid an increase in the number of steps), the capacitance line forms a pixel electrode (transparent electrode). There is a problem that the light cannot pass through the crossing area, and the display luminance is reduced.

【0006】コモンストレージ型の欠点を補い蓄積容量
を形成する方法として特開昭59−16685で開示さ
れているゲートストレージ型の蓄積容量が知られてい
る。図7(a),(b),(c)にゲートストレージ型
の蓄積容量を用いた液晶パネルの上面図、断面図及び等
価回路図を示す。図7(a)に示すように画素電極14
を前段のゲート線11に重ねる事で、画素電極とゲート
線間に容量18を形成している。前段のゲート線は既に
選択が終了し、一定電圧になっているので、蓄積容量の
一端の電極として用いる事ができる。この構成によれ
ば、コモンストレージ型のように新たな容量配線が必要
でないので、光が透過する領域の面積比率(開口率と生
する)を上げる事ができ、表示輝度が上昇する。
A gate storage type storage capacitor disclosed in Japanese Patent Application Laid-Open No. Sho 59-16685 is known as a method for forming a storage capacitor by compensating for the disadvantages of the common storage type. FIGS. 7A, 7B, and 7C show a top view, a cross-sectional view, and an equivalent circuit diagram of a liquid crystal panel using a gate storage type storage capacitor. As shown in FIG.
Is overlapped with the gate line 11 in the preceding stage, thereby forming a capacitor 18 between the pixel electrode and the gate line. Since the selection of the gate line at the previous stage has already been completed and the voltage has become constant, it can be used as an electrode at one end of the storage capacitor. According to this configuration, a new capacitor wiring is not required unlike the common storage type, so that the area ratio of the region through which light is transmitted (the aperture ratio is generated) can be increased, and the display luminance increases.

【0007】一方、一般にTN(ツイストネマチック)
型の液晶は、TFT基板側とカラーフィルター(以降C
Fと記す)側の基板にそれぞれ配向膜(通常ポリイミ
ド)を塗布し、レーヨンなどの布を巻いたローラで擦る
事(ラビング処理)で、液晶分子の界面配向の方向を制
御している。TFT基板とCF基板側ではラビング方向
を90度前後捻る事で液晶は90度前後捻れた状態で配
向する事になる。また配向膜上をラビング処理を行う
と、棒状の液晶分子はそのラビング方向にある角(プレ
チルト角)をもって配向する。
On the other hand, in general, TN (twisted nematic)
Type liquid crystal is connected to the TFT substrate side and a color filter (hereinafter C
An orientation film (usually polyimide) is applied to each of the substrates on the F side, and rubbed with a roller wrapped with cloth such as rayon (rubbing treatment) to control the direction of the interface orientation of the liquid crystal molecules. By twisting the rubbing direction 90 degrees back and forth on the TFT substrate and CF substrate side, the liquid crystal is oriented in a state twisted 90 degrees forward and backward. When a rubbing treatment is performed on the alignment film, the rod-like liquid crystal molecules are aligned at an angle (pretilt angle) in the rubbing direction.

【0008】液晶に電圧が掛かっていない状態では液晶
分子は横に寝た状態でツイスト配向しているが、液晶に
電圧を印加すると液晶分子は立ち上がる。この時液晶分
子の立ち上がる方向は、画素電極と対向電極間の垂直電
界が支配的な領域では、プレチルト角方向と同じ方向に
なる。通常、TFT基板、CF基板とも液晶分子の立ち
上がり方向とプレチルト角方向が一致するようラビング
方向、液晶のカエラル方向(ツイストする回転方向)が
選択される。例えば図8に示すようなラビング方向の設
定で、左回りのTN液晶では、画素中央部では横方向電
界の影響がないので、液晶分子はプレチルト角方向に立
ち上がる。
When no voltage is applied to the liquid crystal, the liquid crystal molecules are twisted while lying horizontally, but when a voltage is applied to the liquid crystal, the liquid crystal molecules rise. At this time, the rising direction of the liquid crystal molecules is the same as the pretilt angle direction in a region where the vertical electric field between the pixel electrode and the counter electrode is dominant. Usually, the rubbing direction and the liquid crystal's chiral direction (twisting rotation direction) are selected so that the rising direction of the liquid crystal molecules and the pretilt angle direction coincide with both the TFT substrate and the CF substrate. For example, in the setting of the rubbing direction as shown in FIG. 8, in the counterclockwise TN liquid crystal, since there is no influence of the horizontal electric field in the central portion of the pixel, the liquid crystal molecules rise in the pretilt angle direction.

【0009】しかし、画素電極端では画素電極と周辺配
線間との横方向電界の影響が顕在化してくる。TFT基
板側のラビング向きの延長線上の画素端では液晶分子の
プレチルト方向と横方向電界による液晶分子が立ち上が
る(液晶の誘電率異方性のため)方向が一致しているた
め、画素中央部と同じ向きに立ち上がり液晶配向不良領
域は発生しないが、ラビング方向の逆の画素端では横方
向電界により液晶分子の立ち上がる向きと、プレチルト
角方向が逆になっており、画素中央部と異なる方向に液
晶分子は立ち上がり、配向不良(リバースチルト)領域
が発生する。この配向不良領域と正常配向領域境界には
通常ディスクリネーション線24という遷移領域が形成
される。これは液晶が白状態と同じ寝た状態となってい
るので明るい輝線として認識され、コントラストが低下
する。またディスクリネーション線は画素電圧の変動で
移動するので、ディスクリネーション線が表示領域に現
われると残像、あるいは焼き付きとなったりして、表示
性能の劣化をもたらす。この横電界の影響は表示容量の
増大による画素サイズの現象に伴ない益々大きな問題と
なる。
However, the influence of the lateral electric field between the pixel electrode and the peripheral wiring becomes obvious at the pixel electrode end. At the pixel end on the extension line of the rubbing direction on the TFT substrate side, the pretilt direction of the liquid crystal molecules and the direction in which the liquid crystal molecules rise due to the lateral electric field (due to the dielectric anisotropy of the liquid crystal) coincide with each other. No liquid crystal alignment failure area occurs in the same direction, but at the pixel end opposite to the rubbing direction, the direction in which the liquid crystal molecules rise due to the lateral electric field and the pretilt angle direction are opposite, and the liquid crystal is oriented in a different direction from the pixel center. The molecules rise, and a misalignment (reverse tilt) region occurs. A transition region called a normal disclination line 24 is formed at the boundary between the poor alignment region and the normal alignment region. This is recognized as a bright bright line because the liquid crystal is in the same lying state as the white state, and the contrast is reduced. In addition, since the disclination line moves due to the fluctuation of the pixel voltage, when the disclination line appears in the display area, an afterimage or burn-in occurs, and the display performance is deteriorated. The influence of the horizontal electric field becomes a more serious problem with the phenomenon of the pixel size due to the increase in the display capacity.

【0010】この横方向電界によるリバースチルト配向
は、前述のゲートストレージ型の蓄積容量では画素電極
がゲートバス線上をある程度覆っているので、横電界が
ある程度緩和される。この緩和効果を上げる為に画素電
極のゲートバスを覆っている面積を増大させると画素電
極に付随する総容量が増大し、画素の書き込みが不十分
となる。
In the reverse tilt alignment due to the lateral electric field, the lateral electric field is alleviated to some extent because the pixel electrode covers the gate bus line to some extent in the aforementioned gate storage type storage capacitor. If the area of the pixel electrode covering the gate bus is increased in order to increase the relaxation effect, the total capacitance associated with the pixel electrode increases, and the writing of the pixel becomes insufficient.

【0011】横方向電界の影響を防止する策としては、
特開平4−51121で先行例が開示されている。これ
は図9に示すように画素電極14より上層に画素電極周
囲を囲むように蓄積容量18を形成している。更にこの
蓄積容量は対向電極の電位と同じ電位にする事で、画素
電極との間に蓄積容量を形成すると供に、画素電極周囲
の横方向電界を抑える事が出来る。しかし、この構成を
実現するには、成膜工程、フォトリソグラフィ工程、エ
ッチング工程が増え、TFT基板の作成コストが上昇す
るという問題がある。
As a measure for preventing the influence of the lateral electric field,
A prior example is disclosed in JP-A-4-51121. As shown in FIG. 9, a storage capacitor 18 is formed above the pixel electrode 14 so as to surround the pixel electrode. Further, by setting the storage capacitor to the same potential as the potential of the counter electrode, a storage capacitor can be formed between the storage capacitor and the pixel electrode, and the lateral electric field around the pixel electrode can be suppressed. However, in order to realize this configuration, there is a problem that the film formation process, the photolithography process, and the etching process are increased, and the production cost of the TFT substrate is increased.

【0012】また、近年視野角を増加させる為に、特開
昭52−21845に開示されているような一画素内の
配向を複数にする構成(マルチドメイン)が検討されて
いる。液晶分子の立ち上がり方向に起因する非対称な視
野角特性を補償しあう事で、視野角の広い表示装置が得
られる事は報告されている。例えば、図10に示すよう
な一画素内を二分割し液晶の立ち方がそれぞれ上下方向
になるように液晶19を配向させる事が多数試みられて
いる。このような構成により電圧印加時に液晶分子が下
側に立ち上がる領域と上側に立ち上がる領域が形成さ
れ、上下の視野特性は従来の上視野と下視野特性を合成
した特性となり、特に下視野での階調反転防止に絶大な
効果があることが知られている。
In recent years, in order to increase the viewing angle, a configuration (multi-domain) in which one pixel has a plurality of orientations as disclosed in Japanese Patent Application Laid-Open No. 52-21845 has been studied. It has been reported that a display device having a wide viewing angle can be obtained by compensating for asymmetric viewing angle characteristics caused by the rising direction of liquid crystal molecules. For example, many attempts have been made to divide the inside of one pixel into two as shown in FIG. 10 and to align the liquid crystal 19 so that the liquid crystal stands in the vertical direction. With such a configuration, a region where liquid crystal molecules rise downward and a region where the liquid crystal molecule rises upward when voltage is applied are formed, and the upper and lower viewing characteristics are characteristics obtained by combining the conventional upper and lower viewing characteristics. It is known that there is a tremendous effect in preventing key reversal.

【0013】この二分割配向の一つの実現方法がDis
play92、P591、1992に開示されている。
この方法はTFT基板上には高プレチルト配向膜を、C
F基板上には低プレチルト配向膜をそれぞれ形成し、T
FT基板上の配向膜のラビング方向を配向分割領域で異
ならせる事を特徴とする。液晶配向は高プレチルト配向
膜上のラビング方向で規定されるので、液晶の配向状態
はTFT基板側のラビング方向に対応して分割され、マ
ルチドメインを実現している。
One method of realizing this two-segment orientation is Dis.
play92, P591, 1992.
In this method, a high pretilt alignment film is formed on a TFT substrate,
A low pretilt alignment film is formed on the F substrate,
The rubbing direction of the alignment film on the FT substrate is made different in the alignment division region. Since the liquid crystal alignment is defined by the rubbing direction on the high pretilt alignment film, the alignment state of the liquid crystal is divided according to the rubbing direction on the TFT substrate side to realize multi-domain.

【0014】例えば図10(a)に示した方向でラビン
グした場合、図10(c)に示すように領域BではTF
T基板、CF基板とも電圧印加時の液晶分子の立ち上が
り方向とラビング方向が一致している通常の配向状態と
なるので、領域Bの左上の角近傍が横方向電界によるデ
ィスクリネーションが発生しやすい。一方領域Aは、図
10(b)に示すようにTFT基板側はラビング方向と
液晶分子の立ち上がり方向が一致しているが、CF基板
側ではラビング方向と液晶分子の立ち上がり方向が異な
る。その結果、CF基板近傍ではスプレイ状態の配向と
なる。スプレイ配向は液晶分子の体積歪みが大きく、エ
ネルギー的に不安定な状態となり、リバースチルト、リ
バースツイスト(液晶分子が逆方向に回転する)などの
配向不良が発生しやすい。図10の場合には、スプレイ
配向となる領域Aの右下はラビング方向と横方向電界に
よる液晶分子の立ち上がり方が異なるためリバースチル
トが発生しやすいが、それ以外に、通常配向では安定な
右上の領域でも横方向電界の影響でリバースチルトが発
生しやすくなる。
For example, when rubbing is performed in the direction shown in FIG. 10A, as shown in FIG.
Since both the T substrate and the CF substrate are in a normal alignment state in which the rising direction of the liquid crystal molecules and the rubbing direction upon application of a voltage match, disclination due to the lateral electric field is likely to occur near the upper left corner of the region B. . On the other hand, in the region A, as shown in FIG. 10B, the rubbing direction and the rising direction of the liquid crystal molecules are the same on the TFT substrate side, but the rubbing direction and the rising direction of the liquid crystal molecules are different on the CF substrate side. As a result, in the vicinity of the CF substrate, the orientation is in a splay state. In the splay alignment, the volume distortion of the liquid crystal molecules is large, the energy becomes unstable, and alignment defects such as reverse tilt and reverse twist (the liquid crystal molecules rotate in the opposite direction) are likely to occur. In the case of FIG. 10, the lower right of the region A in the splay alignment is likely to cause a reverse tilt because the rubbing direction is different from the rising direction of the liquid crystal molecule due to the lateral electric field. The reverse tilt is liable to occur even in the area of due to the influence of the lateral electric field.

【0015】TFT基板上の液晶分子のプレチルト角が
大きい程、横方向電界の影響を受け難くなり、プレチル
ト方向と電圧印加時の立ち上がり方向が異なっている場
合のディスクリネーションの進入は抑えられる。これを
2次元の液晶シミュレーション(液晶内の電界分布から
液晶の分子配向を計算)により示したのが図11であ
る。図よりプレチルト角を3度から7度に上げる事でデ
ィスクリネーション侵入距離が5μmから3.5μm程
度まで低下する事が分かる。またCF基板側のラビング
を液晶分子がスプレイ配向状態になる方向に行うと、T
FT基板が同じ7度のプルチルト角でも、ノーマル配向
での3.5μmから5μm程度までディスクリネーショ
ン侵入距離が増大する事が分かる。
As the pretilt angle of the liquid crystal molecules on the TFT substrate is larger, the influence of the lateral electric field is lessened, and the entry of disclination when the pretilt direction is different from the rising direction when a voltage is applied is suppressed. This is shown in FIG. 11 by a two-dimensional liquid crystal simulation (calculation of the liquid crystal molecular orientation from the electric field distribution in the liquid crystal). From the figure, it can be seen that increasing the pretilt angle from 3 degrees to 7 degrees reduces the disclination penetration distance from 5 μm to about 3.5 μm. When rubbing on the CF substrate side is performed in a direction in which liquid crystal molecules are in a splay alignment state, T
It can be seen that even when the FT substrate has the same pull-tilt angle of 7 degrees, the disclination penetration distance increases from 3.5 μm in normal orientation to about 5 μm.

【0016】上述の様に、従来のゲートストレージ容量
はいずれもゲート配線と画素電極の重ね合わせ部が均一
となる構成がとられていた。
As described above, all of the conventional gate storage capacitors have a configuration in which the overlapping portion between the gate wiring and the pixel electrode is uniform.

【0017】[0017]

【発明が解決しようとする課題】前述の従来の画素電極
周囲の横方向電界でのディスクリネーション線が画素電
極領域の内部に深く侵入すると、そのディスクリネーシ
ョン線を遮光する為にCF基板側のブラックマトリック
ス(BM)の面積を広げる必要がある。その結果、BM
の開口面積が減少し、画素領域内で光が通過する面積率
(開口率)が低下して、輝度低下等の視認性劣化或いは
それを補う為にバックライトの電力を上げると消費電力
の増大と言う問題がある。
When the above-mentioned conventional disclination line in a lateral electric field around the pixel electrode penetrates deeply into the pixel electrode region, the CF substrate side is used to shield the disclination line from light. It is necessary to increase the area of the black matrix (BM). As a result, BM
The opening area of the pixel decreases, the area ratio (opening ratio) through which light passes in the pixel region decreases, and the power consumption of the backlight increases to increase the power of the backlight in order to compensate for the deterioration of the visibility such as a decrease in luminance or the like. There is a problem to say.

【0018】本発明は前述の問題を解決し、高輝度、高
視野角で低消費電力のLCDを実現する事を目的とす
る。
An object of the present invention is to solve the above-mentioned problems and realize a low-power-consumption LCD with a high luminance and a high viewing angle.

【0019】[0019]

【課題を解決するための手段】本発明は、薄膜トランジ
スタをスイッチング素子とし、蓄積容量が画素電極と前
段のゲートバス線間に形成されているアクティブマトリ
ックス型液晶表示装置に於いて、前記薄膜トランジスタ
が形成された基板上の配向膜のラビング方向が前段のゲ
ート配線側の画素電極の第1の角から次段のゲート配線
方向に斜めにされており、且つ前記画素電極の第1の角
側の蓄積容量を形成する画素電極と前段のゲートバス線
との重なり量が、画素電極の前段ゲート配線よりの第2
の角側の蓄積容量を形成する画素電極と前段ゲートバス
線との重なり距離に比べ大きくなっている事を特徴とす
る。TFT基板側の液晶分子のプレチルト角が7度以上
では、第1の角側の重なり距離は10μm以上あり、第
2の角側の重なり距離は4μm以上あること、またプレ
チルト角が3度以上では、それぞれ15μm以上,5μ
m以上あることが必要である。
According to the present invention, there is provided an active matrix type liquid crystal display device in which a thin film transistor is used as a switching element and a storage capacitor is formed between a pixel electrode and a preceding gate bus line. The rubbing direction of the alignment film on the substrate is inclined from the first corner of the pixel electrode on the side of the preceding gate line to the direction of the next gate line, and the accumulation on the first corner side of the pixel electrode is performed. The amount of overlap between the pixel electrode forming the capacitor and the preceding gate bus line is equal to the second amount of the pixel electrode from the preceding gate wiring.
Is larger than the overlap distance between the pixel electrode forming the storage capacitor on the corner side and the preceding gate bus line. When the pretilt angle of the liquid crystal molecules on the TFT substrate side is 7 degrees or more, the overlap distance on the first corner side is 10 μm or more, the overlap distance on the second corner side is 4 μm or more, and when the pretilt angle is 3 degrees or more, , 15μm or more and 5μ respectively
m or more.

【0020】[0020]

【実施例】次に本発明について図面を参照して説明す
る。図1(a),(b),(c)はそれぞれ本発明の第
1の実施例を示すLCDパネルの上面図とその点線A−
Aにおける断面図、及び等価回路図である。本実施例で
は、画素電極14と前段ゲートバス線11間で形成され
たゲートストレージを蓄積容量として用いている。一
方、TFT基板上のラビング方向は右下方向に、CF基
板では左上方向にラビングされている。TFT基板側の
ラビングの向きの反対側に当たる画素電極14の左上角
近傍の画素電極のゲートバス線11への重なり量aは、
画素電極右上の角近傍の画素電極のゲート線への重なり
距離bに比べ大きくしてある。
DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings. FIGS. 1A, 1B, and 1C are respectively a top view of an LCD panel showing a first embodiment of the present invention and a dotted line A-.
2A is a sectional view and an equivalent circuit diagram. FIG. In the present embodiment, a gate storage formed between the pixel electrode 14 and the preceding gate bus line 11 is used as a storage capacitor. On the other hand, the rubbing direction on the TFT substrate is the lower right direction, and the rubbing direction on the CF substrate is the upper left direction. The overlap amount a of the pixel electrode 14 in the vicinity of the upper left corner of the pixel electrode 14 on the opposite side of the rubbing direction on the TFT substrate side to the gate bus line 11 is:
It is larger than the overlap distance b of the pixel electrode near the upper right corner of the pixel electrode to the gate line.

【0021】TFT基板側の液晶分子のプレチルト角を
通常用いられる3度とすると、図11のシミュレーショ
ン結果から左上の角近傍の重なり距離aは約15μm以
上、右上の角近傍の重なり距離bは約5μm以上に設定
する必要がある。また高プレチルト角として現状可能な
7度程度を想定すれば重なり距離aは10μm以上、重
なり距離bは4μm以上とればよい事が図11から分か
る。ここで、重なりの大きい領域の幅Waと重なりの小
さい領域の幅Wbはストレージ面積=a・Wa+b・W
bが、所定の蓄積容量(液晶容量の1/2以上)が得ら
れるようにWa,Wbを設定する。この構成により画素
左上の角近傍のディスクリネーションの進入距離が大き
い個所でのゲートストレージの重なりが大きいため、デ
ィスクリネーションの画素領域までの進入を抑える事が
できる。
Assuming that the pretilt angle of the liquid crystal molecules on the TFT substrate side is 3 degrees, which is usually used, the overlap distance a near the upper left corner is about 15 μm or more and the overlap distance b near the upper right corner is about 15 μm from the simulation result of FIG. It is necessary to set it to 5 μm or more. Further, assuming that the high pretilt angle is about 7 degrees, which is currently possible, the overlapping distance a should be 10 μm or more and the overlapping distance b should be 4 μm or more. Here, the width Wa of the region of large overlap and the width Wb of the region of small overlap are storage area = a · Wa + b · W
Wa and Wb are set so that b can obtain a predetermined storage capacity (1/2 or more of the liquid crystal capacity). With this configuration, the overlap of the gate storages at the location where the approach distance of the disclination near the upper left corner of the pixel is large is large, so that the approach of the disclination to the pixel area can be suppressed.

【0022】図2(a),(b),(c)は本発明の第
2の実施例を示すLCDパネルの上面図と断面図、及び
等価回路図である。本実施例では、ゲートストレージを
画素電極左上の角では重なり距離a、画素電極の右上の
重なり距離bで、それを直線で結んだ形状にしている。
この場合はプレチルト角を3度程度と想定すれば、a≧
10μm、b≧4μmで、かつゲートストレージ面積
(a+b)・W/2が所定の容量が得られるように重な
り距離a,bを選ぶ必要がある。この構成では重なり距
離aを第1の実施例の場合より大きくとる事できるので
ディスクリネーション線の表示領域への侵入をより抑制
する効果が得られる。
FIGS. 2A, 2B, and 2C are a top view, a sectional view, and an equivalent circuit diagram of an LCD panel showing a second embodiment of the present invention. In this embodiment, the gate storage is formed by connecting a straight line with the overlap distance a at the upper left corner of the pixel electrode and the overlap distance b at the upper right corner of the pixel electrode.
In this case, assuming that the pretilt angle is about 3 degrees, a ≧
It is necessary to select the overlapping distances a and b so that 10 μm, b ≧ 4 μm and the gate storage area (a + b) · W / 2 can obtain a predetermined capacity. In this configuration, the overlap distance a can be made larger than in the first embodiment, so that the effect of further suppressing the intrusion of the disclination line into the display area can be obtained.

【0023】図3(a),(b),(c)は本発明の第
3の実施例を示すLCDパネルの上面図と断面図、及び
等価回路図である。本実施例は第1の実施例の構成で、
画素電極の左上の角において、ゲートバス配線上の画素
電極部をデータ線側にcだけはみ出させている。この構
成では、ディスクリネーションが侵入しやすい画素左上
の角が更に距離cだけ離れるので、ディスクリネーショ
ンラインの画素領域への侵入を更に抑制できる。ここで
距離cは僅かでもはみ出させる事で効果はあるが、上方
向へのはみ出し距離10μm程度まで出せれば、より大
きな効果が期待されるが、データ配線のレイアウトとの
バランスを考えて決める必要がある。
FIGS. 3A, 3B, and 3C are a top view, a sectional view, and an equivalent circuit diagram of an LCD panel showing a third embodiment of the present invention. This embodiment has the configuration of the first embodiment.
At the upper left corner of the pixel electrode, the pixel electrode portion on the gate bus wiring protrudes by c toward the data line side. In this configuration, the upper left corner of the pixel where the disclination easily enters is further separated by the distance c, so that the entry of the disclination line into the pixel area can be further suppressed. Here, the effect can be obtained by protruding the distance c even slightly, but a larger effect can be expected if the distance c can be protruded up to about 10 μm. However, it is necessary to determine the distance c in consideration of the balance with the layout of the data wiring. is there.

【0024】図4は、本発明の第4の実施例で一画素内
の配向を二分割した場合である。TFT基板側のラビン
グ方向は、画素電極の上半分のA領域では画素左上に向
けてラビングを行い、画素電極の下半分のB領域では画
素右下に向けてラビングを行っている。一方、CF基板
側は画素右上に向けてラビングを行っている。更に、画
素右上の角部近傍の画素電極のゲートバス線との重なり
aを、画素左上角近傍の画素電極とゲートバス線との重
なりbより大きくしている。この場合Aの領域の液晶は
スプレイ状態の配向となり、画素右上の角近傍ではディ
スクリネーションラインが画素領域に侵入しやすいが、
本構造ではその領域での画素電極のゲートバス線への重
なりが大きいため、画素領域までディスクリネーション
ラインが侵入する事を抑制することができる。図11よ
りTFT基板側のプレチルト角が3度程度の場合は重な
りaは10μm以上、重なりbは5μm以上とる必要が
ある。また7度程度のプレチルト角の場合はaは5μm
以上、bは4μm以上とる必要がある事がわかる。
FIG. 4 shows a case in which the orientation in one pixel is divided into two in the fourth embodiment of the present invention. In the rubbing direction on the TFT substrate side, rubbing is performed toward the upper left of the pixel in the upper half A of the pixel electrode, and rubbing is performed toward the lower right of the pixel in the lower half B of the pixel electrode. On the other hand, rubbing is performed on the CF substrate side toward the upper right of the pixel. Furthermore, the overlap a of the pixel electrode near the upper right corner of the pixel with the gate bus line is larger than the overlap b of the pixel electrode near the upper left corner of the pixel with the gate bus line. In this case, the liquid crystal in the region A is oriented in the splay state, and the disclination line easily enters the pixel region near the upper right corner of the pixel.
In this structure, the pixel electrode greatly overlaps the gate bus line in that region, so that the disclination line can be prevented from entering the pixel region. According to FIG. 11, when the pretilt angle on the TFT substrate side is about 3 degrees, the overlap a needs to be 10 μm or more and the overlap b needs to be 5 μm or more. For a pretilt angle of about 7 degrees, a is 5 μm
As described above, it is understood that b needs to be 4 μm or more.

【0025】図5は、本発明の第5の実施例で、画素右
上角の画素電極をデータ線側にはみ出させて、更にスプ
レイ領域での横方向電界による配向不良領域の侵入を抑
える事ができる。この場合横方向へのはみ出し距離cは
データバス線のレイアウト上可能な範囲でなるべく大き
くとる事で大きな効果が得られる。
FIG. 5 shows a fifth embodiment of the present invention, in which the pixel electrode at the upper right corner of the pixel is protruded to the data line side, and the intrusion of the misalignment region due to the lateral electric field in the spray region can be suppressed. it can. In this case, a great effect can be obtained by setting the protruding distance c in the horizontal direction as large as possible within the range of the layout of the data bus lines.

【0026】本発明は以上の実施例だけでなく、ゲート
ストレージ部の画素電極の前段ゲートバス線への重なり
距離を横電界により配向不良が発生しやすい領域で大き
くする事が本質的であり、画素電極のゲートバス上の形
状は本実施例記載以外の様々な変形が可能である。
According to the present invention, not only the above-described embodiment but also an essential feature is to increase the overlapping distance of the pixel electrode of the gate storage portion to the preceding gate bus line in a region where alignment failure is likely to occur due to a lateral electric field. The shape of the pixel electrode on the gate bus can be variously modified other than that described in this embodiment.

【0027】[0027]

【発明の効果】以上説明した様に本発明の液晶表示装置
では、単一ドメイン配向の場合は、TFT基板側のラビ
ングの向きと逆方向の延長領域、二分割ドメインの配向
の場合は、スプレイ領域でのラビング方向と直角方向の
延長領域など、画素周辺での横方向電界により配向不良
を起こしやすい領域で、それ以外の領域に比べゲートス
トレージを形成する画素電極と前段ゲートバス線の重な
りを大きくする事で、それらの領域で発生するディスク
リネーションの画素領域への侵入を抑制でき、ディスク
リネーション起因の残像、焼き付き、コントラスト比低
下を防止し、優れた表示性能を得ることができる。
As described above, in the liquid crystal display device of the present invention, in the case of single-domain orientation, an extension region in the direction opposite to the rubbing direction on the TFT substrate side, and in the case of two-split domain orientation, spraying is performed. In areas where the lateral electric field around the pixel tends to cause misalignment, such as an area extending in the direction perpendicular to the rubbing direction in the area, the overlap between the pixel electrode forming the gate storage and the previous gate bus line is greater than in other areas. By increasing the size, it is possible to suppress the invasion of the disclination generated in those areas into the pixel area, prevent afterimages, image sticking, and a decrease in contrast ratio due to the disclination, and obtain excellent display performance.

【図面の簡単な説明】[Brief description of the drawings]

【図1】(a),(b),(c)は本発明の第1の実施
例を示す液晶パネルの上面図と断面図、及び等価回路図
である。
FIGS. 1A, 1B, and 1C are a top view, a sectional view, and an equivalent circuit diagram of a liquid crystal panel according to a first embodiment of the present invention.

【図2】(a),(b),(c)は本発明の第2の実施
例を示す液晶パネルの上面図と断面図、及び等価回路図
である。
FIGS. 2A, 2B, and 2C are a top view, a cross-sectional view, and an equivalent circuit diagram of a liquid crystal panel according to a second embodiment of the present invention.

【図3】(a),(b),(c)は本発明の第3の実施
例を示す液晶パネル上面図と断面図、及び等価回路図で
ある。
FIGS. 3A, 3B, and 3C are a top view, a sectional view, and an equivalent circuit diagram of a liquid crystal panel according to a third embodiment of the present invention.

【図4】本発明の第4の実施例を示す液晶パネルの上面
図である。
FIG. 4 is a top view of a liquid crystal panel showing a fourth embodiment of the present invention.

【図5】本発明の第5の実施例を示す液晶パネルの上面
図である。
FIG. 5 is a top view of a liquid crystal panel showing a fifth embodiment of the present invention.

【図6】(a),(b),(c)は従来例を示す液晶パ
ネルの上面図と断面図、及び等価回路図である。
FIGS. 6A, 6B, and 6C are a top view, a cross-sectional view, and an equivalent circuit diagram of a liquid crystal panel showing a conventional example.

【図7】(a),(b),(c)は従来例を示す液晶パ
ネルの上面図と断面図、及び等価回路図である。
7A, 7B, and 7C are a top view, a cross-sectional view, and an equivalent circuit diagram of a liquid crystal panel showing a conventional example.

【図8】(a),(b)は従来例を示す液晶パネルの上
面図と断面図である。
FIGS. 8A and 8B are a top view and a cross-sectional view of a liquid crystal panel showing a conventional example.

【図9】(a),(b),(c)は従来例を示す液晶パ
ネルの上面図と断面図、及び等価回路図である。
FIGS. 9A, 9B, and 9C are a top view, a sectional view, and an equivalent circuit diagram of a liquid crystal panel showing a conventional example.

【図10】(a),(b),(c)は従来例を示す液晶
パネルの上面図と断面図、及び等価回路図である。
FIGS. 10A, 10B, and 10C are a top view, a sectional view, and an equivalent circuit diagram of a liquid crystal panel showing a conventional example.

【図11】TFT基板上のプレチルト角とディスクリネ
ーションラインの侵入距離の関係を示す図である。
FIG. 11 is a diagram showing a relationship between a pretilt angle on a TFT substrate and a penetration distance of a disclination line.

【符号の説明】[Explanation of symbols]

11 ゲート線 12 データ線 13 S/D電極 14 画素電極 15 ゲート絶縁膜 16 TFT 17 液晶容量 18 蓄積容量 19 液晶層 20 対向電極 21 TFT基板 22 CF基板 23 蓄積容量線 24 ディスクリネーション線 25 配向分割線 Reference Signs List 11 gate line 12 data line 13 S / D electrode 14 pixel electrode 15 gate insulating film 16 TFT 17 liquid crystal capacitance 18 storage capacitance 19 liquid crystal layer 20 counter electrode 21 TFT substrate 22 CF substrate 23 storage capacitance line 24 disclination line 25 orientation division line

Claims (6)

【特許請求の範囲】[Claims] 【請求項1】 薄膜トランジスタをスイッチング素子と
し、蓄積容量が画素電極と前段のゲートバス線間に形成
されているアクティブマトリックス型液晶表示装置に於
いて、前記薄膜トランジスタが形成された基板上の配向
膜のラビング方向が前段のゲート配線側の画素電極の第
1の角から次段のゲート配線方向に斜めに形成されてお
り、且つ前記画素電極の第1の角側の蓄積容量を形成す
る画素電極と前段のゲートバス線との重なり量が、画素
電極の前段ゲート配線よりの第2の角側の蓄積容量を形
成する画素電極と前段ゲートバス線との重なり距離に比
べ大きくなっている事を特徴とする液晶表示装置。
1. In an active matrix type liquid crystal display device in which a thin film transistor is used as a switching element and a storage capacitor is formed between a pixel electrode and a gate bus line in the preceding stage, an alignment film on a substrate on which the thin film transistor is formed is formed. The rubbing direction is formed obliquely from the first corner of the pixel electrode on the gate wiring side of the previous stage to the direction of the gate wiring of the next stage, and the pixel electrode forming the storage capacitance on the first corner side of the pixel electrode is formed. It is characterized in that the amount of overlap with the preceding gate bus line is larger than the overlapping distance between the pixel electrode that forms the storage capacitance on the second corner side of the preceding gate wiring of the pixel electrode and the preceding gate bus line. Liquid crystal display device.
【請求項2】 請求項1記載の液晶表示装置に於いて、
前記薄膜トランジスタが形成された基板側の配向膜上の
液晶分子のプレチルト角が7度以上では前記画素電極の
第1の角側での画素電極とゲートバス線との重なり距離
は10μm以上あり、また前記画素電極の第2の角近傍
での重なり距離が4μm以上である事を特徴とする液晶
表示装置。
2. The liquid crystal display device according to claim 1, wherein
When the pretilt angle of the liquid crystal molecules on the alignment film on the substrate side on which the thin film transistor is formed is 7 degrees or more, the overlapping distance between the pixel electrode and the gate bus line on the first corner side of the pixel electrode is 10 μm or more, A liquid crystal display device, wherein an overlapping distance in the vicinity of the second corner of the pixel electrode is 4 μm or more.
【請求項3】 請求項1記載の液晶表示装置に於いて、
前記薄膜トランジスタが形成された基板側の配向膜上の
液晶分子のプレチルト角が3度以上では前記画素電極の
第1の角側での画素電極とゲートバス線との重なり距離
は15μm以上あり、また前記画素電極の第2の角近傍
での重なり距離が5μm以上である事を特徴とする液晶
表示装置。
3. The liquid crystal display device according to claim 1, wherein
When the pretilt angle of the liquid crystal molecules on the alignment film on the substrate side on which the thin film transistor is formed is 3 degrees or more, the overlap distance between the pixel electrode and the gate bus line on the first corner side of the pixel electrode is 15 μm or more, A liquid crystal display device, wherein an overlapping distance in the vicinity of the second corner of the pixel electrode is 5 μm or more.
【請求項4】 薄膜トランジスタをスイッチング素子と
し、蓄積容量が画素電極と前段のゲートバス線間に形成
されているアクティブマトリックス型液晶表示装置に於
いて、前記薄膜トランジスタが形成された基板上の配向
膜のラビング方向が前段ゲートバス線側の第1の画素領
域と次段ゲート側の第2の画素領域で異なり、該第1の
画素領域でのラビング方向は、前段のゲート配線側の画
素電極の第1の角に向けた方向に斜めにされており、且
つ前記画素電極の前段ゲート配線よりの第2の角側の前
記蓄積容量を形成する画素電極と前段のゲートバス線と
の重なり距離が、画素電極の前記第1の角側の前記蓄積
容量を形成する画素電極と前段のゲートバス線との重な
り距離に比べ大きくなっている事を特徴とする液晶表示
装置。
4. An active matrix type liquid crystal display device in which a thin film transistor is used as a switching element and a storage capacitor is formed between a pixel electrode and a preceding gate bus line, wherein an alignment film on a substrate on which the thin film transistor is formed is formed. The rubbing direction is different between the first pixel region on the previous gate bus line side and the second pixel region on the next gate side, and the rubbing direction in the first pixel region is the same as that of the pixel electrode on the previous gate line side. And the overlap distance between the pixel electrode forming the storage capacitor on the second corner side of the pre-stage gate wiring of the pixel electrode and the pre-stage gate bus line is oblique in the direction toward the first corner, A liquid crystal display device, wherein the distance is greater than the overlap distance between a pixel electrode forming the storage capacitor on the first corner side of the pixel electrode and a preceding gate bus line.
【請求項5】 請求項4記載の液晶表示装置に於いて、
前記薄膜トランジスタが形成された基板側の配向膜上の
液晶分子のプレチルト角が7度以上では前記画素電極の
第1の角近傍での画素電極とゲートバス線との重なりは
距離は4μm以上あり、前記画素電極の第2の角近傍で
の重なり距離は5μm以上である事を特徴とする液晶表
示装置。
5. The liquid crystal display device according to claim 4, wherein
When the pretilt angle of the liquid crystal molecules on the alignment film on the substrate side on which the thin film transistor is formed is 7 degrees or more, the overlap between the pixel electrode and the gate bus line near the first angle of the pixel electrode is 4 μm or more, A liquid crystal display device, wherein an overlap distance of the pixel electrode near a second corner is 5 μm or more.
【請求項6】 請求項4記載の液晶表示装置に於いて、
前記薄膜トランジスタが形成された基板側の配向膜上の
液晶分子のプレチルト角が3度以上では前記画素電極の
第1の角近傍での画素電極とゲートバス線との重なりは
距離は5μm以上あり、前記画素電極の第2の角近傍で
の重なり距離は10μm以上である事を特徴とする液晶
表示装置。
6. The liquid crystal display device according to claim 4,
When the pretilt angle of the liquid crystal molecules on the alignment film on the substrate side on which the thin film transistor is formed is 3 degrees or more, the overlap between the pixel electrode and the gate bus line near the first angle of the pixel electrode is 5 μm or more, A liquid crystal display device, wherein an overlapping distance of the pixel electrode near the second corner is 10 μm or more.
JP7164356A 1995-06-29 1995-06-29 Liquid crystal display Expired - Lifetime JP2716004B2 (en)

Priority Applications (1)

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Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
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JPH0915642A true JPH0915642A (en) 1997-01-17
JP2716004B2 JP2716004B2 (en) 1998-02-18

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KR100294686B1 (en) * 1998-07-21 2001-07-12 구본준, 론 위라하디락사 Complex field type liquid crystal display device
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