JP2006184336A - Liquid crystal display element - Google Patents

Liquid crystal display element Download PDF

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JP2006184336A
JP2006184336A JP2004375020A JP2004375020A JP2006184336A JP 2006184336 A JP2006184336 A JP 2006184336A JP 2004375020 A JP2004375020 A JP 2004375020A JP 2004375020 A JP2004375020 A JP 2004375020A JP 2006184336 A JP2006184336 A JP 2006184336A
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liquid crystal
pixel
vertical alignment
substrate
pixel electrodes
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JP4645190B2 (en
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Minoru Yamaguchi
稔 山口
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Casio Computer Co Ltd
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<P>PROBLEM TO BE SOLVED: To provide a vertical aligned type active matrix liquid crystal display element, where liquid crystal molecules in respective pixels are stably aligned in the falling orientation by application of voltage and an image having satisfactory quality can be displayed. <P>SOLUTION: A plurality of pixel electrodes 3 are provided, by superposing one end edges thereof on side edge parts of a gate wiring 10 adjacent to the pixel electrodes 3, a first vertical alignment layer on an inner surface of a rear substrate, on which the plurality of pixel electrodes are provided, is subjected to rubbing treatment in a direction 1a from an end edge side opposite to the side adjacent to the gate wiring 10 of each pixel electrode 3 to acounter edge side and a second vertical alignment layer on an inner surface of a front substrate, on which a counter electrode is provided is subjected to rubbing treatment in a direction 2b that is reverse to the rubbing direction 1a of the first vertical alignment layer. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

この発明は、薄膜トランジスタ(以下、TFTと記す)をアクティブ素子とした垂直配向型のアクティブマトリックス液晶表示素子に関する。   The present invention relates to a vertical alignment type active matrix liquid crystal display element using a thin film transistor (hereinafter referred to as TFT) as an active element.

垂直配向型のアクティブマトリックス液晶表示素子は、予め定めた間隙を存して対向する一対の基板と、前記一対の基板の互いに対向する内面のうち、一方の基板の内面に設けられ、行方向及び列方向にマトリックス状に配列する複数の画素電極と、前記一方の基板の内面に前記複数の画素電極の一端縁にそれぞれ対応させて設けられ、対応する画素電極にそれぞれ接続された複数のTFTと、前記一方の基板の内面に各画素電極行の一側及び各画素電極列の一側にそれぞれ沿わせて設けられ、その行及び列の前記TFTにゲート信号及びデータ信号を供給する複数のゲート配線及びデータ配線と、他方の基板の内面に設けられ、前記複数の画素電極とそれぞれ対向する領域により複数の画素を形成する対向電極と、前記一対の基板の内面にそれぞれ前記電極を覆って設けられた第1と第2の垂直配向膜と、前記一対の基板間の間隙に封入された負の誘電異方性を有する液晶層とからなっている(特許文献1参照)。
特許第2565639号公報
A vertical alignment type active matrix liquid crystal display element is provided on the inner surface of one of a pair of substrates facing each other with a predetermined gap and the inner surfaces facing each other of the pair of substrates, A plurality of pixel electrodes arranged in a matrix in the column direction, a plurality of TFTs provided on the inner surface of the one substrate in correspondence with one end edges of the plurality of pixel electrodes, and connected to the corresponding pixel electrodes, respectively A plurality of gates provided on the inner surface of the one substrate along one side of each pixel electrode row and one side of each pixel electrode column, and supplying gate signals and data signals to the TFTs in the rows and columns, respectively. Wiring and data wiring, provided on the inner surface of the other substrate, forming a plurality of pixels by regions facing each of the plurality of pixel electrodes, and on the inner surfaces of the pair of substrates Each of the first and second vertical alignment films provided so as to cover the electrodes, and a liquid crystal layer having negative dielectric anisotropy sealed in a gap between the pair of substrates (patent) Reference 1).
Japanese Patent No. 2565639

垂直配向型の液晶表示素子は、複数の画素電極と対向電極とが互いに対向する領域からなる複数の画素毎に、前記電極間への書込み電圧の印加により液晶分子を垂直配向状態から倒れ配向させて画像を表示する。   In a vertical alignment type liquid crystal display element, liquid crystal molecules are tilted from a vertical alignment state by applying a write voltage between the electrodes for each of a plurality of pixels composed of regions where a plurality of pixel electrodes and a counter electrode face each other. To display the image.

しかし、従来の垂直配向型液晶表示素子は、各画素の書込み電圧の印加による液晶分子の倒れ配向が不安定で、良好な品質の表示が得られない。   However, in the conventional vertical alignment type liquid crystal display element, the tilted alignment of liquid crystal molecules due to the application of the write voltage of each pixel is unstable, and a good quality display cannot be obtained.

なお、液晶表示素子は、高精細化のために、複数の画素電極を細長形状に形成し、画素密度を高くすることが望まれているが、従来の垂直配向型液晶表示素子は、画素電極を細長形状に形成すると、各画素の書込み電圧の印加による液晶分子の倒れ配向がさらに不安定になり、表示品質がさらに低下する。   In addition, for liquid crystal display elements, it is desired to form a plurality of pixel electrodes in an elongated shape and increase the pixel density for high definition, but conventional vertical alignment type liquid crystal display elements are pixel electrodes. Is formed in an elongated shape, the tilted orientation of the liquid crystal molecules due to the application of the write voltage of each pixel becomes more unstable, and the display quality further deteriorates.

この発明は、各画素の液晶分子を書込み電圧の印加により安定に倒れ配向させ、良好な品質の画像を表示することができる垂直配向型のアクティブマトリックス液晶表示素子を提供することを目的としたものである。   An object of the present invention is to provide a vertical alignment type active matrix liquid crystal display element capable of displaying a good quality image by stably tilting and aligning liquid crystal molecules of each pixel by applying a writing voltage. It is.

この発明の液晶表示素子は、予め定めた間隙を存して対向する一対の基板と、前記一対の基板の互いに対向する内面のうち、一方の基板の内面に設けられ、行方向及び列方向にマトリックス状に配列する複数の画素電極と、前記一方の基板の内面に前記複数の画素電極の一端縁にそれぞれ対応させて設けられ、対応する画素電極にそれぞれ接続された複数のTFTと、前記一方の基板の内面に各画素電極行の一側及び各画素電極列の一側にそれぞれ沿わせて設けられ、その行及び列の前記TFTにゲート信号及びデータ信号を供給する複数のゲート配線及びデータ配線と、他方の基板の内面に設けられ、前記複数の画素電極とそれぞれ対向する領域により複数の画素を形成する対向電極と、前記一対の基板の内面にそれぞれ前記電極を覆って設けられた第1と第2の垂直配向膜と、前記一対の基板間の間隙に封入された負の誘電異方性を有する液晶層とからなり、前記複数の画素電極はそれぞれ、その一端縁を前記ゲート配線の前記画素電極に隣接する側縁部に重ねて設けられ、前記複数の画素電極が設けられた前記一方の基板の内面の第1の垂直配向膜は、前記画素電極の前記ゲート配線に隣接する側とは反対側の端縁から前記ゲート配線に隣接する端縁に向かう方向にラビング処理され、前記対向電極が設けられた前記他方の基板の内面の第2の垂直配向膜は、前記第1の垂直配向膜のラビング方向とは逆方向にラビング処理されていることを特徴とする。   The liquid crystal display element of the present invention is provided on the inner surface of one of the pair of substrates facing each other with a predetermined gap and the inner surfaces facing each other of the pair of substrates in the row direction and the column direction. A plurality of pixel electrodes arranged in a matrix, a plurality of TFTs provided on the inner surface of the one substrate in correspondence with one end edges of the plurality of pixel electrodes, and connected to the corresponding pixel electrodes, respectively, A plurality of gate wirings and data provided on the inner surface of the substrate along one side of each pixel electrode row and one side of each pixel electrode column and supplying gate signals and data signals to the TFTs in the rows and columns, respectively. A wiring, a counter electrode provided on an inner surface of the other substrate and forming a plurality of pixels by regions facing the plurality of pixel electrodes, and an inner surface of the pair of substrates covering the electrodes Each of the plurality of pixel electrodes includes one end edge of the first and second vertical alignment films and a liquid crystal layer having negative dielectric anisotropy sealed in a gap between the pair of substrates. On the side edge adjacent to the pixel electrode of the gate wiring, and the first vertical alignment film on the inner surface of the one substrate on which the plurality of pixel electrodes are provided is the gate of the pixel electrode. The second vertical alignment film on the inner surface of the other substrate on which the counter electrode is provided is rubbed in a direction from the edge opposite to the side adjacent to the wiring toward the edge adjacent to the gate wiring. The first vertical alignment film is rubbed in a direction opposite to the rubbing direction.

この液晶表示素子において、前記複数の画素電極は、液晶表示素子の高精細化のために細長形状に形成するのが望ましく、その場合は、前記画素電極の長手方向の一端縁を前記ゲート配線の側縁部に重ねて設ければよい。   In this liquid crystal display element, the plurality of pixel electrodes are preferably formed in an elongated shape for high definition of the liquid crystal display element. In this case, one end edge in the longitudinal direction of the pixel electrode is formed on the gate wiring. What is necessary is just to provide it by overlapping on a side edge part.

この発明の液晶表示素子は、複数の画素電極をそれぞれ、その一端縁をゲート配線の前記画素電極に隣接する側縁部に重ねて設け、前記複数の画素電極が設けられた前記一方の基板の内面の第1の垂直配向膜を、前記画素電極の前記ゲート配線に隣接する側とは反対側の端縁から前記ゲート配線に隣接する端縁に向かう方向にラビング処理し、前記対向電極が設けられた前記他方の基板の内面の第2の垂直配向膜を、前記第1の垂直配向膜のラビング方向とは逆方向にラビング処理しているため、各画素の液晶分子が、前記画素電極と対向電極との間への書込み電圧の印加により、前記ゲート配線に対応する部分の前記ゲート配線と対向電極との間の電界による液晶分子の倒れ配向方向に誘引され、前記垂直配向膜のラビング方向により規定される方向に倒れ配向する。   In the liquid crystal display element of the present invention, each of the plurality of pixel electrodes is provided such that one end edge thereof is overlapped with a side edge adjacent to the pixel electrode of the gate wiring, and the one substrate on which the plurality of pixel electrodes are provided is provided. The counter electrode is provided by rubbing the first vertical alignment film on the inner surface in a direction from the edge of the pixel electrode opposite to the side adjacent to the gate wiring to the edge adjacent to the gate wiring. Since the second vertical alignment film on the inner surface of the other substrate is rubbed in the direction opposite to the rubbing direction of the first vertical alignment film, the liquid crystal molecules of each pixel are connected to the pixel electrode. By applying a write voltage to the counter electrode, a portion corresponding to the gate line is attracted to a tilt alignment direction of liquid crystal molecules due to an electric field between the gate line and the counter electrode, and a rubbing direction of the vertical alignment film Stipulated by Oriented fallen in the direction.

そのため、この液晶表示素子によれば、各画素の液晶分子を前記書込み電圧の印加により安定に倒れ配向させ、良好な品質の画像を表示することができる。   Therefore, according to this liquid crystal display element, the liquid crystal molecules of each pixel can be stably tilted and oriented by applying the write voltage, and a good quality image can be displayed.

この液晶表示素子において、前記複数の画素電極は、液晶表示素子の高精細化のために細長形状に形成するのが望ましく、その場合は、前記画素電極の長手方向の一端縁を前記ゲート配線の側縁部に重ねて設けることにより、各画素の液晶分子を前記書込み電圧の印加により安定に倒れ配向させ、良好な品質の画像を表示することができる。   In this liquid crystal display element, the plurality of pixel electrodes are preferably formed in an elongated shape for high definition of the liquid crystal display element. In this case, one end edge in the longitudinal direction of the pixel electrode is formed on the gate wiring. By overlapping the side edge portions, the liquid crystal molecules of each pixel can be stably tilted and oriented by applying the write voltage, and a good quality image can be displayed.

図1〜図5はこの発明の一実施例を示しており、図1は液晶表示素子の一方の基板の一部分の平面図、図2及び図3は図1のII−II線及びIII−III線に沿う液晶表示素子の断面図である。   1 to 5 show one embodiment of the present invention, FIG. 1 is a plan view of a part of one substrate of a liquid crystal display element, and FIGS. 2 and 3 are II-II and III-III lines in FIG. It is sectional drawing of the liquid crystal display element which follows a line.

この液晶表示素子は、TFTをアクティブ素子とした垂直配向型のアクティブマトリックス液晶表示素子であり、図1〜図3に示したように、予め定めた間隙を存して対向する一対の透明基板1,2と、これらの基板1,2の互いに対向する内面のうち、一方の基板、例えば表示の観察側とは反対側の基板(以下、後基板という)1の内面に設けられ、行方向及び列方向にマトリックス状に配列する複数の透明な画素電極3と、前記後基板1の内面に前記複数の画素電極3の一端縁にそれぞれ対応させて設けられ、対応する画素電極3にそれぞれ接続された複数のTFT4と、前記後基板1の内面に各画素電極行の一側及び各画素電極列の一側にそれぞれ沿わせて設けられ、その行及び列のTFT4にゲート信号及びデータ信号を供給する複数のゲート配線10及びデータ配線11と、他方の基板、つまり観察側の基板(以下、前基板という)2の内面に設けられ、前記複数の画素電極3とそれぞれ対向する領域により複数の画素を形成する一枚膜状の透明な対向電極15と、前記一対の基板1,2の内面にそれぞれ設けられた第1及び第2の垂直配向膜14,18と、前記一対の基板1,2間の間隙に封入された負の誘電異方性を有する液晶層19とからなっている。   This liquid crystal display element is a vertical alignment type active matrix liquid crystal display element using TFT as an active element. As shown in FIGS. 1 to 3, a pair of transparent substrates 1 facing each other with a predetermined gap therebetween. , 2 and the inner surfaces of these substrates 1 and 2 facing each other, for example, on the inner surface of one substrate, for example, the substrate 1 on the opposite side of the display viewing side (hereinafter referred to as a rear substrate), A plurality of transparent pixel electrodes 3 arranged in a matrix in the column direction, and provided on the inner surface of the rear substrate 1 so as to correspond to one end edges of the plurality of pixel electrodes 3, and connected to the corresponding pixel electrodes 3, respectively. A plurality of TFTs 4 are provided on the inner surface of the rear substrate 1 along one side of each pixel electrode row and one side of each pixel electrode column, and supply gate signals and data signals to the TFTs 4 in the rows and columns. Duplicate A plurality of pixels are formed by the gate wiring 10 and the data wiring 11 and the inner surface of the other substrate, that is, the substrate on the observation side (hereinafter referred to as the front substrate) 2 and facing the plurality of pixel electrodes 3, respectively. A single film-like transparent counter electrode 15, first and second vertical alignment films 14, 18 provided on the inner surfaces of the pair of substrates 1, 2, and the pair of substrates 1, 2, respectively. The liquid crystal layer 19 has negative dielectric anisotropy enclosed in a gap.

前記複数のTFT4は、前記後基板1の基板面に形成されたゲート電極5と、前記ゲート電極5を覆って前記画素電極3の配列領域の全域に形成された透明なゲート絶縁膜6と、前記ゲート絶縁膜6の上に前記ゲート電極5と対向させて形成されたi型半導体膜7と、このi型半導体膜7の一側部と他側部の上に図示しないn型半導体膜を介して形成されたドレイン電極8及びソース電極9とからなっている。   The plurality of TFTs 4 include a gate electrode 5 formed on the substrate surface of the rear substrate 1, a transparent gate insulating film 6 that covers the gate electrode 5 and is formed in the entire array region of the pixel electrode 3, An i-type semiconductor film 7 formed on the gate insulating film 6 so as to face the gate electrode 5, and an n-type semiconductor film (not shown) on one side and the other side of the i-type semiconductor film 7. A drain electrode 8 and a source electrode 9 are formed.

なお、前記ゲート配線10は、前記後基板1の基板面に前記TFT4のゲート電極5と一体に形成されており、前記データ配線11は、前記ゲート絶縁膜6の上に前記TFT4のドレイン電極8と一体に形成されている。   The gate wiring 10 is formed integrally with the gate electrode 5 of the TFT 4 on the substrate surface of the rear substrate 1, and the data wiring 11 is formed on the gate insulating film 6 and on the drain electrode 8 of the TFT 4. And is integrally formed.

そして、前記複数の画素電極3は、前記ゲート絶縁膜6の上に、その一端縁を前記ゲート配線10の前記画素電極3に隣接する側縁部に重ねて設けられており、前記TFT4のソース電極9は、そのTFT4に対応する画素電極3の端縁の一側部に接続されている。   The plurality of pixel electrodes 3 are provided on the gate insulating film 6 so that one end edge thereof is overlapped with a side edge portion adjacent to the pixel electrode 3 of the gate wiring 10. The electrode 9 is connected to one side of the edge of the pixel electrode 3 corresponding to the TFT 4.

この実施例では、画素密度を高くして液晶表示素子を高精細化するために、前記複数の画素電極3を、前記ゲート配線10に沿う方向の幅を通常の画素電極幅よりも狭くした細長形状に形成し、その長手方向の一端縁を前記ゲート配線10の側縁部に重ねて設けている。   In this embodiment, in order to increase the pixel density and increase the definition of the liquid crystal display element, the plurality of pixel electrodes 3 are elongated so that the width along the gate wiring 10 is narrower than the normal pixel electrode width. The one end edge in the longitudinal direction is provided so as to overlap the side edge portion of the gate wiring 10.

さらに、前記後基板1の基板面には、各行の画素電極3にそれぞれ対応させて、前記画素電極3との間に前記ゲート絶縁膜6を誘電体層とする補償容量を形成する補償容量電極13が設けられている。   Further, a compensation capacitor electrode is formed on the substrate surface of the rear substrate 1 so as to correspond to the pixel electrode 3 in each row and to form a compensation capacitor having the gate insulating film 6 as a dielectric layer between the pixel electrode 3 and the substrate electrode. 13 is provided.

なお、この実施例では、補償容量電極13を、各行の画素電極3のTFT隣接側とは反対側の端縁部対応させて設けているが、この補償容量電極13は、前記画素電極3のTFT隣接側とは反対側の端縁部及び両側縁部に対応させて設けてもよい。   In this embodiment, the compensation capacitor electrode 13 is provided so as to correspond to the edge of the pixel electrode 3 of each row on the side opposite to the TFT adjacent side. However, the compensation capacitor electrode 13 corresponds to the pixel electrode 3. You may provide corresponding to the edge part on the opposite side to a TFT adjacent side, and a both-sides edge part.

そして、前記各行の画素電極3にそれぞれ対応する補償容量電極13は、前記複数の画素電極3の配列領域の外側の一端または両端に前記データ配線12と平行に設けられた図示しない容量電極接続配線に共通接続されている。   The compensation capacitor electrodes 13 respectively corresponding to the pixel electrodes 3 in each row are capacitor electrode connection wires (not shown) provided in parallel with the data wires 12 at one end or both ends outside the array region of the plurality of pixel electrodes 3. Commonly connected to

また、前記後基板1の内面には、前記複数の画素電極3に対応する部分を除いて、前記複数のTFT4及びデータ配線11を覆うオーバーコート絶縁膜12が設けられており、その上に、前記複数の画素電極3を覆って第1の垂直配向膜14が形成されている。   Further, an overcoat insulating film 12 is provided on the inner surface of the rear substrate 1 so as to cover the plurality of TFTs 4 and the data lines 11 except for portions corresponding to the plurality of pixel electrodes 3. A first vertical alignment film 14 is formed so as to cover the plurality of pixel electrodes 3.

一方、前記前基板2の内面には、前記後基板1の内面に設けられた複数の画素電極3にそれぞれ対応する複数の画素の間の領域に対向する格子膜状のブラックマスク16と、前記複数の画素にそれぞれ対応する赤、緑、青の3色のカラーフィルタ17R,17G,17Bが設けられており、前記カラーフィルタ17R,17G,17Bの上に前記対向電極15が形成され、その上に第2の垂直配向膜18が形成されている。   On the other hand, on the inner surface of the front substrate 2, a black mask 16 in the form of a lattice film facing regions between a plurality of pixels respectively corresponding to the plurality of pixel electrodes 3 provided on the inner surface of the rear substrate 1, and Red, green, and blue color filters 17R, 17G, and 17B corresponding to a plurality of pixels are provided, and the counter electrode 15 is formed on the color filters 17R, 17G, and 17B. In addition, a second vertical alignment film 18 is formed.

そして、前記後基板1の内面の第1の垂直配向膜14は、前記画素電極3の前記ゲート配線10に隣接する側とは反対側の端縁から前記ゲート配線10に隣接する端縁に向かう方向にラビング処理され、前記前基板2の内面の第2の垂直配向膜18は、前記第1の垂直配向膜14のラビング方向とは逆方向にラビング処理されている。図1及び図2において、矢印1aは後基板1の第1の垂直配向膜14のラビング方向、矢印2aは前基板2の第2の垂直配向膜18のラビング方向を示している。   The first vertical alignment film 14 on the inner surface of the rear substrate 1 is directed from the edge of the pixel electrode 3 opposite to the side adjacent to the gate wiring 10 to the edge adjacent to the gate wiring 10. The second vertical alignment film 18 on the inner surface of the front substrate 2 is rubbed in the direction opposite to the rubbing direction of the first vertical alignment film 14. 1 and 2, the arrow 1 a indicates the rubbing direction of the first vertical alignment film 14 of the rear substrate 1, and the arrow 2 a indicates the rubbing direction of the second vertical alignment film 18 of the front substrate 2.

前記後基板1と前基板2は、前記複数の画素電極3の配列領域を囲む図示しない枠状のシール材を介して接合されている。   The rear substrate 1 and the front substrate 2 are bonded together via a frame-shaped sealing material (not shown) that surrounds the array region of the plurality of pixel electrodes 3.

また、前記後基板1は、図示しないが、その行方向の一端と列方向の一端とにそれぞれ、前基板2の外方に突出する張出部を有しており、その行方向の張出部に複数のゲート側ドライバ接続端子が配列形成され、列方向の張出部に複数のデータ側ドライバ接続端子が配列形成されている。   Further, although not shown, the rear substrate 1 has a protruding portion protruding outward from the front substrate 2 at one end in the row direction and one end in the column direction. A plurality of gate-side driver connection terminals are formed in an array at a portion, and a plurality of data-side driver connection terminals are formed at an extension in the column direction.

そして、前記複数のゲート配線10は、前記行方向の張出部に導出されて前記複数のゲート側ドライバ接続端子にそれぞれ接続され、前記複数のデータ配線11は、前記列方向の張出部に導出されて前記複数のデータ側ドライバ接続端子にそれぞれ接続されており、前記各行の画素電極3にそれぞれ対応する補償容量電極13が共通接続された図示しない容量電極接続配線は、前記行方向と列方向の張出部の一方または両方に導出され、その張出部の複数のドライバ接続端子のうちの基準電位端子に接続されている。   The plurality of gate wirings 10 are led out to the row extending portions and connected to the plurality of gate side driver connection terminals, respectively, and the plurality of data wirings 11 are connected to the column extending portions. A capacitor electrode connection wiring (not shown) that is derived and connected to each of the plurality of data-side driver connection terminals and to which the compensation capacitor electrodes 13 corresponding to the pixel electrodes 3 in each row are connected in common is provided in the row direction and the column. It is led out to one or both of the protruding portions in the direction, and is connected to a reference potential terminal among a plurality of driver connection terminals of the protruding portion.

また、前記液晶層19は、前記後基板1と前基板2の間の前記シール材で囲まれた領域に封入されており、この液晶層19の液晶分子19aは、両基板1,2の内面にそれぞれ設けられた垂直配向膜14,18の垂直配向性により、基板1,2面に対して前記垂直配向膜14,18のラビング方向に僅かにチルトした状態で実質的に垂直に配向している。   The liquid crystal layer 19 is enclosed in a region surrounded by the sealing material between the rear substrate 1 and the front substrate 2, and the liquid crystal molecules 19 a of the liquid crystal layer 19 are formed on the inner surfaces of both substrates 1 and 2. Due to the vertical alignment properties of the vertical alignment films 14 and 18 provided respectively on the first and second substrates, the vertical alignment films 14 and 18 are aligned substantially perpendicularly to the surfaces of the substrates 1 and 2 while being slightly tilted in the rubbing direction of the vertical alignment films 14 and 18. Yes.

また、前記後基板1と前基板2の外面にはそれぞれ、偏光板20,21がその透過軸を予め定めた方向に向けて配置されている。なお、この実施例では、前記偏光板20,21をそれぞれの透過軸を実質的に互いに直交させて配置し、液晶表示素子にノーマリーブラックモードの表示を行なわせるようにしている。   Further, polarizing plates 20 and 21 are respectively disposed on the outer surfaces of the rear substrate 1 and the front substrate 2 with their transmission axes directed in a predetermined direction. In this embodiment, the polarizing plates 20 and 21 are arranged so that their transmission axes are substantially perpendicular to each other so that the liquid crystal display element performs display in a normally black mode.

この液晶表示素子は、複数の画素毎に、前記画素電極3と対向電極15との間への書込み電圧の印加により液晶分子19aを垂直配向状態から倒れ配向させて画像を表示するものであり、前記液晶分子19aは、前記書込み電圧が印加されない画素間領域では実質的に垂直に配向しており、各画素毎に、前記書込み電圧の電圧値に応じて倒れ配向する。   This liquid crystal display element displays an image by aligning the liquid crystal molecules 19a from the vertical alignment state by applying a write voltage between the pixel electrode 3 and the counter electrode 15 for each of a plurality of pixels, The liquid crystal molecules 19a are aligned substantially vertically in the inter-pixel region where the write voltage is not applied, and are tilted and aligned for each pixel according to the voltage value of the write voltage.

この液晶表示素子は、複数の画素電極3をそれぞれ、その一端縁をゲート配線10の前記画素電極3に隣接する側縁部に重ねて設け、複数の画素電極3が設けられた後基板1の内面の第1の垂直配向膜14を、前記画素電極3のゲート配線10に隣接する側とは反対側の端縁から前記ゲート配線10に隣接する端縁に向かう方向にラビング処理し、対向電極15が設けられた前基板2の内面の第2の垂直配向膜18を、前記第1の垂直配向膜14のラビング方向とは逆方向にラビング処理しているため、各画素の液晶分子19aが、前記画素電極3と対向電極15との間への書込み電圧の印加により、前記ゲート配線10に対応する部分の前記ゲート配線10と対向電極15との間の電界による液晶分子19aの倒れ配向方向に誘引され、前記垂直配向膜14,19のラビング方向1a,2aにより規定される方向に倒れ配向する。   In this liquid crystal display element, a plurality of pixel electrodes 3 are provided so that one end edge thereof is overlapped with a side edge adjacent to the pixel electrode 3 of the gate wiring 10, and the substrate 1 is provided after the plurality of pixel electrodes 3 are provided. The first vertical alignment film 14 on the inner surface is rubbed in the direction from the edge of the pixel electrode 3 opposite to the side adjacent to the gate wiring 10 toward the edge adjacent to the gate wiring 10, Since the second vertical alignment film 18 on the inner surface of the front substrate 2 provided with 15 is rubbed in a direction opposite to the rubbing direction of the first vertical alignment film 14, the liquid crystal molecules 19a of each pixel are By applying a write voltage between the pixel electrode 3 and the counter electrode 15, the direction of the tilt alignment of the liquid crystal molecules 19 a due to the electric field between the gate line 10 and the counter electrode 15 in a portion corresponding to the gate line 10. Attracted to before Oriented collapsed direction defined rubbing direction 1a of the vertical alignment film 14 and 19, by 2a.

図4及び図5は、上記実施例の液晶表示素子の1つの画素の書込み電圧印加時の液晶分子配向状態を模式的に示す平面図及び断面図、図6及び図7は、画素電極3をゲート配線10から離間させて設けた比較素子の1つの画素の書込み電圧印加時の液晶分子配向状態を模式的に示す平面図及び断面図である。   4 and 5 are a plan view and a cross-sectional view schematically showing a liquid crystal molecular alignment state when a write voltage is applied to one pixel of the liquid crystal display element of the above embodiment, and FIGS. 6 and 7 show the pixel electrode 3. FIG. 6 is a plan view and a cross-sectional view schematically showing a liquid crystal molecule alignment state when a write voltage is applied to one pixel of a comparison element provided apart from the gate wiring.

まず、前記比較素子の書込み電圧の印加による液晶分子19aの倒れ配向状態を説明すると、この比較素子では、図6及び図7のように、各画素の液晶分子19aが、書込み電圧の印加により、画素の周縁部から画素電極3が設けられた後基板の第1の垂直配向膜14のラビング方向1aに倒れ込むように配向するが、前記画素のゲート配線10に隣接する端部側の液晶分子19aは、前記ゲート配線10と画素電極3の端縁との間に発生するゲート信号に応じた強い横電界を受けてその横電界の方向、つまり前記第1の垂直配向膜14のラビング方向1aとは逆方向に倒れ込むように配向する。   First, the tilted alignment state of the liquid crystal molecules 19a by the application of the write voltage of the comparison element will be described. In this comparison element, as shown in FIGS. 6 and 7, the liquid crystal molecules 19a of each pixel are applied by the application of the write voltage. After the pixel electrode 3 is provided from the peripheral edge of the pixel, the first vertical alignment film 14 of the substrate is aligned so as to fall in the rubbing direction 1a, but the liquid crystal molecules 19a on the end side adjacent to the gate wiring 10 of the pixel are arranged. Receives a strong lateral electric field corresponding to a gate signal generated between the gate wiring 10 and the edge of the pixel electrode 3, and the direction of the lateral electric field, that is, the rubbing direction 1a of the first vertical alignment film 14 Are oriented so as to fall in the opposite direction.

そのため、この比較素子は、各画素の書込み電圧の印加による液晶分子19aの倒れ配向が不安定で、良好な品質の表示が得られず、特に、液晶表示素子を高精細化するために画素電極3を細長形状に形成すると、各画素の書込み電圧の印加による液晶分子19aの倒れ配向がさらに不安定になり、表示品質がさらに低下する。   Therefore, this comparison element is unstable in the tilted orientation of the liquid crystal molecules 19a due to the application of the write voltage of each pixel, and cannot display a good quality display. In particular, in order to increase the definition of the liquid crystal display element, the pixel electrode When 3 is formed in an elongated shape, the tilted orientation of the liquid crystal molecules 19a due to the application of the write voltage to each pixel becomes more unstable, and the display quality further deteriorates.

それに対し、上記実施例の液晶表示素子は、画素電極3の一端縁をゲート配線10の前記画素電極3に隣接する側縁部に重ねているため、前記ゲート配線10と画素電極3の端縁との間に前記横電界が発生することは無い。   On the other hand, in the liquid crystal display element of the above embodiment, the one end edge of the pixel electrode 3 is overlapped with the side edge portion adjacent to the pixel electrode 3 of the gate line 10, so that the edge of the gate line 10 and the pixel electrode 3 is overlapped. The horizontal electric field does not occur between the two.

一方、前記ゲート配線10に対応する部分の液晶分子19aは、前記ゲート配線10と対向電極15との間に発生するゲート信号に応じた−15V程度の強い電界により、倒れるように配向する。   On the other hand, the liquid crystal molecules 19a corresponding to the gate wiring 10 are aligned so as to be tilted by a strong electric field of about −15 V corresponding to the gate signal generated between the gate wiring 10 and the counter electrode 15.

また、上記実施例の液晶表示素子は、画素電極3が設けられた後基板1の内面の第1の垂直配向膜14を、前記画素電極3のゲート配線10に隣接する側とは反対側の端縁から前記ゲート配線10に隣接する端縁に向かう方向にラビング処理しているため、前記ゲート配線10に対応する部分のゲート配線10と対向電極15との間に発生する電界による液晶分子19aの倒れ込み方向と前記画素電極3上の前記ゲート配線に重なる縁部における液晶分子19aの倒れ込み方向は一致する。   Further, in the liquid crystal display element of the above embodiment, the first vertical alignment film 14 on the inner surface of the substrate 1 after the pixel electrode 3 is provided is opposite to the side of the pixel electrode 3 adjacent to the gate wiring 10. Since the rubbing process is performed in the direction from the edge toward the edge adjacent to the gate wiring 10, the liquid crystal molecules 19 a due to the electric field generated between the gate wiring 10 and the counter electrode 15 corresponding to the gate wiring 10. The tilt direction of the liquid crystal molecules 19a coincides with the tilt direction of the liquid crystal molecules 19a at the edge overlapping the gate wiring on the pixel electrode 3.

そのため、前記画素の液晶分子19aは、図4及び図5のように、書込み電圧の印加により、ゲート配線10に対応する部分の前記ゲート配線10と対向電極15との間の電界による液晶分子19aの倒れ配向方向に誘引され、画素の全域にわたって、前記第1の垂直配向膜14のラビング方向1aに倒れ込むように倒れ配向する。   Therefore, as shown in FIGS. 4 and 5, the liquid crystal molecules 19 a of the pixel are liquid crystal molecules 19 a due to an electric field between the gate wiring 10 and the counter electrode 15 in a portion corresponding to the gate wiring 10 by applying a write voltage. The tilted orientation direction of the first vertical alignment film 14 is induced to fall in the rubbing direction 1a over the entire area of the pixel.

したがって、この液晶表示素子によれば、各画素の液晶分子19aを前記書込み電圧の印加により安定に倒れ配向させ、良好な品質の画像を表示することができる。   Therefore, according to this liquid crystal display element, the liquid crystal molecules 19a of each pixel can be stably tilted and oriented by applying the write voltage, and an image of good quality can be displayed.

また、上記実施例の液晶表示素子は、複数の画素電極3を、液晶表示素子の高精細化のために細長形状に形成しているが、前記画素電極3の長手方向の一端縁をゲート配線10の側縁部に重ねて設け、複数の画素電極3が設けられた後基板1の内面の第1の垂直配向膜14を、前記画素電極3の長手方向に沿わせて、前記画素電極3のゲート配線10に隣接する側とは反対側の端縁から前記ゲート配線10に隣接する端縁に向かう方向にラビング処理し、対向電極15が設けられた前基板2の内面の第2の垂直配向膜18を、前記第1の垂直配向膜14のラビング方向とは逆方向にラビング処理しているため、画素電極3が細長形状であっても、各画素の液晶分子を前記書込み電圧の印加により安定に倒れ配向させ、良好な品質の画像を表示することができる。   In the liquid crystal display element of the above embodiment, a plurality of pixel electrodes 3 are formed in an elongated shape for high definition of the liquid crystal display element. One end edge in the longitudinal direction of the pixel electrode 3 is connected to a gate wiring. The first vertical alignment film 14 on the inner surface of the substrate 1 is provided along the longitudinal direction of the pixel electrode 3 so as to overlap the side edge portion of the pixel electrode 3 and the plurality of pixel electrodes 3 are provided. A rubbing process is performed in the direction from the edge opposite to the side adjacent to the gate wiring 10 toward the edge adjacent to the gate wiring 10, and the second vertical surface of the inner surface of the front substrate 2 provided with the counter electrode 15 is provided. Since the alignment film 18 is rubbed in the direction opposite to the rubbing direction of the first vertical alignment film 14, even if the pixel electrode 3 is elongated, the liquid crystal molecules of each pixel are applied with the write voltage. To stably tilt and display images of good quality Rukoto can.

この発明の一実施例を示す液晶表示素子の一方の基板の一部分の平面図。The top view of a part of one board | substrate of the liquid crystal display element which shows one Example of this invention. 図1のII−II線に沿う液晶表示素子の断面図。Sectional drawing of the liquid crystal display element which follows the II-II line | wire of FIG. 図1のIII−III線に沿う液晶表示素子の断面図。Sectional drawing of the liquid crystal display element which follows the III-III line | wire of FIG. 前記液晶表示素子の1つの画素の書込み電圧印加時の液晶分子配向状態を模式的に示す平面図。The top view which shows typically the liquid crystal molecule orientation state at the time of the write-in voltage application of one pixel of the said liquid crystal display element. 前記液晶表示素子の1つの画素の書込み電圧印加時の液晶分子配向状態を模式的に示す断面図。FIG. 3 is a cross-sectional view schematically showing a liquid crystal molecule alignment state when a write voltage is applied to one pixel of the liquid crystal display element. 画素電極をゲート配線から離間させて設けた比較素子の1つの画素の書込み電圧印加時の液晶分子配向状態を模式的に示す平面図。及び断面図である。The top view which shows typically the liquid crystal molecule orientation state at the time of the write-in voltage application of one pixel of the comparison element provided with the pixel electrode spaced apart from the gate wiring. FIG. 前記比較素子の1つの画素の書込み電圧印加時の液晶分子配向状態を模式的に示す断面図。FIG. 3 is a cross-sectional view schematically showing a liquid crystal molecule alignment state when a write voltage is applied to one pixel of the comparison element.

符号の説明Explanation of symbols

1,2…基板、3…画素電極、4…TFT、10…ゲート配線、11…データ配線、13…補償容量電極、14…垂直配向膜、15…対向電極、16…ブラックマスク、17R,17G,17B…カラーフィルタ、18…垂直配向膜、19…液晶層、19a…液晶分子、20,21…偏光板。   DESCRIPTION OF SYMBOLS 1, 2 ... Substrate, 3 ... Pixel electrode, 4 ... TFT, 10 ... Gate wiring, 11 ... Data wiring, 13 ... Compensation capacity electrode, 14 ... Vertical alignment film, 15 ... Counter electrode, 16 ... Black mask, 17R, 17G , 17B ... color filter, 18 ... vertical alignment film, 19 ... liquid crystal layer, 19a ... liquid crystal molecule, 20, 21 ... polarizing plate.

Claims (2)

予め定めた間隙を存して対向する一対の基板と、前記一対の基板の互いに対向する内面のうち、一方の基板の内面に設けられ、行方向及び列方向にマトリックス状に配列する複数の画素電極と、前記一方の基板の内面に前記複数の画素電極の一端縁にそれぞれ対応させて設けられ、対応する画素電極にそれぞれ接続された複数の薄膜トランジスタと、前記一方の基板の内面に各画素電極行の一側及び各画素電極列の一側にそれぞれ沿わせて設けられ、その行及び列の前記薄膜トランジスタにゲート信号及びデータ信号を供給する複数のゲート配線及びデータ配線と、他方の基板の内面に設けられ、前記複数の画素電極とそれぞれ対向する領域により複数の画素を形成する対向電極と、前記一対の基板の内面にそれぞれ前記電極を覆って設けられた第1と第2の垂直配向膜と、前記一対の基板間の間隙に封入された負の誘電異方性を有する液晶層とからなり、
前記複数の画素電極はそれぞれ、その一端縁を前記ゲート配線の前記画素電極に隣接する側縁部に重ねて設けられ、
前記複数の画素電極が設けられた前記一方の基板の内面の第1の垂直配向膜は、前記画素電極の前記ゲート配線に隣接する側とは反対側の端縁から前記ゲート配線に隣接する端縁に向かう方向にラビング処理され、前記対向電極が設けられた前記他方の基板の内面の第2の垂直配向膜は、前記第1の垂直配向膜のラビング方向とは逆方向にラビング処理されていることを特徴とする液晶表示素子。
A plurality of pixels provided on the inner surface of one of the pair of substrates facing each other with a predetermined gap and the inner surfaces of the pair of substrates facing each other, arranged in a matrix in the row and column directions An electrode, a plurality of thin film transistors provided on the inner surface of the one substrate so as to correspond to one end edges of the plurality of pixel electrodes, and respectively connected to the corresponding pixel electrode, and each pixel electrode on the inner surface of the one substrate A plurality of gate wirings and data wirings that are provided along one side of the row and one side of each pixel electrode column and supply gate signals and data signals to the thin film transistors in the rows and columns, and an inner surface of the other substrate A counter electrode that forms a plurality of pixels by regions facing the pixel electrodes, and an inner surface of the pair of substrates that covers the electrodes. Consists of a liquid crystal layer having first and the second vertical alignment film, a negative dielectric anisotropy is sealed in a gap between the pair of substrates,
Each of the plurality of pixel electrodes is provided with one end edge thereof overlapped with a side edge portion adjacent to the pixel electrode of the gate wiring,
The first vertical alignment film on the inner surface of the one substrate on which the plurality of pixel electrodes are provided has an edge adjacent to the gate wiring from an edge opposite to the side adjacent to the gate wiring of the pixel electrode. The second vertical alignment film on the inner surface of the other substrate provided with the counter electrode is rubbed in a direction toward the edge, and is rubbed in a direction opposite to the rubbing direction of the first vertical alignment film. A liquid crystal display element characterized by comprising:
複数の画素電極は、細長形状に形成されており、その長手方向の一端縁をゲート配線の側縁部に重ねて設けられていることを特徴とする請求項1に記載の液晶表示素子。   The liquid crystal display element according to claim 1, wherein the plurality of pixel electrodes are formed in an elongated shape, and one end edge in the longitudinal direction thereof is provided so as to overlap a side edge portion of the gate wiring.
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Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2565639B2 (en) * 1992-04-30 1996-12-18 インターナショナル・ビジネス・マシーンズ・コーポレイション Liquid crystal display
JPH0915642A (en) * 1995-06-29 1997-01-17 Nec Corp Liquid crystal display device
JPH09127554A (en) * 1995-10-31 1997-05-16 Sharp Corp Transmission type liquid crystal display device
JP2002229029A (en) * 2000-11-28 2002-08-14 Sharp Corp Liquid crystal display and method for manufacturing the same
JP2003066491A (en) * 2001-08-28 2003-03-05 Mitsubishi Electric Corp Liquid crystal display
JP2004163746A (en) * 2002-11-14 2004-06-10 Sanyo Electric Co Ltd Liquid crystal display

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2565639B2 (en) * 1992-04-30 1996-12-18 インターナショナル・ビジネス・マシーンズ・コーポレイション Liquid crystal display
JPH0915642A (en) * 1995-06-29 1997-01-17 Nec Corp Liquid crystal display device
JPH09127554A (en) * 1995-10-31 1997-05-16 Sharp Corp Transmission type liquid crystal display device
JP2002229029A (en) * 2000-11-28 2002-08-14 Sharp Corp Liquid crystal display and method for manufacturing the same
JP2003066491A (en) * 2001-08-28 2003-03-05 Mitsubishi Electric Corp Liquid crystal display
JP2004163746A (en) * 2002-11-14 2004-06-10 Sanyo Electric Co Ltd Liquid crystal display

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