JPH09153594A - Semiconductor device and its manufacture - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce the manufacture processes of a high resistance loading type static random access memory and stabilize a resistance element. SOLUTION: The manufacture of a semiconductor device is composed of; e) a process of forming a poly Si film 110 on the surface of a first insulating layer 108 to an extent that a through hole 109 is not completely filled, g) a process of forming a double-layer structure second conductive film by forming a metal silicide film 311 composed of WSi, Ti, Co, etc., on the surface of the poly Si film 110, and h) a process of processing the second conductive films 110 and 111 into the prescribed patterns. A process (f) which implants ions of P, As, etc., to the surface of the poly Si film 110 may be preferably added between the process of (e) and the process of (g), and prior to the process of (e), a process of oxidizing the surface of the first conductive film 104 which faces the through hole 109 may be added. A process of annealing the poly Si film 110 with hydrogen may also be added between the process of (e) and the process of (g).

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having a built-in high-resistance element and a method of manufacturing the same, and more particularly to a static random-type semiconductor device having a flip-flop composed of four transistors and two high-resistance loads in each cell circuit. The present invention relates to a structure of a semiconductor device having an access memory (SRAM) and the like and a manufacturing method thereof.

[0002]

2. Description of the Related Art The S of the above-mentioned high resistance load type 4 transistor
The circuit configuration of the RAM memory cell is shown in FIG. The line 11 of the power supply Vcc is connected to the direct contact 15 through the high resistance load 12. The feature of this configuration is that the gate and drain of the driver transistor 16 are directly connected by the direct contact 15. Data is,
Input / output is performed through the bit line 14 and the word transistor 13.

The structure of each cell of a typical conventional SRAM is shown in a sectional view of FIG. Each cell of this SRAM is
A field oxide film 102 for element isolation formed on a silicon substrate 101, and a first conductive layer 104 including a source region, a drain region, a gate electrode of a transistor, etc.
And the silicon oxide films 108 and 11 for insulating between the conductive layers.
2. Insulating layers such as phosphorus (P) glass 113, and second conductive layers 401, 4 of polysilicon (hereinafter referred to as poly Si) wiring formed to penetrate on and through the first insulating layer 108.
02 and the contact 11 connected to the aluminum wiring 115
It has a structure consisting of 4 parts. Usually, the second conductive layer is formed by a second-layer poly-Si wiring (hereinafter, abbreviated as 2 poly) having a high resistance region 402 and a low resistance region 401, and the high resistance region 402 is a high resistance load element. , Low resistance region 4
A part of 01 is used as a power supply line.

The most widely used method for forming the second conductive layer is to form the low resistance portion and the high resistance portion in a non-self-aligned manner by a aligning exposure technique and to form them separately.
For that purpose, four alignments of a direct contact step for directly contacting the gate electrode and the diffusion layer, a poly-poly contact step for connecting the poly and the poly-Si of the gate electrode, a poly processing step, and a poly resistance control step Exposure technology was required. However, this method has many steps,
2 Advanced poly wiring technology is required for processing poly,
There is a problem that it is difficult to reduce the resistance of the low resistance portion of the 2 poly, and the resistance of the 2 poly changes in the subsequent step of the chemical vapor deposition (CVD) method or the like.

In order to reduce the number of manufacturing processes, it has been proposed to reduce the direct contact process, poly-poly contact process, etc. by making the structure of the cell circuit as shown in FIGS. 14 (a) and 14 (b). There is also a method of increasing the poly-Si wiring layer to form a three-dimensional structure in order to improve the processing accuracy of the two-poly structure. However, it is difficult to form the aluminum (Al) wiring. Therefore, before forming the 2 poly wiring, a method of flattening the underlying gate step by chemical mechanical polishing (CMP) or the like to improve the processing accuracy, or forming a high resistance poly Si on the inner wall of the through hole to form a metal contact A method of electrically connecting Al wiring and high-resistance polysilicon to form a load resistance at the contact portion, and forming a laminated structure of Si oxide film / Si nitride film at the bottom of the through-hole for contact to form a high-resistance load And the like are disclosed.

As a measure for preventing a resistance change of a high resistance load, a method of forming a thermal oxide film of about 50 angstrom (hereinafter referred to as Å) after 2 poly processing has been put into practical use. This is used as a charge trap reduction at the interface of the 2 poly CVD oxide film and as a barrier against P diffusion from the P glass layer.

[0007]

However, each of the above-mentioned methods is effective as an individual measure, but is ineffective as a measure for other problems, or requires a higher level technique. Etc., there was a problem in practical use.

In order to solve these problems, a structure in which the inside of the through hole is filled with high-resistance poly-Si is disclosed in JP-A-1-124.
250. The outline of the manufacturing method is shown in FIGS. 12 and 13 (a) to (g).

(A) First, a field oxide film 102 of about 7,000 Å is formed on an N-type Si substrate 101 by a known method to form an element isolation film.

(B) Next, about 300 Å of gate oxide film 1
After forming 03, gate poly Si1 of about 4000 Å
04 is formed into a film and processed into an arbitrary wiring.

(C) Next, a source / drain layer of only N channel is formed by a known method to form a transistor. The SD annealing temperature is 950 ° C. After this, an atmospheric oxide film 108 of about 4000 Å is formed, and SO
After G coating is applied to planarize the through hole 109, a through hole 109 at a connection portion between the second layer wiring and the gate electrode is opened with an opening diameter of about 1.2 μm.

(D) Next, 1.2 μm is formed by the low pressure CVD method.
A poly Si film 110 of about m is formed to be 2 poly.

(E) Next, the poly-Si film 110 is entirely etched back to remove the poly-Si in the flat portion. At this time, the high-resistance poly-Si 601 is embedded in the through hole 109 while keeping its upper surface flat.

(F) Next, poly-Si6 of about 2500 Å
02 is formed, and arsenic (As) is deposited on the entire surface at 80 keV, 1 e
Implanting about xp16 atoms / cm ² to reduce the resistance.

(G) After that, the low resistance wiring 602 is patterned, and the P glass 113, the contact 114, and the Al wiring 115 are formed and completed.

This proposal has the advantage that it can solve all the problems described above, has a simple structure, and can be easily manufactured with current equipment, but the inside of the through-hole is filled with high-resistance poly-Si to provide a high-resistance load. The structure still has the following problems.

Since the inside of the poly-poly contact has a high resistance, the direct contact process cannot be reduced in the structure as shown in FIG. 14 (c). In the conventional example, only the aligning and exposing step for controlling the two-poly resistance can be reduced.

Further, the high resistance poly-Si formed in the through hole
Resistance is greatly influenced by the intrinsic resistance of poly-Si, resistance control is difficult, and matching between manufacturing lines is difficult.

When the diameter of the through hole is large, it is necessary to deposit 2 poly thickly so as to fill the hole. Therefore,
An etch-back process is essential after the two-poly film formation, resulting in an increase in the number of processes and the in-plane dependence of the two-poly etch rate on the wafer.

An object of the present invention is to make it possible to simultaneously reduce the two aligning exposure steps of the direct contact step and the two-poly resistance control step, facilitate resistance control of a high resistance load, and penetrate a large-diameter through hole. It is an object of the present invention to provide a semiconductor device that can be stably manufactured even when holes are used and a manufacturing method thereof.

[0021]

In order to achieve the above object, a semiconductor device of the present invention includes a metal film having a low resistance and a high melting point and at least a portion which is in contact with the first conductive film. It is characterized by having a second conductive film made of a resistance poly-Si film.

The second conductive film may have a two-layer structure of a polySi layer having a high resistance and a metal layer having a low resistance and a high melting point, and the metal layer may be located above the polySi layer.

Alternatively, the opening diameter of the second conductive film of the through hole is larger than the width of the first conductive film in the short side direction, and the third conductive film having a low resistance is provided at least on the side wall of the gate electrode which is the first conductive film inside the through hole. And a high resistance poly-Si film as an upper layer.

According to the method of manufacturing a semiconductor device of the present invention, the first step of forming the poly-Si film on the entire surface of the insulating layer including the through-holes to the extent that the through-holes are not filled up, and the low step on the surface of the poly-Si film. The method includes a second step of forming a metal film having a high melting point of resistance to form a second conductive film, and a third step of processing the second conductive film into a desired pattern.

After the completion of the first step of forming the poly-Si film and before the second step of forming the second conductive film, impurities are ion-implanted on the surface of the formed poly-Si film. It is desirable to include the step of injecting.

Further, it is desirable to further include a step of oxidizing the surface of the first conductive film facing the through hole before performing the first step of forming the poly-Si film.

After the completion of the first step of forming the poly-Si film, and before the second step of forming the second conductive film, a step of annealing the formed poly-Si film with hydrogen is performed. It is desirable to include.

A second method of manufacturing a semiconductor device according to the present invention is
The through hole is formed by making the opening diameter of the second conductive film larger than the width of the first conductive film, and the low resistance conductive film is included in the side wall of the gate electrode on the first conductive film. It is included inside the through hole above the gate electrode.

After the through hole is opened in the insulating layer, impurities are injected into the entire upper surface to form metal silicide on the exposed portion inside the through hole of the first conductive film, and then the resistance of the metal silicide is reduced. Then, the second conductive film may be formed by depositing a refractory metal on the poly-Si which becomes a high resistance load.

As described above, when the second conductive film has a two-layer structure of poly-Si and a low resistance refractory metal, the resistance of the high resistance load and the power supply line can be controlled and the insulating layer including the through hole can be controlled. By forming the poly-Si film to the extent that the through-holes are not filled up on the entire surface of, the 2 poly etch-back which has been conventionally performed is unnecessary, and therefore the process variation due to the etch-back is eliminated.

By implanting impurities into the surface of the formed poly-Si film, the resistance value of the high resistance load portion can be freely controlled.

In addition, by oxidizing the surface of the first conductive film facing the through hole before forming the poly-Si film, the exposed portion of the first conductive film at the bottom of the through hole is oxidized and high resistance is obtained. The layer can be stably formed. This high resistance layer is the first
It also serves as a barrier against P diffusion from the upper layer of the conductive film.

After the poly-Si film is formed, the formed poly-Si film is annealed with hydrogen to increase the resistance of the high-resistance load portion.

[0034]

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a partial structural sectional view of a first embodiment of a semiconductor device of the present invention, FIG. 5 is a surface layout of the semiconductor device of FIG. 1, and FIG. 6 is a first embodiment of a method of manufacturing the semiconductor device of FIG. FIG. 7 is a sectional view of the partial structure in the order of manufacturing steps, and FIG. 7 is an explanatory view of the manufacturing flow in FIG.

In FIG. 1, the semiconductor device according to the first embodiment has an element isolation film 102, a gate oxide film 103, a poly Si 104a and a tungsten silicide (WSi) 104b poly on an N-type silicon (Si) substrate 101. The first conductive film 104 including the side gate, the first insulating film 108, the first
To fill the through-hole 109 of the insulating film 108 of the first conductive film 10
4 and 2 poly 110 reaching poly poly contact 109a
And a second conductive film made of a refractory metal 111, a second insulating film 112, a P glass 113, an Al wiring 115, and a contact 114 extending from the gate oxide film 103 to the Al wiring 115.

The method of manufacturing the semiconductor device according to the first embodiment is shown in FIGS. 6 to 7. (a) First, the element isolation film 102 is formed on the N-type Si substrate 101.
Is formed downward in a convex shape to about 4800Å.

(B) Next, after implanting a channel impurity for controlling the VT voltage, a gate oxide film 103 of about 75Å is formed, and then the gate oxide of the direct contact portion 106 for directly joining the gate and the diffusion layer is formed. Remove the membrane.

Although this step is not clearly shown in the above-mentioned conventional example, it is a step required also in the case of the conventional example. If this step is omitted, a metal contact as shown in FIG. 14A is used. A direct contact 505 is required.
l The layout of the wiring 508 is limited. In practice, it is necessary to increase the number of aluminum wires. FIG.
The direct contact formation via the poly-poly contact as shown in (c) is not practical because a high resistance is formed between the diffusion layer and the gate electrode.

(C) Next, the gate electrode 10 is formed by a known method.
4 is processed to form a transistor region. At this time, the gate electrode 104 is formed of WSi 1500Å / polySi 150
Polycide gate of 0Å laminated structure 104a, 104b, or titanium (Ti) or cobalt (Co)
Use a salicide gate using.

(D) Next, the oxide film 108 of the first insulating layer is formed to 1000 by the atmospheric pressure CVD method which can be formed at a relatively low temperature.
About 2000 to form a film. As the grown film thickness increases, cavities (voids) are generated between the gate electrodes close to each other.
When the thickness is reduced, the interlayer capacitance between the 2 poly 110 and the gate electrode 104 cannot be ignored.

After that, by the alignment technique, 2 poly 110 is used.
Poly-poly contact 10 for connecting the gate electrode 104 to the gate electrode 104
A through hole 109 for 9a is opened. In this case, the opening diameter is set to about 0.6 to 0.8 μm. In the prior art, the smaller the opening diameter, the better, but in the present invention, the larger the opening diameter, the better.

As described above, the steps (a) to (d) are almost the same as those in the prior art.

(E) Next, 2 poly 110 of about 1000 to 1500 Å is grown at a temperature of about 670 ° C. by the CVD method. A portion of the 2 poly 110 inside the through hole 109 is used later as a high resistance load.

In this step, since the 2 poly film is thin, the inside of the through hole 109 is not completely filled with the 2 poly 110. 2 Because the poly film is thin,
The poly etch back is not necessary, so that the process variation due to the etch back is eliminated and the manufacturing margin can be improved. Further, since there may be any number of steps under 2 poly, the conventional flattening process under 2 poly is not necessary at all, resulting in an effect of reducing the number of steps.
Needless to say, the material of 2 poly may be amorphous Si.

After forming the 2 poly 110, the 2 poly 110 may be further increased in resistance by hydrogen annealing as in the conventional case.

The 2 poly may be thickened to fill the inside of the through hole. On the contrary, if the diameter of the through-hole is reduced due to the cell size, the inside of the through-hole is filled only by forming two thin poly, so that the inside of the poly-poly contact is inevitably filled. In this case, the resistance control of the through hole can be controlled by a technique such as thinning the interlayer film.

(F) Next, 50 keV, 5 exp
Phosphorus (P) is implanted at about 12 to 3 exp13 atoms / cm ² .

Since the resistance value inside the through hole is determined by the resistance in the central portion of the through hole, it becomes possible to freely control the poly-poly contact resistance value by performing P implantation. If one wants to use the intrinsic resistance of poly, then this P implantation step is unnecessary. When the VT voltage of the memory transistor is lowered to speed up the operation, if the resistance value of the high resistance load resistance is higher than necessary, retention failure will occur, so that the controllability of this resistance value is significant.

In the prior art, since 2 poly is buried inside the through hole, the poly Si film thickness in the high resistance portion becomes thick, and therefore, when the resistance control is performed by ion implantation, the required acceleration energy is large. Become. Further, since the resistance is determined not by the peak portion of the impurity profile but by the tail portion, there is a problem that the manufacturing variation becomes large.

(G) Next, refractory metal 111 such as WSi
Is deposited to about 300 to 700 Å. Since this step is different from the conventional method of forming a low resistance layer by ion implantation of impurities, the resistance fluctuation due to the diffusion of impurities from the upper layer WSi is negligible. Therefore, the manufacturing margin is improved with respect to the thermal history of the subsequent process, and
It has the effect of thinning the poly film. Moreover, the resistance of this metal is
Since it is lower than that of the poly-Si resistor, it is also effective for lowering the resistance of the power supply line.

(H) After that, the 2 poly 110 is processed into an arbitrary pattern. At this time, as shown in FIG.
In the layout of 04, since only the periphery of the metal contact 201 needs to be removed, fine processing is unnecessary. That is, there is no fear of short-circuiting between wirings, which is also effective in improving the yield.

(I) The subsequent steps are not so different from the prior art. That is, this embodiment also uses 2 poly 1 as in the conventional case.
RTA (Rapi
It is necessary to control in units of seconds using the d Thermal Anneal method. This is the gate poly Si of the N-channel transistor.
This is to prevent the diffusion of P or As atoms doped therein into the poly-poly contact. But RT
Even if the method A is used, some impurities are diffused into the poly-Si at the bottom of the through hole to lower the resistance, which is different from the conventional structure in which the contact bottom is a high resistance body.

Next, another example of the method of manufacturing the semiconductor device of the first embodiment will be described with reference to FIG.

In this method, first, (a) of the first embodiment is used.
After forming (a) up to the opening of the through hole in the same manner as in (d), a step of applying heat treatment at 650 to 700 ° C. in a 2% oxygen atmosphere for about 5 minutes is inserted (b), and thereafter. The following steps (e) of the first embodiment are carried out (c). By doing so, as shown in FIG. 8B, the exposed portion 301 of the gate electrode WSix at the bottom of the through hole is oxidized, and the high resistance layer can be stably formed. The high resistance layer 301 serves as a barrier against P diffusion from the first layer poly Si.

In the above description, WSix is used as the refractory metal 111 on the 2 poly 110, but Ti or Co is used.
May be used.

2 WS provided on all surfaces on poly 110
Due to the wiring 111 having a low resistance such as i, the fluctuation of the 2-poly resistance due to the process in the subsequent steps is reduced to a negligible level. Therefore, a surface protection film such as a thermal oxide film on the surface of 2 poly, which is conventionally required in part, is unnecessary.

In addition to the above-mentioned P, As, Sb and the like are also effective as the material for injecting and diffusing for controlling the 2 poly resistance.
Further, it is possible to further increase the load resistance by performing hydrogen (H2) annealing after forming the two poly films.

As described above, if the opening diameter of the through hole becomes smaller than the sub-half micron, 2 poly will fill the through hole. At this time, 2 poly may be left as it is without being etched back, and As may be injected into the surface to form a low resistance layer. In this case, since the thickness of the two-poly film becomes thicker than 1/2 of the diameter of the through hole, the area directly above the connection hole is not necessarily flat, but it is not necessary to make it flat.

Further, by introducing oxygen during the growth of 2 poly,
It is also possible to control the grain size by forming a thin oxygen (O2) leak layer in the poly.
In general, the use of the O2 leak layer can increase the poly-poly contact resistance, and is an effective method for manufacturing a standard SRAM cell.

Next, the second embodiment of the present invention will be described with reference to FIG.
And FIG.

In the semiconductor device of the second embodiment, as shown in FIG. 2, the polycide gate 1 which is the first conductive layer in the through hole is formed.
There is a low-resistance conductive film on the side walls of 04a and 104b, and high-resistance poly-Si exists between the second conductive layer and the low-resistance high-melting-point metal film WSi 111. The semiconductor device manufacturing method according to the second embodiment is as follows. In FIG. 9, (a) First, in the same manner as in FIG. 6 (a) of the first embodiment, an element isolation film 102 of about 4800Å is formed on an N-type Si substrate 101. After formation and channel impurity implantation for VT control, a gate oxide film 103 of about 75 A ″ is formed.

In the first embodiment, the selective etching process of the gate oxide film for forming the direct contact portion is required here. Without this selective etching step, the diffusion layer and the gate electrode would have to be connected via the aluminum wiring Al, limiting the layout of the aluminum wiring. That is, if there is no aluminum wiring of three layers or more, it is very difficult to connect via aluminum wiring, but in the present embodiment, the selective etching step for this direct contact becomes unnecessary.

(B) Next, the gate electrodes 104a and 104
b is processed to form a transistor region. At this time, the gate electrodes 104a and 104b are made of tungsten silicide (W
Si): 1500Å / poly Si: 1500Å laminated polycide gate or salicide gate using titanium Ti or cobalt Co is used.

(C) Next, a first oxide film 108 having a thickness of about 2000 Å is formed by an atmospheric pressure CVD method which can be formed at a relatively low temperature, and then a poly-poly connecting two poly and a gate electrode is connected by an alignment technique. The contact 109a is opened.
This opening diameter is made larger than the gate electrode. Generally, it is preferable to set the long side direction to about 1.0 μm. Further, when the poly-poly contact is opened, almost no oxide film remains on the side wall of the gate electrode.

(D) Thereafter, using the CVD method, 670
After the first 2 poly 110 is grown to about 500Å at a temperature of about ℃, 50 KeV, 1 exp13 atom / c on the entire surface.
Ion implantation of phosphorus of about m ^{2 is performed by} a rotary implantation method in which the phosphorus is tilted by about 30 °. By this operation, the gate electrode and the diffusion layer are connected via the 2 poly 110.

(E) Next, the entire surface of poly-Si is etched back by an anisotropic etching technique. Since the gate electrode is vertical, poly-Si is left on the side wall of the gate electrode without being etched. The remaining portion becomes the direct contact 106 that directly connects the gate electrode and the diffusion layer. It is also possible to effectively destroy the natural oxide film existing at the interface between the 2 poly 110 and the silicon substrate by optimizing the energy of this phosphorus implantation.

(F) Next, the second poly-Si is grown to 1000 to 2000 liters, and a refractory metal such as WSi is formed on the film to about 400 liters. As a result, the second layer wiring has a polycide structure. The second growth WSi
The lower poly Si acts as a high resistance load.

The subsequent steps are the same as those in (h) of FIG. 6 of the first embodiment, and the memory cell of FIG. 2 is completed by removing only the polycide around the metal contact.

In order to prevent the phosphorus or arsenic atoms doped in the gate poly Si and the diffusion layer of the N-channel transistor from diffusing into the poly poly contact, 2
When heat treatment at 800 ° C. or higher after poly formation is performed, control in seconds using RTA is necessary also in this embodiment.

Next, regarding the semiconductor device of the third embodiment,
This will be described with reference to FIGS. 3 and 10. As shown in FIG. 3, the semiconductor device of the third embodiment is composed of TiSi2 121 in which the direct contact 106 between the gate electrode and the diffusion layer is left.

FIG. 10 is a partial sectional view in order of the steps, showing the method for manufacturing the semiconductor device of the third embodiment.

(A) to (c) This method is the same as that up to (c) in the second embodiment up to the opening of the poly-poly contact portion.

(D) Next, 50 keV, 1 exp1 over the entire surface
After injecting As of about 5 atom / cm ^2, titanium metal 120 is deposited on the entire surface to a thickness of about 300 Å. After this, 69
By performing heat treatment at 0 ° C. for about 30 seconds, titanium silicide (TiSi 2) 121 is formed only in the exposed portion of the silicon inside the poly-poly contact.

(E) When immersed in a mixed solution of ammonia and hydrogen peroxide in this state, the TiSi 2 1 inside the poly contact is
Only 21 remains as it is, and titanium on the silicon oxide film is removed. The remaining TiSi2 121 functions as a direct contact between the gate electrode and the diffusion layer. This is the same principle as the so-called salicide process.

(F) Then, after heat treatment at 870 ° C. for about 10 seconds to reduce the resistance of the TiSi 2 121, the second polySi 110 and WSi 111 are treated in the same manner as in the second embodiment.
To form

After this, the same steps as those of the first and second embodiments are carried out to complete the semiconductor device of the third embodiment of FIG.

In the step of forming the direct contact of the third embodiment, the refractory metal sputtering and the etch back may be used instead of TiSi2. At this time, the refractory metal may be removed only in the flat portion.

In the direct contact forming process of the first embodiment, the inside of the through hole may be filled by selective W growth. Since W does not grow anywhere other than through holes, direct contacts can be formed in the fewest steps.

In the second and third embodiments, the conductive material such as refractory metal is completely embedded in the direct contact 106 portion inside the poly-poly contact, and the entire through hole is filled with the conductive material. It doesn't matter. In particular, when the poly-poly contact is small, the inside of the through hole is inevitably completely occupied by the conductive material, and this feature is effective.

Further, the direct contact may be connected to only one side of the gate electrode, not both ends.

[0082]

As described above, in the semiconductor device of the present invention, the second conductive film is thickened by forming the second conductive film into a laminated structure including a refractory metal film and a high resistance poly-Si film. It is not necessary to form a film, and there is an effect that resistance control of the connection portion of the first and second conductive films can be easily performed.

Further, since the first conductive film is made of a metal having a low resistance and a high melting point in which the surface of the portion exposed in the through hole is oxidized, or its metal silicide, the resistance fluctuation due to the diffusion of impurities from the upper layer. Is negligible. Therefore, there is an effect of improving the manufacturing margin with respect to the thermal history of the subsequent process and reducing the thickness of the poly-2 film. Further, since the resistance of this metal is lower than that of the poly-Si resistor, it is also effective for lowering the resistance of the power supply line.

In addition, the opening diameter of the second conductive film of the through hole is the first
A third conductive film having a width smaller than the width of the conductive film in the short side direction and having a low resistance at least on the sidewall of the gate electrode, which is the first conductive film, inside the through hole.
By including the conductive film and the high resistance silicon film on the third conductive film, it is possible to reduce the direct contact PR process without increasing the number of Al wiring layers. High integration of memory cells can be achieved.

According to the method of manufacturing a semiconductor device of the present invention, the second conductive film is formed as a poly-Si film on the entire surface of the insulating layer on the first conductive film to such an extent that the through holes are not filled up. By forming a high melting point metal film on the surface to form a laminated structure, a low resistance layer is formed by the high melting point metal, and poly S
Since it is possible to obtain a resistance value lower than that of the i-resistor, and impurity diffusion from the low-resistance wiring portion can be ignored, it is possible to improve the margin for the thermal history during manufacturing. In addition, poly-Si cannot be filled to the extent that it does not fill up the through holes.
By forming a film, it can be applied stably even when a large-diameter through hole is used, the etching back process of poly-Si of the second conductive film can be omitted, and the effect of reducing the process can be obtained.
Effective in stabilizing the quality during manufacturing.

After forming the poly-Si film, poly-Si film is formed.
By implanting impurities into the surface of the film, the second
There is an effect that the resistance of the power supply line of the conductive film can be reduced.

By oxidizing the surface of the first conductive film facing the through hole before forming the poly-Si film,
There is an effect that the high resistance layer can be stably formed.

Further, after forming the poly-Si film and before forming the low-resistance and high-melting-point metal film, the poly-Si film is annealed with hydrogen, whereby the load resistance can be further increased. .

Further, according to the second manufacturing method, it is possible to prevent the inside of the through hole of the poly-poly contact portion from having a high resistance, and it is not necessary to use aluminum wiring of three or more layers.

[Brief description of the drawings]

FIG. 1 is a partial cross-sectional view showing the structure of a first embodiment of a semiconductor device of the present invention.

FIG. 2 is a partial cross-sectional view showing the structure of a second embodiment of the semiconductor device of the present invention.

FIG. 3 is a partial cross-sectional view showing the structure of a third embodiment of the semiconductor device of the present invention.

FIG. 4 is a circuit configuration diagram of a high resistance load type four-transistor SRAM memory cell.

FIG. 5 is a surface layout of the first embodiment.

FIG. 6 is a partial structural sectional view of an example of a manufacturing process of the semiconductor device according to the first embodiment of the present invention.

7 is an explanatory diagram of the manufacturing flow of FIG.

FIG. 8 is a partial structural cross-sectional view of another example of the manufacturing process of the semiconductor device according to the first exemplary embodiment of the present invention. (A) It is a partial structure sectional view in order of a manufacturing process. (B) is a manufacturing flow of (A).

FIG. 9 is a partial structural sectional view of an example of a manufacturing process of a semiconductor device according to a second embodiment of the present invention.

FIG. 10 is a partial structural sectional view of an example of a manufacturing process of a semiconductor device according to a third embodiment of the present invention.

FIG. 11 is an example of a conventional typical structural sectional view.

FIG. 12 is a structural cross-sectional view in the order of manufacturing steps of a conventional example.

FIG. 13 is an explanatory view of the manufacturing flow of FIG.

FIG. 14 is a sectional view of another conventional structure.

[Explanation of symbols]

11 power source, Vcc 12 high resistance load 13 word transistor 14 bit line 15 direct contact 16 driver transistor 17 ground 101 Si substrate 102 element isolation film 103 gate oxide film 104 first layer conductive film, gate electrode 104a, 501 polycide, poly Si 104b, 502 Salicide, WSix 106, 503 Direct contact 108, 506 First insulating layer, oxide film 109 Through hole 109a Poly poly contact 110, 204, 301, 401, 402, Second layer conductive film, 2 Poly 111 Second layer Conductive film, refractory metal, metal silicide 112 second insulating layer, oxide film 113 P glass 114, 201, 507 contact 115, 504 Al wiring 120 titanium, Ti 121 titanium silicon, Ti Six 202 word line 03 gate 601 high resistance of the flip-flop poly Si 602 low-resistance poly Si (a) ~ (i) manufacturing process

Claims (10)

[Claims] 1. A first conductive film formed on a silicon substrate, and an insulating layer formed on the first conductive film.
A semiconductor device having a second conductive film electrically connected to the first conductive film through a through hole penetrating the insulating layer from above the insulating layer, wherein the second conductive film is A semiconductor device having a laminated structure including a low-resistance and high-melting-point metal film and a high-resistance polysilicon film including at least a portion in contact with the first conductive film. 2. The second conductive film has a two-layer structure of a polysilicon layer having a high resistance and a metal layer having a low resistance and a high melting point, and the metal layer is located above the polysilicon layer. Semiconductor device. 3. A first conductive film formed on a silicon substrate, and an insulating layer formed on the first conductive film.
A semiconductor device having a second conductive film electrically connected to the first conductive film through a through hole penetrating the insulating layer from above the insulating layer. The opening diameter of the hole is larger than the width of the first conductive film in the short side direction, and at least the side wall of the gate electrode, which is the first conductive film, includes the third conductive film having a low resistance inside the through hole. A semiconductor device having a high-resistance silicon film on the upper part of the film. 4. A step of forming a first conductive film on a semiconductor substrate, a step of forming an insulating layer on the first conductive film, and a step of penetrating the insulating layer to form the first conductive film. In the method of manufacturing a semiconductor device, which comprises the step of forming a through hole that reaches and a step of forming a second conductive film including a high resistance load inside the through hole, the step of forming the second conductive film includes: A first step of forming a high resistance load of the polysilicon film on the surface of the insulating layer on the first conductive film including the inside of the through hole; and forming a low resistance high melting point metal film on the surface of the polysilicon film. And a second step of forming a second conductive film, and a third step of processing the second conductive film into a desired pattern. 5. The high resistance load of the polysilicon film is formed on the surface of the insulating layer on the first conductive film including the inside of the through hole to an extent not filling the through hole in the first step.
A method of manufacturing a semiconductor device according to item 1. 6. The polysilicon film is further formed after the first step of forming the polysilicon film and before the second step of forming the second conductive film. The method for manufacturing a semiconductor device according to claim 5, comprising a step of ion-implanting impurities into the surface. 7. The method according to claim 5, further comprising a step of oxidizing the surface of the first conductive film facing the through hole before performing the first step of forming a polysilicon film. A method for manufacturing a semiconductor device as described above. 8. After the completion of the first step of forming a polysilicon film, and before performing the second step of forming a second conductive film, the polysilicon film is further hydrogenated. The method for manufacturing a semiconductor device according to claim 5, comprising a step of annealing. 9. A step of forming a first conductive film on a semiconductor substrate, a step of forming an insulating layer on the first conductive film, and a step of penetrating the insulating layer to form the first conductive film. In the method of manufacturing a semiconductor device, which comprises the step of forming a through hole reaching the opening and the step of forming a second conductive film including a high resistance load inside the through hole, the opening diameter of the second conductive film is set to the first diameter. A through hole is formed to reach the silicon substrate by making it wider than the width of the conductive film in the short side direction, and a low resistance conductive film is formed so as to be included in the side wall of the gate electrode on the first conductive film. A method of manufacturing a semiconductor device, comprising forming a second conductive film by including a film inside a through hole above a gate electrode. 10. After forming a through hole in the insulating layer, impurities are injected into the entire upper surface to form a metal silicide on the exposed portion of the first conductive film in the through hole, and then the metal silicide is reduced in resistance. 10. The method for manufacturing a semiconductor device according to claim 9, wherein the second conductive film is formed by forming a refractory metal film on a polysilicon film, which has a high resistance load.