JPH09153544A - Semiconductor device and its manufacture - Google Patents

Abstract

PROBLEM TO BE SOLVED: To attain a high integration of semiconductor device by simultaneously forming wiring layers having conductor connecting to upper layer using single resist layer per wiring layer. SOLUTION: Films made of conductive material are formed on the surface of a semiconductor substrate 1; resist film 4a-2 in fine width is formed on the wiring forming part while the other resist films 4b-1, 4b-2 in larger width are formed on the part connecting to upper layer; oxygen, etc., is injected in combination of rotary ion implanting step and almost vertical ion implanting step to form an insulating part so that wiring layers, interlayer insulating film and connecting conductor may be simultaneously formed on the surface of the semiconductor substrate 1.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to a structure of a wiring layer and a forming method thereof.

[0002]

2. Description of the Related Art As an example of the prior art, a method of forming a wiring by aluminum formation will be described with reference to the sectional views of FIGS. This example is disclosed in JP-A-63-108.
This is an example shown in Japanese Patent Publication No. 750. First, FIG.
As shown in (a), an aluminum film 3 is formed over the entire surface of the N ⁻ type silicon substrate 1 on which the diffusion layers 1B, 1C, 1E and the insulating film 2 are formed, and then, as shown in FIG. As shown, a thin oxide layer 14 is formed on the surface of the aluminum film 3.
And further, a resist film 4 is formed by a coating method,
The resist film other than the wiring formation portion is removed by lithography, and then the thin oxide layer 1 on the surface is etched.
Remove 4. Next, after removing the resist film 4, FIG.
Using the electric field tank 17 as shown in FIG.
Then, the aluminum film 3 other than the wiring forming portion is oxidized by anodic formation. The N ⁻ type silicon substrate 1 is attached to the anode 19 side in the electrolytic solution 15, and the DC power supply 18 is supplied between the anode 19 and the cathode 16. When the oxidized substrate is taken out from the electrolytic solution, as shown in FIG. 8C, a wiring layer is formed by the aluminum film 3 which is insulated by the alumina isolation insulating portion 7.

Further, as a conventional technique closer to the present invention, an aluminum chemical conversion method by ion implantation (Japanese Patent Laid-Open No. 3-10).
Wiring forming method disclosed in Japanese Patent No. 8750) will be described with reference to FIGS. First, FIG.
As shown in (a), the aluminum film 3 is formed on the entire surface of the substrate in the same manner as the above-described aluminum chemical conversion method, and then, as shown in FIG.
As shown in (b), a photoresist film 4 is formed on the aluminum film by a coating method, and the photoresist film in the ion-implanted portion 6 is removed by a lithography technique.
Next, as shown in FIG. 10C, oxygen ions are implanted by using the ion implantation method. For example, in order to oxidize an aluminum film having a thickness of 1 μm, implantation of oxygen ions 5 of about 1 × 10 ¹⁹ / cm ² may be performed. In the case of a high current ion implanter with a beam current of 100 mA, a 4-inch wafer can be implanted in about 40 minutes. Since the distribution width in the depth direction is narrower than the normal implantation depth and the standard deviation is several tens of nanometers, the accelerating voltage is changed stepwise or continuously as shown in FIG. As a result, oxygen ions are distributed over the entire ion-implanted portion to form the isolation insulating portion 7. After this ion implantation, the photoresist film 4 on the surface is removed and annealing is performed. This annealing is for completing the oxidation reaction and stabilizing the oxygen ions. Depending on the aluminum film thickness, the oxygen ions are not redistributed, but the annealing is performed at a temperature as low as 500 ° C. or less.
It may be performed for about 0 minutes. Depending on the film thickness and material (difference in aluminum film forming method) and the substrate temperature during ion implantation, stable oxides can be formed without annealing. After this annealing, as shown in FIG.
The surface protection film 8 is provided. This surface protection film 8 adjusts the acceleration voltage so that oxygen ions are implanted only in the surface portion,
The dose is adjusted according to the required film thickness, the entire surface except the bonding pad portion 9 is ion-implanted, and annealing is performed as before.

[0004]

The above-described conventional wiring layer formed by aluminum conversion is excellent in that the surface is flat because an isolation insulating film is necessarily formed between them. However, as in the example described with reference to FIG. 8, a lithography process for exposing the bonding pad portion is required in the case of single layer wiring, and in the case of multilayer wiring, the surface protective film 8 or the thin oxide film 14 is used. A through hole must be formed by forming it to a certain thickness or by depositing an interlayer insulating film again. The lithography process is required twice, that is, the formation of the wiring layer and the formation of the openings in these insulating films.

If the number of wiring layers is N, a lithography process is required at least 2N times, so that there is a disadvantage in terms of cost, and the construction period for production also increases, resulting in a short TAT.
It is disadvantageous in responding to the customer's request for (turnaround time). Further, it is necessary to take a planar margin in order to absorb the misalignment between the wiring layer and the through hole and the conversion error of each dimension. This increases the pitch of the wiring layers, which increases the chip area of the semiconductor chip, which is disadvantageous in terms of cost. Further, an increase in the pitch of the wiring layers leads to an increase in the average wiring length, which increases the wiring delay, which is also disadvantageous in terms of performance.

An object of the present invention is to provide a semiconductor device capable of simultaneously forming a wiring length, a connecting portion and an insulating film by requiring only one lithography step for each wiring layer, and attempting miniaturization, high integration and reduction of man-hours. It is to provide the manufacturing method.

[0007]

According to the present invention, there is provided a semiconductor device comprising:
A first wiring layer that selectively covers the first insulating film on the semiconductor substrate; a second insulating film that covers the first insulating film on which the first wiring layer is formed; A second wiring layer that is formed by filling the opening provided in the insulating film and selectively covers the second insulating film, or a connection conductor connected to a lead, and the opening and the connection conductor Are self-aligned with the first wiring layer immediately below them.

Here, the first wiring layer and the connection conductor may be formed of the same conductive material at the same time, and the second insulating film may be an oxide, a nitride, or an oxynitride of the conductive material.

Further, the conductive material may be aluminum, an alloy containing aluminum as a main component, or silicon.

A method of manufacturing a semiconductor device according to the present invention comprises the steps of covering a first insulating film on a semiconductor substrate and forming a conductive film whose oxide, nitride or oxynitride is an insulator. Forming a resist film having a main wiring forming portion having a first width and a connection region forming portion having a second width wider than the main wiring forming portion; and the first portion of the conductive film immediately below the resist film. A step of implanting oxygen ions and / or nitride ions over a predetermined thickness from the surface in contact with the insulating film, and a part of the conductive film not covered with the resist film and the main wiring forming part. The first portion is formed by converting all the portions and the portion of the peripheral portion of the portion covered by the connection region forming portion to the predetermined thickness portion into which oxygen ions and / or nitrogen ions are implanted into an insulator. In width A first wiring layer having a main wiring portion having a corresponding width and a connection region having a width corresponding to the second width, and a second insulating film self-aligned with the connection region and made of the insulator. In addition, the second wiring layer that selectively covers this or the connection conductor that is connected to the lead is formed.

Here, the conductive coating can be formed of aluminum, an alloy containing aluminum as a main component, or silicon.

The wiring layer, the insulating film covering the wiring layer, and the connection conductor can be formed at the time of self-alignment using a single resist film.

[0013]

Next, a first embodiment of the present invention will be described.

First, as shown in FIG. 1, a diffusion layer 1B (P ⁺ type base region), a diffusion layer IC (N ⁺ type collector connection region), a diffusion layer IE (N) are formed on the surface of the N ⁻ type silicon substrate 1.
^{A +} type emitter region), a silicon oxide film (insulating film 2), contact holes CB, CC and CE are formed, and an aluminum film 3-1 having a thickness of 1 μm is deposited on the entire surface.

Next, as shown in FIG. 2, a photoresist film is applied on the aluminum film and a pattern is formed by lithography. Here, the photoresist films 4a-1 to 4a-4 having a narrow width are formed in the main wiring formation portion, and the photoresists 4b-1 and 4b having a width larger than that are formed in a portion (connection area formation portion) for connection with an upper layer. -2 is formed. The method of determining these widths will be described later. Next, as shown in FIG. 3, the rotary ion implantation and the substantially vertical ion implantation are combined to implant oxygen ions 5 into the substrate obliquely from above and in the vertical direction. For example, in order to oxidize an aluminum film having a thickness of 1 μm, implantation of oxygen ions 5 of about 1 × 10 ¹⁹ / cm ² may be performed. In the case of a high-current ion implanter with a beam current of 100 mA, it can be implanted in a 4-inch wafer in about 40 minutes. Since the distribution width in the depth direction is narrower than the normal implantation depth and the standard deviation is several tens of nanometers, the insulating portion is formed by changing the acceleration voltage stepwise or continuously. Further, if necessary, the angle of the rotational injection may be changed stepwise or continuously to form an insulating portion having a more desired shape. Here, since the photoresist films 4a-1 to 4a-4 having a narrow width are formed in the main wiring formation portion, the aluminum film remains as the main wiring portions 3a-1 to 3a-4 below them and these photoresist films 4a-1 to 4a-4 are formed. An ion-implanted region 3-1b is formed above the main wiring portion and in a portion not covered with the photoresist film. Since the thick photoresist films 4b-1 and 4b-2 are formed in the connection region formation portion, the connection regions 10-1 and 10b are formed below them.
-3 and the connection conductors 10-2 and 10-4 are formed in a self-aligned manner.

After this ion implantation, the photoresist film on the surface is removed and annealing is performed. This anneal is for completing the oxidation reaction and stabilizing the oxygen ions, and is performed at a temperature as low as 500 ° C. or less for about 30 minutes so that the redistribution of oxygen ions does not occur depending on the aluminum film thickness. I'll do it. As an annealing method, there is a method using an infrared lamp irradiation called an RTA method (rapid thermal annealing method) other than a normal baking apparatus. By this step, the conversion of the ion-implanted region 3-1b into the insulator (aluminum oxide) is completed, and the interlayer insulating film 3-1 shown in FIG.
c is formed.

Next, a method of determining the width of the photoresist film and the ion implantation conditions for forming the wiring and the interlayer insulating film will be described. Here, in order to simplify the description, a model simplified in the following points will be described.

It is assumed that the side surface of the photoresist film is vertical. Although the implantation depth (projection range Rp and dispersion ΔRp) at the time of ion implantation is different depending on the resist material and the wiring material, they are the same for simplification of description. 1) Vertical ion implantation conditions As shown in FIG. 6, a conductive film 3 such as an aluminum film.
A photoresist film 4 having a width W _{PR and a} thickness t _PR on (thickness t _AL ).
Have been formed. Although vertical ion implantation is performed using the photoresist film 4 as a mask, conditions are set such that the region I from the lower surface of the conductive film 3 to at least the thickness t _LINE is made into an insulator.

For example, the aluminum film thickness (t _AL ) is set to 1
In order to set t _LINE to 0.5 μm, the oxygen ion implantation conditions are such that the implantation angle is 0 degree and the energy from the surface of the aluminum film (3) to 0.5 to 1.0 μm can be converted to alumina. And the dose amount. 2) Resist film thickness The film thickness of the resist is determined so that ions do not reach the aluminum film portion covered with the photoresist film 4 by the vertical ion implantation of 1). 3) Rotating Ion Implantation Condition The rotating ion implantation is set under the condition that at least the hatched region II in FIG. Now, assuming that the oxygen ion implantation angle is θ, conditions are set so that the aluminum film from the surface to y, that is, (t _AL −t _LINE ) can be converted to alumina.

4) Method for determining pattern width At that time, the length of x in FIG. 6B is (t _AL -t _LINE ) t
anθ. For example, t _AL is 1 μm and t _LINE is 0.
When 5 μm and θ are 45 degrees, y is 0.5 μm and x is 0.5 μm. In this case, a connection conductor is formed when W _PR > 2x, that is, when the width exceeds 1 μm. For example, t _AL is 1
If μm, t _LINE is 0.5 μm and θ is 30 degrees, y is
0.5 μm and x are 0.29 μm. In this case W _PR ＞
If the width exceeds 2 ×, that is, 0.58 μm, the connection conductor is formed.

For example, when W _PR is 0.7 μm,
The size (W _PR -2x) of the connecting conductor is 0.12 μm, and an extremely fine connecting conductor can be formed.

When the projection range R _P is different between the photoresist film and the conductive film, the side surface of the connecting conductor is not vertical and forms an acute angle or an obtuse angle with respect to the surface of the connecting region. Since it does not have the problem of step coverage (step coating property) unlike the case of forming by the method,
I can't make a difference.

Thus, the formation of the first aluminum wiring layer, the connection conductor and the interlayer insulating film is completed.

The wiring layer, the interlayer insulating film and the connection conductor can be formed not only by a single photoresist process, but also the connection region and the connection conductor of the lower wiring layer can be formed in a self-aligned manner. In addition, a planar margin required for alignment for forming a through hole, which has been conventionally required, is unnecessary. Subsequently, a second aluminum wiring layer is formed. As shown in FIG. 5A, an aluminum film 3-2 is formed, and then a photoresist is applied on the aluminum film as shown in FIG. 5B and a pattern is formed by lithography.

Here, thin photoresist films 4C-1 and 4C-2 are formed in the main wiring forming portion, and a thicker photoresist film 4d-1 is formed in the bonding pad forming portion. Next, as shown in FIG. 5C, the rotary ion implantation and the substantially vertical ion implantation are combined,
Oxygen ions 5 are implanted obliquely above and perpendicular to the substrate. For example, in order to oxidize the aluminum film having a thickness of 1μm is, 1x10 ¹⁹ / cm ^{2 extent} oxygen ions 5
Should be injected. In the case of a high-current ion implanter with a beam current of 100 mA, it can be implanted in a 4-inch wafer in about 40 minutes. Since the distribution width in the depth direction is narrower than the normal implantation depth and the standard deviation is several tens of nanometers, the insulating portion is formed by changing the acceleration voltage stepwise or continuously. Further, if necessary, the angle of the rotational injection may be changed stepwise or continuously to form an insulating portion having a more desired shape. Here, since the photoresist films 4c-1 and 4c-2 having a narrow width are formed in the main wiring forming portion, the main wiring portions 3-2a1 and 3-2a2 are formed in the lower portion thereof in the upward direction of the main wiring portion. Further, the ion implantation region 3-2b is formed in the lateral direction. Since the photoresist film 4d-1 having a larger width is formed in the bonding pad formation portion, the connection region 10-5, the connection conductor (bonding pad 10-
6) is formed. After this ion implantation, the photoresist film on the surface is removed and annealing is performed. This anneal is to complete the oxidation reaction and stabilize the oxygen ions, but depending on the aluminum film thickness, it should be kept at a temperature as low as 500 ° C or less for about 30 minutes so that the redistribution of oxygen ions does not occur. Just go. As a result of this annealing, the ion-implanted region 3-2b is converted into an insulating material and becomes a surface protective film 3-2C as shown in FIG. 5D. Thus, the bonding pad and the connection conductor filling the through hole can be formed simultaneously with the wiring layer in a self-aligned manner in one photoresist process.

Although the two-layer wiring structure has been described above, it will be apparent that a single-layer wiring structure and a multi-layer wiring structure of three or more layers can be realized without explaining again.

Next, a second embodiment of the present invention will be described with reference to the drawings. 7A to 7D are cross-sectional views showing the process order for explaining the second embodiment of the present invention. First, as shown in FIG. 7A, a polysilicon film 3-3 doped with impurities such as phosphorus is formed on the entire surface of the N ⁻ type silicon substrate 1 on which the diffusion layers 1B, 1C, 1E and the insulating film 2 are formed. Then, as shown in FIG. 3B, a photoresist is applied on the polysilicon film and a pattern is formed by lithography. Here, the photoresist films 4e-2 and 4e-3 having a narrow width are formed in the main wiring formation portion, and the photoresist having a wider width is formed in a portion (connection region formation portion) where a contact (connection conductor) on the polysilicon is formed. Resist films 4f-1 and 4f-2 are formed. The method of determining the width of the pattern here is the same as that described in the first embodiment. Next, as shown in FIG. 7C, rotary ion implantation and substantially vertical ion implantation are combined to implant oxygen ions 5 into the substrate obliquely from above and in the vertical direction. For example, in order to oxidize a 0.2 μm thick polysilicon film, oxygen ions 5 may be implanted at about 2 × 10 ¹⁸ / cm ² . This is beam current 100m
In case of A high current ion implanter, 8 inches for 4 inch wafer
It can be injected in about a minute. Since the distribution width in the depth direction is narrower than the normal implantation depth and the standard deviation is several tens of nanometers, the insulating portion is formed by changing the pressurizing voltage stepwise or continuously. Further, if necessary, the angle of the rotational injection may be changed stepwise or continuously to form an insulating portion having a more desired shape. Since the photoresist films 4e-2 and 4e-3 having a narrow width are formed in the main wiring forming portion, the lower portion of the polysilicon film shown in FIG. 7 is the main wiring portions 3-3a1 and 3-3.
Ion implantation regions 3-3b are formed in the upper and lateral directions remaining as a2. Since the photoresist films 4f-1 and 4f-2 having a wider width than that are formed in the connection region forming portion, the connection regions 10a-1 and 10a-3 and the connection conductors 10a-2 and 10a-4 are formed. It After this ion implantation, the photoresist film on the surface is removed and annealing is performed. This annealing is for completing the oxidation reaction and stabilizing the oxygen ions, and depending on the polysilicon film thickness, it is 500 ° C. so that the oxygen ions are not redistributed.
It may be carried out at the following temperature as low as possible for about 30 minutes. As an annealing method, there is a method using an infrared lamp irradiation called an RTA method (rapid thermal annealing method) other than a normal baking apparatus. Not only the polysilicon wiring layer 1, the interlayer insulating film, and the connection conductor can be simultaneously formed in only one photoresist process, but also the polysilicon wiring layer and the connection conductor can be formed in self-alignment, which eliminates the need for a planar margin. .

After that, the upper wiring and the bonding pad may be formed using aluminum at the same time as the first embodiment.

The example of implanting oxygen ions to form an oxide has been described above. However, nitrogen ions or oxygen ions and nitrogen ions are implanted to form a nitride (AlN, Si ₃ N 2).
₄ ) It is also possible to form some kind of oxynitride.

Not only aluminum but also Al-Si and Al-Si used as wiring materials for semiconductor devices.
An alloy containing aluminum as a main component, such as Cu, may be used.

As is clear from the above description, the size of the connecting conductor can be made finer than the limit imposed by the lithography technique.

[0032]

As described above, according to the present invention, oxygen ions and nitrogen ions are selected from a vertical direction and an oblique direction in a conductive film which can be converted into an insulator by ion implantation and annealing like aluminum or silicon. By injecting selectively, it is possible to form the wiring layer and the insulating film with the connecting conductor, which are connected to the upper wiring and the lead using a single resist film, and in this case, the connecting region between the connecting conductor and the wiring layer is formed. Since they can be self-aligned with each other, the resist process for each wiring layer can be simplified, and an alignment margin for forming a through hole is not required, so that the connection conductor can be miniaturized. Therefore, there is an effect that the degree of integration of the semiconductor device can be improved and the number of manufacturing steps can be reduced.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view for explaining a first embodiment of the present invention.

FIG. 2 is a plan view (FIG. 2A) following FIG. 1 and a cross-sectional view taken along line XX of FIG. 2A (FIG. 2B).

3 is a plan view (FIG. 3A) following FIG. 2 and a sectional view taken along line XX of FIG. 3A (FIG. 3B).

4 is a plan view (FIG. 4A) shown subsequent to FIG. 3 and FIG. 4B in a cross-sectional view taken along line XX of FIG. 4A.

5A to 5D are cross-sectional views in order of the processes, which are divided into (a) to (d) shown subsequent to FIG. 4;

FIG. 6 is a schematic diagram used to describe an embodiment of the present invention.

FIGS. 7A to 7D are sectional views in order of the processes, which are divided into (a) to (d) for describing a second embodiment of the present invention. FIGS.

FIG. 8A is a view for explaining a first conventional example.
It is a process order sectional view divided and shown to (c).

FIG. 9 is a schematic diagram used for explaining a first conventional example.

FIG. 10A is a view for explaining a second conventional example.
FIGS. 4A to 4D are cross-sectional views in the order of steps, which are separately illustrated.

[Explanation of symbols]

1 N ^- type silicon substrate 1B, 1C, 1E Diffusion layer 2 Insulating film 3, 3-1 and 3-2 Aluminum film 3-3 Polysilicon film 3a-1 to 3a-4, 3-2a1, 3-2a2, 3 -3
a1, 3-3a2, 3-3a3 Main wiring part 3-1b, 3-2b, 3-3b Ion implantation area 3-1c, 3-3c Interlayer insulating film 3-2c Surface protective film 4, 4a-1 to 4a- 4, 4b-1, 4b-2, 4c-
2, 4d-1, 4e-2, 4e-3, 4f-1, 4f-
2 Photoresist film 5 Oxygen ion 6 Ion-implanted portion 8 Surface protective film 9 Bonding pad 10-1, 10a-1, 10-3, 10a-3, 10-
5 Connection Area 10-2, 10a-2, 10-4, 10a-4 Connection Conductor 10-6 Bonding Pad (Connection Conductor) 15 Electrolyte Solution 16 Cathode 17 Electrolyzer 18 DC Power Supply 19 Anode

Claims (5)

[Claims] 1. A first wiring layer that selectively covers a first insulating film on a semiconductor substrate, and a second insulating film that covers the first insulating film on which the first wiring layer is formed. And a second wiring layer that is formed by filling the opening provided in the second insulating film and selectively covers the second insulating film, or a connection conductor connected to a lead, A semiconductor device, wherein the opening and the connection conductor are self-aligned with the first wiring layer immediately below them. 2. The first wiring layer and the connection conductor are made of the same conductive material simultaneously formed, and the second insulating film is an oxide, a nitride or an oxynitride of the conductive material. Semiconductor device. 3. The semiconductor device according to claim 2, wherein the conductive material is aluminum, an alloy containing aluminum as a main component, or silicon. 4. A step of covering a first insulating film on a semiconductor substrate to form a conductive film whose oxide, nitride or oxynitride is an insulator, and a main wiring having a first width. Forming a resist film having a forming portion and a connecting region forming portion having a second width wider than the forming portion; and a surface of the conductive coating, which is directly below the resist film and is in contact with the first insulating film. A step of implanting oxygen ions and / or nitrogen ions over a predetermined thickness from above, and all the portions of the conductive film which are not covered with the resist film and the main wiring formation portion and the connection region formation And a step of implanting oxygen ions and / or nitrogen ions from an oblique direction from the surface of the peripheral portion of the portion covered with the portion to the predetermined thickness portion, and the portion implanted with the oxygen ions and or nitrogen ions. Insulator A first wiring layer comprising a main wiring portion having a width corresponding to the first width and a connection region having a width corresponding to the second width, by self-alignment with the connection region; A method of manufacturing a semiconductor device, comprising: forming a second insulating film made of the insulator, a second wiring layer selectively covering the second insulating film, or a connection conductor connected to a lead. 5. The method of manufacturing a semiconductor device according to claim 4, wherein the conductive film is made of aluminum, an alloy containing aluminum as a main component, or silicon.