JPH0915352A - Electronic timepiece and its charging method - Google Patents

Abstract

PURPOSE: To provide an electronic timepiece using charging technology which has an improved efficiency for an accumulating means even if a capacitor which is connected in parallel with a timepiece system is small and does not cause any loss in a backward-flow diode after the timepiece system is activated. CONSTITUTION: An electronic timepiece has an energy source 1, a boosting means 2, an accumulating means 3, a clock outputting means, a constant-voltage circuit 5, a voltage detection circuit 6, a control means 7, and a switching means 8. A timepiece outputting means 4 connects a logic signal bus 202 to the control means 7 and the control means 7 connects a boosting control signal bus 200 to the boosting means 2, connects a selection signal bus 204 and a data signal bus 206 to the voltage detection circuit 6, and connects a switch control signal bus 208 to the switching means 8.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an electronic timepiece having an energy source for generating electric energy by external energy as a power source and having storage means for charging electric power generated by the energy source, and a charging method thereof.

[0002]

2. Description of the Related Art A conventional electronic timepiece having an energy source for generating electric energy by external energy as a power source and a storage means for charging the generated power of the energy source is disclosed in, for example, Japanese Patent Publication No. 4-81754. There is an electronic clock.

FIG. 13 is a circuit diagram of a charging circuit of a conventional electronic timepiece disclosed in Japanese Patent Publication No. 4-81745. FIG.
2 is a waveform diagram of a control signal of the conventional charging circuit shown in FIG. 13, and FIG. 12 (a) shows a capacitor C1 and a capacitor C.
FIG. 12B is a waveform diagram showing a state in which charging with 2 is alternately performed in synchronization with the drive signal, and FIG. 12B is a waveform diagram showing a state in which the capacitor C1 is continuously charged for two drive signals. Is.

First, the configuration of the charging circuit which constitutes the conventional electronic timepiece will be described with reference to FIG. A charging circuit that constitutes an electronic timepiece of a conventional example includes a power source SC that is a solar cell that is an energy source, a large-capacity capacitor C1 such as a charge double layer capacitor that is a storage unit, and a timepiece circuit (not shown).
A small capacity capacitor C2 connected in parallel to the switch, a switch SW1 connecting the capacitors C1 and C2, and a switch SW2 connecting the capacitor C1 and the power supply SC.
And a backflow prevention diode D1 inserted in a closed circuit composed of the power supply SC and the capacitor C1, and a backflow prevention diode D2 inserted in a closed circuit composed of the power supply SC and the capacitor C2.

Further, the clock circuit has a voltage detection circuit (not shown) for detecting the charging voltage of the capacitors C1 and C2, and a control circuit (not shown) for controlling the switches SW1 and SW2. doing.

The operation of the charging circuit will be described below with reference to the circuit diagram of the conventional charging circuit shown in FIG. 13 and the waveform diagram shown in FIG.

The signals shown in FIG. 12 are generated once per second to move the display mechanism of the timepiece and drive signal for driving the step motor and drive signal for detecting the charging voltage of the capacitors C1 and C2. A detection control signal for controlling the voltage detection circuit synchronized with the signal, and a SW1 control signal and a SW2 control signal synchronized with the drive signal for controlling the switches SW1 and SW2 are generated.

In the initial state, as shown in FIG.
The switches SW1 and SW2 are open, and no charging voltage is generated in the capacitors C1 and C2.

Therefore, when the solar cell SC is exposed to light, the power source SC, the capacitor C2 and the diode D2 form a closed circuit, the capacitor C2 is charged through the diode D2 and the capacitor C2 is charged at a certain voltage or more. The clock circuit, the voltage detection circuit that constitutes the clock circuit, and the control circuit that controls the switches SW1 and SW2 operate.

For example, when the charging voltage of the capacitor C2 becomes 2 volts or more, the voltage detecting circuit closes the switch SW2 via the control circuit, and the state shown in FIG. 13 (b) is obtained.

At time t1, when the detection voltage of the capacitor C2 exceeds 2 volts, a detection signal is generated and the switch SW2 is closed by the SW2 control signal to charge the uncharged capacitor C1.

Next, at the time t2, when the detection voltage of the capacitor C2 becomes 2 volts or less, no detection signal is generated, the switch SW2 opens and the state shown in FIG. 13 (a) is reached, and the time t1 and the time t2. Between and, almost only the capacitor C1 is charged.

Next, at time t3, when the detection voltage of the capacitor C2 becomes 2 volts or more, a detection signal is generated,
The switch SW2 is closed and the state shown in FIG. Only the capacitor C2 is charged between the time t2 and the time t3, and the capacitor C1 is charged again from the time t3. Thus, the capacitors C1 and C2 are alternately charged every second.

Further, when the charging voltage of the capacitor C1 becomes 2 volts or more, the voltage detection circuit closes the switches SW1 and SW2 through the control circuit, and the voltage detection circuit shown in FIG.
As shown in (c), the capacitors C1 and C2 are connected in parallel and charged at the same time.

The drive waveform of FIG. 12 (b) detects that the detection voltage of the capacitor C2 is 2 V or less at time t1, opens the switch SW2, and becomes the state of FIG. 13 (a). The capacitor C2 is charged from time t1.

Next, at time t2, when the detection voltage of the capacitor C2 becomes 2 volts or more, a detection signal is generated,
The switch SW2 is closed to enter the state shown in FIG. 13B, the capacitor C2 is charged between the time t1 and the time t2, and the time t
The capacitor C1 is charged from 2.

Next, at time t3, if the detection voltage of the capacitor C2 is still 2 V or higher, a detection signal is generated and the switch SW2 remains closed.
The state of (b) is continued, and the capacitor C1 is charged between time t2 and time t3 and after time t3.

Next, at the time t4, it is detected that the detection voltage of the capacitor C2 is 2 V or less, the switch SW2 is opened and the state of FIG.
To charge the capacitor C2.

When the charging voltage of the capacitor C1 becomes 2 volts or more, the voltage detecting circuit closes the switch SW1 and the switch SW2 via the control circuit, as shown in FIG. 13 (c).
As described above, the capacitors C1 and C2 are connected in parallel and charged at the same time.

[0020]

However, in the conventional charging circuit, when the capacitance of the capacitor C2 is reduced,
As shown in FIG. 12A, one second between time t1 and time t2 is the charging period of the capacitor C1.
Since one second between 2 and t3 is the charging period of the capacitor C2, there is a problem that only half of the generated power of the energy source can charge the capacitor C1 which is the storage means.

Further, the time from t2 to t3 is applied to the capacitor C2.
In order to supply the pulse motor drive power for two times of the drive signals P3 and P4 with the power charged in one second, the capacitance value of the capacitor C2 needs to be increased to some extent, and therefore the capacitor C2 is charged. There is a problem that the time required to reach the minimum operating voltage of the timepiece circuit becomes long and the self-starting property of the timepiece deteriorates.

As shown in FIG. 12 (b), if the charging time of the capacitor C1 which is the storage means is to be increased, the capacitor C2 has three pulse motor driving powers synchronized with the driving signals P2, P3 and P4. Therefore, there is a problem in that the capacitance value of the capacitor C2 needs to be further increased, and the time for charging the capacitor C2 to reach the minimum operating voltage of the timepiece circuit becomes longer.

Further, since the backflow prevention diodes D1 and D2 are always inserted in the circuit, there is a problem that the loss due to D1 and D2 cannot be ignored when the power generated by the power supply SC is small.

Therefore, an object of the present invention is to solve the above-mentioned problems, and even if the capacitor connected in parallel to the timepiece circuit is small, the efficiency of the storage means is high, and after the timepiece circuit is activated, the loss of the reverse current diode is reduced. It is to provide an electronic timepiece that uses no charging technology.

[0025]

In order to achieve the above object, the electronic timepiece of the present invention has the following configuration.

An energy source that outputs a generated voltage to a power supply voltage signal by external energy, a boosting unit that outputs a boosted voltage to the boosted voltage signal by a boosting control signal bus from the power supply voltage signal, and a boosted voltage of the boosted voltage signal. Storage means for storing via the switch means, clock output means for outputting a plurality of logic signals by inputting the voltage of the power supply voltage signal, the boosted voltage signal or the stored voltage signal to the clock voltage signal via the switch means, A constant voltage circuit that outputs a reference voltage from the voltage of the clock voltage signal, and a voltage of the power supply voltage signal, the boost voltage signal, the storage voltage signal, and the clock voltage signal is selected, and the voltage detection signal is output by the data signal bus and the data signal bus. The voltage detection circuit and the plurality of logic signals and the voltage detection signals are used to switch the boost control signal bus, the selection signal bus, the data signal bus, and the switch. Control means for outputting a control signal bus, and having a switch means having a plurality of switches for controlling the charging time of the switch control signal bus to the storage means and the clock output means.

Further, the voltage detection circuit has a transmission gate for selecting the voltage of the power supply voltage signal, the boosted voltage signal, the storage voltage signal and the clock voltage signal by the signal of the selection signal bus and a resistor for dividing the selected voltage into two. Multiple inverters in which the voltage divider circuit and the reference voltage of the constant voltage circuit are used as the low-potential side power supply, and resistors of the same value are connected to the high-potential side and the low-potential side for the output, and the data signal bus is connected to the input. And a D / A conversion circuit including a comparator, the resistance value of each inverter is set to a multiple of 2 in order, and the output of each inverter is connected to the inverting input terminal of the comparator, The output of the voltage dividing circuit is connected to the non-inverting input terminal of the comparator.

The control means includes a voltage detection control circuit for outputting a selection signal bus and a data signal bus for controlling the voltage detection circuit by the logic signal bus, a voltage detection signal, a selection signal bus, and a logic signal bus. A step-up control circuit that outputs a step-up control signal bus for controlling the step-up means, a pulse width control circuit, and a storage means and a clock by controlling the switch means by the voltage detection signal, the selection signal bus, and the logic signal bus. And a switch control circuit for outputting a switch control signal bus for controlling the charging time to the output means.

The switch means is connected to the first switch control signal output from the control means and is located between the boosted voltage signal and the accumulated voltage signal, and the second switch output from the control means. The switch control signal is connected and the second switch located between the accumulated voltage signal and the clock voltage signal is connected to the third switch control signal output by the control means to connect the boost voltage signal and the clock voltage signal. Third located between
Switch, the fourth switch control signal output from the control means is connected to the fourth switch, which is positioned between the power supply voltage signal and the clock voltage signal, and the backflow prevention diode connected in parallel to the fourth switch. It is characterized by including.

The method of charging the electronic timepiece of the present invention is the method described below.

An energy source for outputting a generated voltage to a power supply voltage signal by external energy, a boosting means for outputting a voltage of the power supply voltage signal to a boost voltage signal by a boost control signal bus, and a boost voltage of the boost voltage signal. Storage means for storing via the switch means, clock output means for outputting a plurality of logic signals by inputting the voltage of the power supply voltage signal, the boosted voltage signal or the stored voltage signal to the clock voltage signal via the switch means, A constant voltage circuit that outputs a reference voltage from the voltage of the clock voltage signal, and a voltage of the power supply voltage signal, the boost voltage signal, the storage voltage signal, and the clock voltage signal is selected, and the voltage detection signal is output by the data signal bus and the data signal bus. The voltage detection circuit and the plurality of logic signals and the voltage detection signals are used to switch the boost control signal bus, the selection signal bus, the data signal bus, and the switch. The clock output means has a control means for outputting a control signal bus and a switch means having a plurality of switches for controlling charging time to the storage means and the timepiece output means by the switch control signal bus. When the voltage becomes a constant voltage, the logic signal bus is output to the control means, and the voltage detection control circuit forming the control means outputs the selection signal bus to the voltage dividing circuit forming the voltage detection circuit according to the signal of the logic signal bus. Then, the data signal bus corresponding to the selection signal bus is output to the D / A conversion circuit forming the voltage detection circuit, and the voltage value selected by the selection signal bus is changed to D / A.
The voltage detection signal is output to the boost control circuit and the switch control circuit which are detected by the A conversion circuit and constitute the control means, and the boost control circuit outputs the voltage detection signal, the second selection signal and the fourth selection signal of the selection signal bus. A boost control signal bus is output to the boosting means by the signal and the switch control circuit configures the switch control circuit by the voltage detection signal, the first selection signal of the selection signal bus, the third selection signal, and the fourth selection signal. The switch control signal bus is output to the switch means by controlling the pulse width control circuit for controlling the charging time to the storage means and the timepiece output means.

Further, when the voltage of the accumulated voltage signal is equal to or lower than the constant voltage and the voltage of the clock voltage signal is equal to or lower than the constant voltage, the switch control circuit causes the voltage detection signal, the first selection signal and the third selection signal of the selection signal bus. The pulse width control circuit forming the switch control circuit is controlled as a down counter by the signal and the fourth selection signal, and the conduction of the first switch located between the boosted voltage signal forming the switch means and the accumulated voltage signal. The control is performed so that the time is reduced and the conduction time of the third switch, which is located between the boosted voltage signal and the clock voltage signal that constitutes the switch means, is increased.

When the voltage of the accumulated voltage signal is equal to or lower than the fixed voltage and the voltage of the clock voltage signal is equal to or higher than the fixed voltage, the switch control circuit causes the voltage detection signal, the third selection signal and the fourth selection signal of the selection signal bus. The pulse width control circuit forming the switch control circuit is controlled by the signal as an up-counter to increase the conduction time of the first switch located between the boosted voltage signal forming the switch means and the accumulated voltage signal. Is controlled to reduce the conduction time of the third switch located between the boosted voltage signal and the clock voltage signal.

When the voltage of the accumulated voltage signal is less than the constant voltage and the voltage of the boosted voltage signal is less than the constant voltage, the switch control circuit causes the voltage detection signal, the second selection signal of the selection signal bus, and the third selection signal. The fourth switch located between the power supply voltage signal and the clock voltage signal forming the switch means is made conductive by the signal and the fourth selection signal, and the backflow prevention diode is short-circuited. To do.

When the voltage of the accumulated voltage signal is equal to or lower than the constant voltage and the voltage of the boosted voltage signal is equal to or higher than the constant voltage, the switch control circuit uses the voltage detection signal and the second selection signal of the selection signal bus to switch the switching means. It is characterized in that the fourth switch located between the power supply voltage signal and the clock voltage signal, which constitutes the above, is made non-conducting and the backflow prevention diode is inserted.

Further, when the voltage of the accumulated voltage signal is equal to or higher than a certain voltage, the switch control circuit deselects the pulse width control circuit forming the switch control circuit by the voltage detection signal and the third selection signal of the selection signal bus. The second switch located between the storage means and the timepiece output means forming the switch means is rendered conductive, and the fourth switch located between the energy source and the timepiece output means is rendered non-conductive to prevent backflow. It is characterized by controlling so as to insert a diode.

[0037]

The timepiece output means outputs the logic signal bus to the control means when the voltage of the power supply voltage signal becomes a constant voltage, and the voltage detection control circuit forming the control means changes the voltage of the selection signal bus to the voltage by the signal of the logic signal bus. The voltage is output to the voltage divider circuit that constitutes the detection circuit.

The data signal bus corresponding to the selection signal bus is output to the D / A conversion circuit forming the voltage detection circuit, and the voltage value selected by the selection signal bus is detected by the D / A conversion circuit to form the control means. The boosting control circuit outputs a voltage detection signal to the boosting control circuit and the switch control circuit, and the boosting control circuit sends the boosting control signal bus to the boosting means by the voltage detection signal and the second selection signal and the fourth selection signal of the selection signal bus. Output.

When the voltage of the accumulated voltage signal is equal to or lower than the constant voltage and the voltage of the clock voltage signal is equal to or lower than the constant voltage, the switch control circuit outputs the voltage detection signal, the first selection signal of the selection signal bus, and the third selection signal. The pulse width control circuit forming the switch control circuit is controlled by the fourth selection signal as a down counter, and the conduction time of the first switch located between the boosted voltage signal and the accumulated voltage signal forming the switch means is controlled. The control is performed so as to decrease and increase the conduction time of the third switch located between the boosted voltage signal and the clock voltage signal forming the switch means.

When the voltage of the accumulated voltage signal is equal to or lower than the constant voltage and the voltage of the clock voltage signal is equal to or higher than the constant voltage, the switch control circuit causes the voltage detection signal, the third selection signal of the selection signal bus, and the fourth selection signal. The pulse width control circuit forming the switch control circuit is controlled by the signal as an up-counter to increase the conduction time of the first switch located between the boosted voltage signal forming the switch means and the accumulated voltage signal. Is controlled so as to reduce the conduction time of the third switch located between the boosted voltage signal and the clock voltage signal.

When the voltage of the accumulated voltage signal is equal to or lower than the fixed voltage and the voltage of the boosted voltage signal is equal to or lower than the fixed voltage, the switch control circuit outputs the voltage detection signal, the second selection signal of the selection signal bus, and the third selection signal. By the fourth selection signal, the fourth switch located between the power supply voltage signal and the clock voltage signal forming the switch means is turned on, and the backflow prevention diode is controlled to be short-circuited.

When the voltage of the accumulated voltage signal is equal to or lower than the fixed voltage and the voltage of the boosted voltage signal is equal to or higher than the fixed voltage, the switch control circuit forms the switch means by the voltage detection signal and the second selection signal of the selection signal bus. The fourth switch located between the power supply voltage signal and the clock voltage signal is turned off and the backflow prevention diode is inserted.

When the voltage of the accumulated voltage signal is equal to or higher than a certain voltage, the switch control circuit sets the pulse width control circuit constituting the switch control circuit to the non-selected state by the voltage detection signal and the third selection signal of the selection signal bus, The second switch located between the storage means and the timepiece output means forming the switch means is made conductive, the fourth switch located between the energy source and the timepiece output means is made nonconductive, and the backflow prevention diode is connected. Control to insert.

In accordance with the output of the voltage detection circuit for detecting the voltage of the clock output means, it is possible to automatically lengthen or shorten the charging time for the storage means, thus improving the charging efficiency. .

Further, when the voltage of the accumulated voltage signal is equal to or lower than the constant voltage and the voltage of the boosted voltage signal is equal to or higher than the constant voltage, the fourth switch is made non-conductive and a reverse current prevention diode is inserted to control the accumulated voltage. When the voltage of the signal is below a certain voltage and the voltage of the boost voltage signal is below a certain voltage, the fourth
By controlling the switch to be conductive and the backflow prevention diode to be short-circuited, the generated power can be used more efficiently.

[0046]

Embodiments of the present invention will be described below with reference to the drawings. 1 is a block diagram showing a circuit configuration of an electronic timepiece according to an embodiment of the present invention.

First, the structure of the electronic timepiece according to the embodiment of the present invention will be described with reference to FIG. The electronic timepiece according to the embodiment of the present invention includes an energy source 1, a boosting unit 2, and a storage unit 3.
It comprises a clock output means 4, a constant voltage circuit 5, a voltage detection circuit 6, a control means 7 and a switch means 8.

The high potential side of the energy source 1 is the ground, and the ground signal 19 of the energy source 1 is the voltage boosting means 2.
It is connected to the storage means 3, the clock output means 4, the constant voltage circuit 5, the voltage detection circuit 6 and the control means 7.

The low potential side of the energy source 1 is the generated voltage of the energy source 1, and the power supply voltage signal 18 of the energy source 1 is connected to the boosting means 2, the voltage detection circuit 6 and the switch means 8. There is.

Further, the boosted voltage signal 17 of the boosting means 2 is
The voltage detection circuit 6 is connected to the switch means 8, and the accumulated voltage signal 35 of the storage means 3 is connected to the voltage detection circuit 6 and the switch means 8.

Further, the clock voltage signal 36 of the clock output means 4
Is connected to the constant voltage circuit 5, the voltage detection circuit 6, the control means 7, and the switch means 8.

The reference voltage signal 46 of the constant voltage circuit 5 is connected to the voltage detection circuit 6, and the voltage detection signal 69 of the voltage detection circuit 6 is connected to the control means 7.

Further, the logic signal bus 202 of the clock output means 4 is connected to the control means 7, the boost control signal bus 200 of the control means 7 is connected to the boost means 2, and the data signal bus 206 of the control means 7 and the selection signal. The bus 204 is connected to the voltage detection circuit 6, and the switch control signal bus 2 of the control means 7 is connected.
08 is connected to the switch means 8.

Energy source 1 used in the embodiment of the present invention
Is a thermoelectric generator that generates electricity according to the Seebeck effect principle, and is a module (not shown) in which a large number of thermoelectron pairs connecting a P-type semiconductor material and an N-type semiconductor material in series are combined.

The thermoelectric generator uses one as a hot electrode and the other as a cold electrode to generate power by giving a temperature difference, and to use as a power source for a wristwatch, for example, the back side in contact with human skin inside the watch is the hot electrode. , The front side in contact with the atmosphere is a cold pole.

Next, the circuit configuration of each block constituting the electronic timepiece of the present invention will be described with reference to the drawings. FIG. 2 is a circuit diagram showing an internal configuration of the energy source 1 and the boosting means 2 in the embodiment of the present invention.

The energy source 1 shown in FIG. 2 is a thermoelectric generator in which a large number of thermoelectron pairs are combined, and is equivalently represented by a voltage source 20 and an internal resistance 21, and the clock output means 4 shown in FIG. Thousands of thermionic pairs are used to obtain an open circuit voltage of about 1 to 2 volts required for activation, and an internal resistance 21
Is a power source that can reach several tens of kilohms or more.

The internal resistance 21 of the energy source 1 shown in FIG.
Is connected to the high potential side with respect to the voltage source 20, but this is merely expressed equivalently, and it is generally considered that the voltage is distributed evenly inside the voltage source 20. .

The boosting means 2 shown in FIG. 2 is composed of a first boosting circuit 15 and a second boosting circuit 16, and will be described below as a first boosting circuit 15 and a second boosting circuit 16. The configuration of will be described.

The first booster circuit 15 and the second booster circuit 16 shown in FIG. 2 are booster circuits having the same structure,
First capacity 22, second capacity 23 and first N channel M
OS transistor (hereinafter referred to as N-MOST) 24
And a second N-MOST 25, a third N-MOST 26, a fourth N-MOST 27, and a P-channel MOS transistor (hereinafter referred to as P-MOST) 28.

Next, the connection configuration of the components of the first booster circuit 15 and the second booster circuit 16 will be described.

The ground signal 19 of the energy source 1 is connected to one terminal of the first capacitor 22 and one terminal of the P-MOST 28 which form the first booster circuit 15 and the second booster circuit 16. , Power source voltage signal 18 of energy source 1
Is a first N-MOST 24 and a second N-MOST 25 that constitute the first booster circuit 15 and the second booster circuit 16.
It is connected to one of the terminals.

First booster circuit 15 and second booster circuit 16
And the other terminal of the first capacitor 22 constituting
-The other terminal of the MOST 24 and the third N-MOST 26
It is connected to one of the terminals.

First booster circuit 15 and second booster circuit 16
The other terminal of the P-MOST 28 constituting the above is connected to the other terminal of the third N-MOST 26 and one terminal of the second capacitor 23.

First booster circuit 15 and second booster circuit 16
And the other terminal of the second capacitor 23 constituting
-The other terminal of the MOST 25 and the fourth N-MOST 27
It is connected to one of the terminals.

First booster circuit 15 and second booster circuit 16
And the other terminal of the fourth N-MOST 27 that forms
Each of them is connected to the boosted voltage signal 17 of the boosting means 2.

The first N- which constitutes the first booster circuit 15
The gate terminals of the MOST 24 and the second N-MOST 25 are the third N-MOST which constitutes the second booster circuit 16.
26, the fourth N-MOST 27, and the P-MOST 28 are connected to the gate terminals of the boost control signal bus 20 shown in FIG.
0 connected to a first boost control signal 10.

In addition, the third booster circuit 15 constituting the first booster circuit 15
N-MOST 26, fourth N-MOST 27 and PM
The gate terminal of the OST 28 is connected to the first N-MOST 24 and the second N-MOST 2 which form the second booster circuit 16.
5 and the second boost control signal 11 forming the boost control signal bus 200 shown in FIG.

FIG. 3 shows the storage means 3 in the embodiment of the present invention.
FIG. 3 is a circuit diagram showing an internal configuration of a clock output means 4 and a switch means 8.

The storage means 3 shown in FIG. 3 is a rechargeable secondary battery 43, and the timepiece output means 4 is a timepiece system 4.
2 and a small capacitor 41 connected in parallel to the timepiece system 42 to stabilize the power supply of the timepiece system 42. The storage means 3 and the timepiece output means 4 are connected to the power supply terminals on the high potential side as shown in FIG. The ground signal 19 of the energy source 1 shown in is connected.

Although the internal structure of the timepiece system 42 is not shown, it is a general crystal timepiece including a crystal oscillation circuit, a frequency dividing circuit, a waveform generating circuit, a drive circuit, a step motor, a train wheel, a display and the like.

The switch means 8 shown in FIG. 3 comprises a first switch 30, a second switch 31, a third switch 32, a fourth switch 33 and a backflow prevention diode 34, and each switch is N-. It is MOST.

One terminal of the first switch 30 and one terminal of the third switch 32 are connected to the boosting means 2 shown in FIG.
, And the other terminal of the first switch 30 and one terminal of the second switch 31 are connected to the stored voltage signal 35 which is the low potential side of the storage means 3.

One terminal of the fourth switch 33 and the cathode terminal of the backflow prevention diode 34 are connected to the power supply voltage signal 18 of the energy source 1 shown in FIG.

The other terminal of the second switch 31, the other terminal of the third switch 32, the other terminal of the fourth switch, and the anode terminal of the backflow prevention diode 34 are the watch voltage signal of the watch output means 4. Connected to 36.

The gate terminal of the first switch 30 is shown in FIG.
The switch control signal bus 208 shown in FIG. 1 is connected to the first switch control signal 38, and the gate terminal of the second switch 31 is connected to the second switch control signal 37 shown in FIG. Connected to.

Further, the gate terminal of the third switch 32 is connected to the third switch control signal 39 forming the switch control signal bus 208 shown in FIG. 1, and the gate terminal of the fourth switch 33 is shown in FIG. The switch control signal bus 208 shown in FIG.

Further, the clock output means 4 outputs the logic signal bus 202 to the control means 7 as shown in FIG.

FIG. 4 is a circuit diagram showing the internal structures of the constant voltage circuit 5 and the voltage detection circuit 6 in the embodiment of the present invention. The constant voltage circuit 5 shown in FIG. 4 is a general constant voltage circuit, and includes N-MOST49 and N-MOST50 having the same structure, P-MOST47 and P-MOST48 having the same structure, and a resistor 5.
1, an operational amplifier 44, and a capacitor 45.

One terminal of the P-MOST 47 has a resistor 5
2 through the ground signal 1 of the energy source 1 shown in FIG.
9, and one terminal of the P-MOST 48 is connected to the ground signal 19 of the energy source 1 shown in FIG.

One terminals of the N-MOST 49 and the N-MOST 50 are connected to the clock voltage signal 36 of the clock output means 4 shown in FIG. 1, and the N-MOST 49 and the N-MOST 50 are connected.
The gate terminals of and are the other terminal of the N-MOST 49,
Connected to the other terminal of P-MOST47, N-MOST
The other terminal of 50 is connected to the other terminal of the P-MOST 48 and the gate terminals of the P-MOST 47 and the P-MOST 48.

The reference voltage generated at the connection point where the other terminal of the N-MOST 50 and the other terminal of the P-MOST 48 are connected to each other has a low impedance by using the operational amplifier 44 to make a voltage flow. The reference voltage signal 46 is supplied to the D / A which constitutes the voltage detection circuit 6 described later
It is connected to the power supply terminal of the conversion circuit 77.

The capacitor 45 connected between the output terminal of the operational amplifier 44 and the ground signal 19 is for stabilizing the reference voltage signal 46.

The voltage detection circuit 6 shown in FIG. 4 comprises a voltage dividing circuit 75 and a D / A conversion circuit 77. The voltage divider circuit 75 of the voltage detection circuit 6 shown in FIG. 4 includes a first resistor 81 and a second resistor 82 having the same resistance value, a first transmission gate (hereinafter referred to as TG) 83, and a second resistor 82. T
It is composed of a G84, a third TG85 and a fourth TG86.

One terminal of the first resistor 81 is connected to the ground signal 19 of the energy source 1 shown in FIG. 2, and the other terminal of the first resistor 81 is connected to one terminal of the second resistor 82. And the other terminal of the second resistor 82 is connected to the first TG
83, second TG 84, third TG 85, and fourth TG 8
6 is connected to one of the input / output terminals.

The other input / output terminal of the first TG 83 is connected to the clock voltage signal 36 shown in FIG.
The other input / output terminal of 84 is connected to the accumulated voltage signal 3 shown in FIG.
5, the other input / output terminal of the third TG 85 is connected to the boost voltage signal 17 shown in FIG. 2, and the other input / output terminal of the fourth TG 86 is connected to the power supply voltage signal 18 shown in FIG. Connected.

The control terminal of the first TG 83 is shown in FIG.
Selection signal 9 constituting the selection signal bus 204 shown in FIG.
3 and the control terminal of the second TG 84 is connected to the third selection signal 92 forming the selection signal bus 204 shown in FIG. 1, and the control terminal of the third TG 85 is connected to the selection signal shown in FIG. Connected to the second selection signal 91 that constitutes the bus 204,
The control terminal of the fourth TG 86 is connected to the first selection signal 90 forming the selection signal bus 204 shown in FIG.

Further, the first resistor 81 and the second resistor 82
The comparison reference voltage signal, which is the connection point with
It is connected to the non-inverting input terminal of the comparator 68 that constitutes the conversion circuit 77.

The D / A conversion circuit 77 of the voltage detection circuit 6 shown in FIG. 4 includes a first inverter 60 and a second inverter 6
1 and a third inverter 62, a fourth inverter 63 and a comparator 68, the comparator 68,
The ground signal 19 of the energy source 1 shown in and the clock voltage signal 36 shown in FIG. 3 are used as power sources.

Further, the four inverters 60, 61, 62 and 63 forming the D / A conversion circuit 77 have the same structure, and P
-MOST55, N-MOST56, a third resistor 57 and a fourth resistor 58, the third resistor 57 and the fourth resistor 58 have the same resistance value, and are different depending on each inverter. It has a resistance value.

In the embodiment of the present invention, the first inverter 6
The resistance value of the third resistor 57 and the fourth resistor 58 forming 0 is 1M ohm, and the resistance value of the third resistor 57 and the fourth resistor 58 forming the second inverter 61 is 2M ohm. And the third resistor 5 constituting the third inverter 62
The resistance value between 7 and the fourth resistor 58 is 4M ohm,
The resistance values of the third resistance 57 and the fourth resistance 58 that form the inverter 63 are set to 8M ohms.

Four inverters 60, 61, 62, 63
2 is connected to the ground signal 19 of the energy source 1 shown in FIG.
The other terminal of the OST 55 is connected to one terminal of the third resistor 57, the other terminal of the third resistor 57 is connected to one terminal of the fourth resistor 58, and the other terminal of the fourth resistor 58 is connected. The other terminal is connected to the other terminal of the N-MOST 56,
One terminal of the MOST 56 is connected to the reference voltage signal 46 which is the output of the constant voltage circuit 5.

The four inverters 60, 61, 6
The connection points of the third resistor 57 and the fourth resistor 58, which form 2, 63, are connected to each other, and are connected to the inverting input terminal of the comparator 68.

In addition, P which constitutes the first inverter 60
-The gate terminals of MOST 55 and N-MOST 56 are
The gate terminals of the P-MOST 55 and the N-MOST 56 that are connected to the first data signal 94 that forms the data signal bus 206 shown in FIG. 1 and that form the second inverter 61 are the data signal bus 206 shown in FIG. Is connected to the second data signal 95 which constitutes

Further, P which constitutes the third inverter 62
-The gate terminals of MOST 55 and N-MOST 56 are
The gate terminals of the P-MOST 55 and the N-MOST 56, which are connected to the third data signal 96 forming the data signal bus 206 shown in FIG. 1 and forming the fourth inverter 63, have the data signal bus 206 shown in FIG. Is connected to the fourth data signal 97 which constitutes

Further, the voltage detection signal 69 output from the comparator 68 is connected to the control means 7 as shown in FIG.

FIG. 5 is a table showing the relationship between the input signal and the output voltage of the D / A conversion circuit 77 of the voltage detection circuit 6 in the embodiment of the present invention. The four data signals 94, 95, 96,
FIG. 9 is a diagram showing a ratio of the potential output to the inverting input terminal of the comparator 68 corresponding to the data of 97 when the potential of the reference voltage signal 46 is “1”.

D1 shown in FIG. 5 corresponds to the first data signal 94 shown in FIG. 4, D2 corresponds to the second data signal 95, D3 corresponds to the third data signal 96, and D4 is the first data signal 96. Four
The voltage of the inverting input terminal of the comparator 68 that constitutes the D / A conversion circuit 77 corresponding to the data signal 97 of FIG. 2 can take 16 different output levels depending on the data of the data signals 94, 95, 96 and 97.

FIG. 6 is a circuit diagram showing the internal structure of the control means 7 shown in FIG. The control means shown in FIG. 6 includes a voltage detection control circuit 122, a boost control circuit 123, and a switch control circuit 124.

The voltage detection control circuit 122 constituting the control means shown in FIG. 6 includes a ring counter 100 and four data FFs (hereinafter referred to as DFFs) 101, 102 and 10.
3, 104 and four 2-input AND circuits 105, 10
6, 107, 108 and two 2-input OR circuits 111,
113, 4-input NOR circuit 112, and data output circuit 1
It is composed of 10.

The booster control circuit 123 constituting the control means shown in FIG. 6 includes two inverters 121 and 137, three two-input AND circuits 125, 136 and 138, and a set / reset FF (hereinafter referred to as SRFF) 132. It consists of and.

The switch control circuit 124 constituting the control means shown in FIG. 6 includes two inverters 142 and 146,
Eight 2-input AND circuits 126, 127, 128, 12
9, 130, 131, 144, 147 and 3 SRFs
F133, 134, 135 and 2-input OR circuit 145
And 3-input AND circuit 148 and pulse width control circuit 14
9.

The clock input terminal of the ring counter 100 constituting the voltage detection control circuit 122 is connected to the first logic signal 70 constituting the logic signal bus 202 output by the clock output means 4 shown in FIG.

The output Q1 of the ring counter 100 is the first
Connected to the data input terminal of the DFF 101 and one input terminal of the first 2-input AND circuit 105, and the output Q2 of the ring counter 100 is connected to the data input terminal of the second DFF 102 and the second 2-input AND circuit 106. It is connected to one of the input terminals.

The output Q3 of the ring counter 100 is the third
Connected to the data input terminal of the DFF 103 and one input terminal of the third 2-input AND circuit 107, and the output Q4 of the ring counter 100 is connected to the data input terminal of the fourth DFF 104 and the fourth 2-input AND circuit 108. It is connected to one of the input terminals.

The four DFFs 101, 102, 103 and 1
The clock input terminal 04 is connected to the second logic signal 71 forming the logic signal bus 202 shown in FIG.

The inverted output of the first DFF 101 is connected to the other input terminal of the first 2-input AND circuit 105, and the inverted output of the second DFF 102 is input to the other input of the second 2-input AND circuit 106. Connected to the terminal, the third DFF10
The inverted output of 3 is connected to the other input terminal of the third 2-input AND circuit 107, and the inverted output of the fourth DFF 104 is connected to the other input terminal of the fourth 2-input AND circuit 108. .

The first selection signal 90 output from the first 2-input AND circuit 105 is the first 2-input OR circuit 111.
One input terminal, one input terminal of the twelfth two-input AND circuit 130 and the thirteenth two-input AND circuit 131 which configure the switch control circuit 124, and the voltage component of the voltage detection circuit 6 shown in FIG. Fourth TG8 constituting the pressure circuit 75
6 control terminals.

The second selection signal 91 output from the second 2-input AND circuit 106 is the first 2-input OR circuit 111.
4 and one input terminal of a fifth two-input AND circuit 125 that constitutes the boost control circuit 123, and FIG.
Is connected to the control terminal of the third TG 85 forming the voltage dividing circuit 75 of the voltage detection circuit 6 shown in FIG.

The third selection signal 92 output from the third two-input AND circuit 107 is the second two-input OR circuit 113.
One input terminal, one input terminal of the tenth two-input AND circuit 128 and the eleventh two-input AND circuit 129 which form the switch control circuit 124, and the voltage component of the voltage detection circuit 6 shown in FIG. Second TG8 constituting the pressure circuit 75
4 control terminal.

The fourth selection signal 93 output from the fourth 2-input AND circuit 108 is the second 2-input OR circuit 113.
The other input terminal, one input terminal of the eighth two-input AND circuit 126 and the ninth two-input AND circuit 127 configuring the switch control circuit 124, and the switch control circuit 1
24 is connected to the load terminal of the pulse width control circuit 149 and the control terminal of the first TG 83 that constitutes the voltage divider circuit 75 of the voltage detection circuit 6 shown in FIG.

Further, the respective selection signals 90, 91, 9
2, 93 are connected to respective input terminals of the 4-input NOR circuit 112, and output 114 of the first 2-input OR circuit 111
The output 116 of the second 2-input OR circuit 113 and the output 115 of the 4-input NOR circuit 113 are connected to the data output circuit 110.

The data output circuit 110 outputs four data signals 94, 95, 96 and 97 and outputs four data signals 9
4, 95, 96, and 97 are four inverters 60 that form the D / A conversion circuit 77 of the voltage detection circuit 6 shown in FIG.
The gate terminals of 61, 62, and 63 are respectively connected.

Four selection signals 90, 91, 92, 93
Represents the select signal bus 204 shown in FIG. 1, and the four data signals 94, 95, 96, 97 represent the data signal bus 206 shown in FIG.

One of the input terminals of the sixth two-input AND circuit 136 and the input terminal of the sixth inverter 137 which constitute the boost control circuit 123 are the logic signal bus 202 output by the timepiece output means 4 shown in FIG. And the output of the sixth inverter 137 is connected to one input terminal of the seventh two-input AND circuit 138.

The input terminal of the fifth inverter 121 which constitutes the step-up control circuit 123, the eighth two-input AND circuit 126, the tenth two-input AND circuit 128 and the twelfth two input which constitute the switch control circuit 124. AND circuit 130
The other input terminals of and are connected to the voltage detection signal 69 output from the comparator 68 included in the D / A conversion circuit 77 of the voltage detection circuit 6 shown in FIG.

The output of the fifth inverter 121 is the fifth two-input AND circuit 125 which constitutes the boost control circuit 123.
Are connected to the other input terminals of the ninth two-input AND circuit 127, the eleventh two-input AND circuit 129, and the thirteenth two-input AND circuit 131, respectively, which configure the switch control circuit 124.

The output of the fifth 2-input AND circuit 125 is
The set terminal of the first SRFF 132 is connected to the reset terminal of the first SRFF 132, and the switch control circuit 12
4 is connected to the output of the eighth 2-input AND circuit 126 and the set terminal of the second SRFF 133.

The output of the first SRFF 132 is the second 2
Input AND circuit 136 and seventh 2-input AND circuit 138
, And the inverted output of the first SRFF 132 is connected to the first input terminal of a 3-input AND circuit 148 that constitutes the switch control circuit 124.

The output of the sixth 2-input AND circuit 136 is the first boost control signal 10, and the output of the seventh AND circuit 138 is the second boost control signal 11, which is the same as the first boost control signal 10 and the first boost control signal 10. The boosting control signal 11 of 2 is connected to the boosting means 2 shown in FIG. 2 as the boosting control signal bus 200 shown in FIG.

The output of the eighth 2-input AND circuit 126 constituting the switch control circuit 124 is the second output signal as described above.
Of the SRFF 133 and the boost control circuit 123
Is connected to the set terminal of the SRFF 132.

The output of the ninth 2-input AND circuit 127 is
Connected to the reset terminal of the second SRFF 133,
2 input AND circuit 128 outputs the third SRFF1
34, and the output of the eleventh two-input AND circuit 129 is connected to the reset terminal of the third SRFF 134.

The output of the twelfth 2-input AND circuit 130 is connected to the set terminal of the fourth SRFF 135, and the first
The output of the 3-input 2-input AND circuit 131 is the fourth SRFF.
It is connected to the reset terminal of 135.

The inverted output 150 of the second SRFF 133 is connected to the up / down terminal of the pulse width control circuit 149,
The second switch control signal 37, which is the output of the third SRFF 134, is connected to the enable terminal of the pulse width control circuit 149, and the fourth logic constituting the logic signal bus 202 output by the clock output means 4 shown in FIG. The signal 73 is
It is connected to the clock terminal of the pulse width control circuit 149 via the inverter 142.

The fifth logic signal 74, the sixth logic signal 75, the seventh logic signal 76, and the eighth logic signal
Of the logic signal 77 and the ninth logic signal 78 of
It is connected to the logic signal input terminal of the pulse width control circuit 149.

The output of the third SRFF 134, which is the second switch control signal 37, is the third two-input OR circuit 145.
One of the terminals is connected to the gate terminal of the second switch 31 constituting the switch means 8 shown in FIG.

The inverted output of the third SRFF 134 is the first
4 two-input AND circuit 144 and one of the fifteenth two-input AND circuit 147 and the second input terminal of the three-input AND circuit 148, and the output of the fourth SRFF 135 is the three-input AND circuit 148. Is connected to the third input terminal of.

The output of the pulse width control circuit 149 is the 14th
Connected to the other input terminal of the 2-input AND circuit 144 and the input terminal of the eighth inverter 146, and the output of the eighth inverter 146 is connected to the other input terminal of the fifteenth 2-input AND circuit 147. There is.

The output of the fourteenth two-input AND circuit 144 is connected to the other input terminal of the third two-input OR circuit 145 to output the first switch control signal 38 of the third two-input OR circuit 145. The output is connected to the gate terminal of the first switch 30 which constitutes the switch means 8 shown in FIG.

The fifteenth which is the third switch control signal 39
The output of the 2-input AND circuit 147 is connected to the gate terminal of the third switch 32 which constitutes the switch means 8 shown in FIG. 3, and is the fourth switch control signal 40.
The output of the input AND circuit 148 is connected to the gate terminal of the fourth switch 33 which constitutes the switch means 8 shown in FIG.

Four switch control signals 37, 38, 3
Reference numerals 9 and 40 represent the switch control signal bus 208 shown in FIG.

FIG. 7 is a circuit diagram showing a circuit configuration of the data output circuit 110 which constitutes the voltage detection control circuit 122 of the control means 7 shown in FIG.

The data output circuit shown in FIG. 7 has three tri-state buffer blocks 11 each having a 4-bit structure.
7, 118, 119, the first tri-state
The enable terminal of the buffer block 117 is connected to the output 114 of the first 2-input OR circuit 111 which constitutes the voltage detection control circuit 122 shown in FIG.

The enable terminal of the second tri-state buffer block 118 is connected to the output 116 of the second 2-input OR circuit 113 constituting the voltage detection control circuit 122 shown in FIG. 6, and the third tri-state is connected. ·buffer·
The enable terminal of the block 119 is connected to the output 115 of the 4-input NOR circuit 112 forming the voltage detection control circuit 122 shown in FIG.

When an enable signal is input to the tri-state buffer blocks 117, 118 and 119 which form the data output circuit 110, the first tri-state
The buffer block 117 outputs a hexa “8”, the second tri-state buffer block 118 outputs a hexa “B”, and the third tri-state buffer block 119 outputs a hexa “F”. , 95, 9
Output to 6 and 97.

FIG. 8 is a circuit diagram showing a circuit configuration of a pulse width control circuit 149 which constitutes the switch control circuit 12 of the control means 7 shown in FIG.

The pulse width control circuit shown in FIG.
Input NAND circuits 153, 160, 161, 162, 16
3 and three 4-input AND circuits 156, 157, 164
And two 3-state buffers of 4 bits
Blocks 158 and 159, a DFF 165, a 4-bit binary up / down counter (hereinafter referred to as an up / down counter) 155 equivalent to a general 74HC191, and three inverters.

The enable terminal of the up-down counter 155 is connected to the inverting output of the third SRFF 134 which is the second switch control signal 37 shown in FIG. 6, and the up-down terminal of the up-down counter 155 is shown in FIG. It is connected to the inverted output 150 of the second SRFF 133, and the clock terminal of the up / down counter 155 is connected to the inverted signal of the fourth logic signal 73 which is the output 151 of the seventh inverter shown in FIG.

One input terminal of the first 2-input NAND circuit 153 is connected to the fourth selection signal 93, and one input terminal of the second 2-input NAND circuit 160 is connected to the clock output means shown in FIG. 4 is connected to the fifth logic signal 74 which forms the logic signal bus 202.

One input terminal of the third two-input NAND circuit 161 is connected to the sixth logic signal 75 constituting the logic signal bus 202 output from the timepiece output means 4 shown in FIG. One input terminal of the input NAND circuit 162 is connected to the seventh logic signal 76 forming the logic signal bus 202, and one input terminal of the fifth two-input NAND circuit 163 forms the logic signal bus 202. It is connected to the eighth logic signal 77.

The clock input terminal of the fifth DFF 165 is connected to the ninth logic signal 78 forming the logic signal bus 202 output by the timepiece output means 4 shown in FIG.

The input terminal of the first 4-input AND circuit 156 is connected to the 4-bit output of the up-down counter 155, and the input terminal of the second 4-input AND circuit 157 is the 4-bit output of the up-down counter 155. The lower 1 bit of the output is directly connected, and the upper 3 bits are connected via an inverter.

The other input terminal of the second 2-input NAND circuit 160 is connected to the output Q1 of the up-down counter 155, and the other input terminal of the third 2-input NAND circuit 161 is the output of the up-down counter 155. Connect to Q2,
The other input terminal of the fourth 2-input NAND circuit 162 is connected to the output Q3 of the up-down counter 155, and the other input terminal of the fifth 2-input NAND circuit 163 is connected to the output Q4 of the up-down counter 155. doing.

The output of the first 4-input AND circuit 156 is
It is connected to one input terminal of the fourth 2-input OR circuit 154 and the enable terminal of the fourth tri-state buffer block 158.

The output of the second 4-input AND circuit 157 is
It is connected to the other input terminal of the fourth two-input OR circuit 154 and the enable terminal of the fifth tri-state buffer block 159.

The outputs of the fourth tri-state buffer block 158 and the fifth tri-state buffer block 159 are connected for each bit, and are connected to the data input terminal of the up / down counter 155.

The output of the fourth 2-input OR circuit 154 is connected to the other input terminal of the first 2-input NAND circuit 153, and the output of the first 2-input NAND circuit 153 is the load terminal of the up / down counter 155. Connected to.

Second 2-input NAND circuit 160, third 2-input NAND circuit 161, and fourth 2-input NAND circuit 1
62 and the output of the fifth 2-input NAND circuit 163 are connected to the input terminal of the third 4-input AND circuit 164,
4 input AND circuit 164 outputs the fifth DFF 165.
It is connected to the reset terminal of.

The inverted output of the fifth DFF 165 is connected to the data input terminal of the fifth DFF 165, and the fifth DFF 165 is connected.
The output 152 of 165 is the switch control circuit 1 shown in FIG.
It is connected to the other terminal of the fourteenth two-input AND circuit 144 that forms part 24 and the input terminal of the eighth inverter 146.

When an enable signal is input to the tri-state buffer blocks 158 and 159 which form the pulse width control circuit 149, the fourth tri-state buffer block 158 outputs a hexadecimal "E" and a fifth tri-state. -The buffer block 159 is a hexa "2"
Is output to the data input terminal of the up / down counter 155.

Next, a method of charging the electronic timepiece according to the embodiment of the present invention will be described with reference to the drawings.

First, when a temperature difference occurs between the hot pole and the cold pole of the thermoelectric generator of the energy source 1, an electromotive voltage is generated and the boosting means 2, the voltage detection circuit 6 and the switch are connected via the power supply voltage signal 18. An electromotive voltage is supplied to the means 8 and.

The cathode terminal of the backflow prevention diode 34 shown in FIG. 3 is connected to the power supply voltage signal 18, and the
When a voltage of about 2 volts is generated, the backflow prevention diode 34 is forward biased and a current flows, and the capacitor 4
1 is gradually charged, and a voltage is generated in the clock voltage signal 36 to generate the clock output means 4, the constant voltage circuit 5, and the voltage detection circuit 6.
And the control means 7 are supplied with a voltage.

At this time, however, the voltage generated in the clock voltage signal 36 becomes about 0.5 V lower than the voltage of the power supply voltage signal 18 due to the voltage drop due to the forward bias of the backflow prevention diode.

The clock output means 4, the constant voltage circuit 5, the voltage detection circuit 6, and the control means 7 start operating when the voltage of the clock voltage signal 36 becomes negative 0.7 V or more, and the clock output means 4 Outputs the logic signal bus 202 to the control means 7, and the control means 7 outputs signals to the boost control bus 200, the selection signal bus 204, the data signal bus 206, and the switch control signal bus 208 according to the signals of the logic signal bus 202. Output.

When the clock output means 4 starts operating, 4H
z first logic signal 70 and several tens Hz to several KHz
The second logic signal 71, the third logic signal 72 of 2 Hz, and the fourth logic signal 73, which is a drive signal for moving the hand every second, are output to the control means 7.

Further, the clock output means 4 has the fifth logic signal 74 of 8 Hz and the sixth logic signal 75 of 4 Hz.
And a 7 Hz logic signal 76 at 2 Hz and an 8 Hz at 1 Hz
Control means 7 and the ninth logic signal 77 of the eighth logic signal 77 with a delay.
Output to

Further, the constant voltage circuit 5 outputs a negative reference voltage of 0.7 volt to the reference voltage signal 46 to supply the reference voltage to the D / A conversion circuit 77 which constitutes the voltage detection circuit 6 shown in FIG. We are supplying.

When the first logic signal 70 and the second logic signal 71 are input to the voltage detection control circuit 122 of the control means 7 shown in FIG. 6, the first selection signal 90, the second selection signal 91 and the second selection signal 91 are input. As the 3rd selection signal 92 and the 4th selection signal 93, a signal obtained by shifting a pulse of one cycle of the second logic signal 71 for each one second is output for each cycle of the first logic signal 70. .

The first tristate buffer block 117 constituting the data output circuit 110 shown in FIG.
Outputs a hex signal "8" to the data signal bus 206 when the first selection signal 90 and the second selection signal 91 are "high".

The second tri-state buffer block 1 which constitutes the data output circuit 110 shown in FIG.
18 is a hex signal on the data signal bus 206 when the third selection signal 92 and the fourth selection signal 93 are "high".
The B "signal is output.

Further, the third tri-state buffer block 1 which constitutes the data output circuit 110 shown in FIG.
19 is a hexadecimal signal on the data signal bus 206 when any one of the first selection signal 90, the second selection signal 91, the third selection signal 92 and the fourth selection signal 93 is not "high". The F "signal is output.

From the above, in the embodiment of the present invention, the data output circuit 110 outputs only the data in three states to the data signal bus 206.

Since the data signal bus 206 is connected to the gate terminals of the four inverters 60, 61, 62 and 63 forming the D / A conversion circuit 77 of the voltage detection circuit shown in FIG. As shown in FIG. 5, the voltage at the inverting input terminal is negative 0.34 volts when the data signal bus 206 is hex "8", and is negative 0. 4 volts when the data signal bus 206 is hex "B". 51
At 4 volts, it will be negative 0.7 volts when the data signal bus 206 is a hex "F".

The first selection signal 90, the second selection signal 91, the third selection signal 92, and the fourth selection signal 93 are generated by the voltage dividing circuit 75 of the voltage detecting circuit 6 shown in FIG. 4 TG83, TG84, TG85, TG86 that make up
Is input to the control terminal.

Therefore, when the first selection signal 90 is "high", the voltage of the power source voltage signal 18 of the energy source 1 is set, and when the second selection signal 91 is "high", the boosted voltage signal 17 of the boosting means 2 is set. Voltage to the third selection signal 92
Is "high", the voltage of the storage voltage signal 35 of the storage means 3 is selected, and when the fourth selection signal 93 is "high", the voltage of the clock voltage signal 36 of the clock output means 4 is selected. The voltage divided by half by the first resistor 81 and the second resistor 82 is output to the non-inverting input terminal of the comparator 68.

As described above, each selection signal 90,
The voltage supplied to the non-inverting input terminal and the inverting input terminal of the comparator 68 differs depending on 91, 92, 93, and the voltage detection signal 69 output from the comparator 68 is "low" or "high" depending on the respective states. 6 is output to the boost control circuit 123 and the switch control circuit 124 of the control means 7 shown in FIG.

Further, the first selection signal 90, the third selection signal 92, and the fourth selection signal 93 are input to the switch control circuit 124 of the control means 7 shown in FIG. 6, and the second selection signal 91 is input. Is input to the boost control circuit 123 shown in FIG.

Therefore, the voltage boost control circuit 123 causes the voltage boosting means 2 shown in FIG. The boost control signal bus 200 configured by the boost control signal 11 of 2 is output.

Further, the switch control circuit 124 has the voltage detection signal 69, the first selection signal 90 and the third selection signal 92.
And the fourth selection signal 93, the fourth logic signal 73, and the fifth
Of the logic signal 74, the sixth logic signal 75, the seventh logic signal 76, the eighth logic signal 77, and the ninth logic signal 78 of the switch means 8 shown in FIG.
A switch control signal bus 208 composed of the first switch control signal 38, the second switch control signal 37, the third switch control signal 39, and the fourth switch control signal 40 is output.

FIG. 9 is a waveform diagram showing drive waveforms of the boost control signal bus when the energy source of the electronic timepiece of the present invention raises and lowers the generated voltage.

The waveform diagram shown in FIG. 9 is a waveform diagram when the secondary battery 43, which is the storage means 3 shown in FIG. 3, is not charged.

When the voltage of the power supply voltage signal 18 becomes negative 1.2 V or more at time Ta, the operation of the clock output means 4, the constant voltage circuit 5, the voltage detection circuit 6 and the control means 7 is started. When starting the operation, the four DFFs forming the control means 7
101, 102, 103, 104 and four SRFFs 13
The outputs of 2, 133, 134, and 135 are "low", and the inverted outputs are "high".

When the clock output means 4 starts operating, a logic signal is output to the logic signal bus 202, and the first selection signal 90, the second selection signal 91, the third selection signal 92, and the fourth selection signal 93. Means to output a pulse of one cycle of the second logic signal 71 every one second in synchronization with the first logic signal 70.

When the first selection signal 90 first outputs a pulse at time T11, the fourth TG 86 constituting the voltage detection circuit 6 shown in FIG. 4 is turned "on", and the power source voltage signal output from the energy source 1 is output. A voltage that is half the voltage of 18 is output to the non-inverting input terminal of the operational amplifier 68.

At the same timing, the data output circuit 110 shown in FIG.
The hexadecimal "8" is output to the voltage detection circuit 6 shown in
"ON" the P-MOST 55 which forms the inverter 60, the second inverter 61, and the third inverter 62 of FIG.
The N-MOST 56 that constitutes the fourth inverter 63.
Is turned on to output a negative voltage of 0.374 V to the inverting input terminal of the comparator 68.

As is apparent from the above description, the voltage of the power supply voltage signal 18 for activating the timepiece output means 4 is negative 1.2 V, and therefore the voltage of the power supply voltage signal 18 is half the voltage. Is greater than negative 0.374 volts in absolute value, the output of the fourth SRFF 135 shown in FIG. 6 goes "high" in synchronization with the pulse of the first selection signal 90.

At this point, the first SRFF 132
The inverted output of the second SRFF 133, the inverted output of the second SRFF 133, and the inverted output of the third SRFF 134 are "high".

Since the inverted output of the first SRFF 132 and the inverted output of the third SRFF 134 are "high", when the output of the fourth SRFF 135 becomes "high", the 3-input AND circuit 148 The output, the fourth switch control signal 40, becomes "high".

When the fourth switch control signal 40 becomes "high", the fourth switch 33 constituting the switch means 8 shown in FIG.
The voltage of 6 becomes the voltage of the power supply voltage signal 18.

Also, since the inverted output of the second SRFF 133 is "high" and the output of the third SRFF 134 is "low", the pulse width control circuit 149 operates as a down counter and the first counter Switch control signal 3
8 and the third switch signal 38, which is an inverted signal of the first switch control signal 38.
As the switch control signal 39, a signal whose duty changes every second is output to control the first switch 30 and the third switch 32 which constitute the switch means 8 shown in FIG.

Since the second switch control signal 37, which is the output of the third SRFF 134, is "low", the second switch 31 shown in FIG. 3 is non-conductive.

At this time, the output of the first SRFF 132 is "low" and the output of the sixth 2-input AND circuit 136 and the seventh 2-input AND circuit 138 is the first boost control signal 10 and The second boost control signal 11 outputs "low", and the boosting means 2 shown in FIG. 2 is not operating.

Next, at time T12, the second selection signal 91
Outputs a pulse, the third TG 85 constituting the voltage detection circuit 6 shown in FIG. 4 is turned “on”, and a half voltage of the boosted voltage signal 17 output from the boosting means 2 is supplied to the operational amplifier 68. Output to the non-inverting input terminal.

At the same timing, the data output circuit 110 shown in FIG.
The hexadecimal "8" is output to the voltage detection circuit 6 shown in
"ON" the P-MOST 55 which forms the inverter 60, the second inverter 61, and the third inverter 62 of FIG.
The N-MOST 56 that constitutes the fourth inverter 63.
Is turned on to output a negative voltage of 0.374 V to the inverting input terminal of the comparator 68.

However, the boosting means 2 is not operating at this time, and the voltage of the boosted voltage signal 17 is almost at the ground potential. Therefore, the first SRF shown in FIG.
The output of F132 remains "low", and the sixth 2-input AND circuit 136 and the seventh 2-input AND circuit 13
The first boosting control signal 10 and the second boosting control signal 11, which are the outputs of 8, output "low", and the boosting means 2 shown in FIG. 2 is not operating.

At this point, the second SRFF 133
Since the outputs of the third SRFF 134 and the fourth SRFF 135 have not changed, the respective switch control signals 37, 38, 39, 40 maintain the previous states.

Next, at time T13, the third selection signal 92
Outputs a pulse, the second TG 84 constituting the voltage detection circuit 6 shown in FIG. 4 is turned “on”, and a voltage half the voltage of the accumulated voltage signal 35 output from the accumulating means 3 is output from the operational amplifier 68. Output to the non-inverting input terminal.

At the same timing, the data output circuit 110 shown in FIG.
The hexadecimal "B" is output to the voltage detection circuit 6 shown in
The P-MOST 55, which constitutes the inverter 62 of the above, is turned “on”, and the first inverter 60 and the second inverter 61 are
And the N-MOST 56 that constitutes the fourth inverter 63
Is turned on to output a negative voltage of 0.514 V to the inverting input terminal of the comparator 68.

However, at this time, the secondary battery 43 of the storage means 3 is not charged, and the voltage of the storage voltage signal 35 is almost at the ground potential. Therefore, FIG.
The output of the third SRFF 134 shown in (4) remains "low".

At this point, the first SRFF 132
Since the outputs of the second SRFF 133 and the fourth SRFF 135 have not changed, the switch control signals 37, 3
8, 39 and 40 and the boost control signals 10 and 11 maintain the previous state.

Next, at time T14, the fourth selection signal 93
Outputs a pulse, the first TG 83 constituting the voltage detection circuit 6 shown in FIG. 4 is turned "on", and the operational amplifier 68 outputs a voltage half the voltage of the clock voltage signal 36 output from the clock output means 4. Output to the non-inverting input terminal of.

At the same timing, the data output circuit 110 shown in FIG.
The hexadecimal "B" is output to the voltage detection circuit 6 shown in
The P-MOST 55, which constitutes the inverter 62 of the above, is turned “on”, and the first inverter 60 and the second inverter 61 are
And the N-MOST 56 that constitutes the fourth inverter 63
Is turned on to output a negative voltage of 0.514 V to the inverting input terminal of the comparator 68.

At this time, the clock voltage signal 3 of the clock output means 4
No. 6 has a negative voltage of 1.2 V or more because the fourth switch 33 shown in FIG. 3 is conducting. It is not charged, and the voltage of the accumulated voltage signal 35 is almost at the ground potential. Therefore, the output voltage of the first SRFF 132 shown in FIG. 6 becomes “high” and the second SRFF 133 and the voltage of half of the voltage of the clock voltage signal 36 are larger than the negative 0.514 volt in absolute value. The inverted output of is "low".

At this point, the third SRFF 134
And the output of the fourth SRFF 135 has not changed.

When the output of the first SRFF 132 becomes "high", the sixth two-input AND circuit 136 and the seventh two-input AND circuit 138 start operating, and in the present invention, 2 Hz.
A signal synchronized with the third logic signal 72 is output to the first boost control signal 10 and the second boost control signal 11, and the boosting means 2 shown in FIG. 2 starts operating.

At this time, when the inverted output of the first SRFF 132 becomes "low", the fourth switch control signal 40
Is "low" in synchronization with the inverted output of the first SRFF 132.
Then, the fourth switch 33 constituting the switch means 8 shown in FIG. 3 is turned off.

At this time, when the inverted output from the second SRFF 133 becomes "low", the pulse width control circuit 149 tries to operate as an up counter.

Although omitted in FIG. 9, next time T21
Then, the first selection signal 90 outputs a pulse, but the outputs of the respective SRFFs 132, 133, 134, 135 do not change, and the previous state is maintained.

Next, at time T22, the second selection signal 91
If the potential of the boosted voltage signal 17 is not sufficiently boosted even when the pulse is output, the first S shown in FIG.
The output of the RFF132 becomes "low", and the boost control signal 1
The operations of 0 and 11 are stopped.

At this time, since the inverted output of the first SRFF 132 becomes "high", the fourth switch control signal 40
Makes the fourth switch 33 shown in FIG. 3 conductive.

Thereafter, at time T23, the same operation as at time T13 is performed, and at time 24, the same operation as at time 14 is performed. At time T31, the same operation as at time T21 is performed.

Time Tb between time T31 and time T32.
Then, when the boosted voltage signal 17 becomes negative 0.75 V or more and the second selection signal 91 outputs a pulse at time T32, the comparator 68 shown in FIG. 4 outputs "high", and as shown in FIG. The first SRFF 132 disappears after being reset, and the output of the first SRFF 132 maintains "high".

Further, since the inverted output of the first SRFF 132 also maintains "low", the fourth switch control signal 40 maintains "low", which constitutes the switch means 8 shown in FIG. The fourth switch 33 is made non-conductive.

When the voltage of the power supply voltage signal 17 of the energy source 1 becomes negative 0.75 V or less at time Tc,
In synchronization with the first selection signal 90 output at time T41,
The output of the fourth SRFF 135 becomes "low", and the fourth switch control signal 40 tries to make "low".

Although not shown in FIG. 9, when the voltage of the storage voltage signal 35 of the storage means 3 becomes negative 1.03 V or more, the output of the third SRFF 134 becomes "high" and pulsed. The width control circuit 149 is stopped, the first switch control signal 38 and the second switch control signal 37 are set to "high", and the third switch control signal 39 and the fourth switch control signal 40 are set to "low". To

Therefore, the first switch 3 shown in FIG.
By connecting 0 and the second switch 31, the accumulated voltage signal 35 and the clock voltage signal 36 are connected, and the third switch 32 and the fourth switch 33 are cut off.

As described above, the 3-input AND circuit 148 determines whether the boosted voltage signal 17 becomes negative 0.75 V or more,
Whether the accumulated voltage signal 35 becomes negative 1.03 volt or more,
When the power supply voltage signal 18 becomes negative 0.75 V or less, the fourth switch 33 shown in FIG. 3 is turned off.

The non-conduction of the fourth switch 33 shown in FIG. 3 means that when the voltage of the boosted voltage signal 17 and the accumulated voltage signal 35 becomes equal to or higher than the voltage of the power supply voltage signal 18, a current flows through the energy source 1. This is to prevent backflow.

FIG. 10 is a waveform diagram showing how the pulse width control circuit shown in FIG. 8 counts down, and FIG. 11 is a waveform diagram showing how the pulse width control circuit shown in FIG. 8 counts up.

Although not shown in FIG. 10 or 11, an 8 Hz signal used for the fifth logic signal 74, a 4 Hz signal used for the sixth logic signal 75, and a 1 Hz signal used for the seventh logic signal 76, Eighth logic signal 77
The 1 Hz signal used for is a signal that rises in synchronization with the rising of the fourth selection signal 93.

Further, the fourth logic signal 73 is a signal which outputs a pulse slightly earlier than the fourth selection signal 93 in synchronization with the fourth selection signal 93, and the ninth logic signal 78.
Is 1H output after the pulse output of the fourth selection signal 93
z signal.

The driving method will be described below with reference to the pulse width control circuit shown in FIG. 8 and the down count waveform shown in FIG.

Up / down counter 155 shown in FIG.
The output of is initially hexadecimal "4", and the inverted signal of the fourth logic signal 73 is the up / down counter 1
When it is input to the clock input terminal of 55, the output of the up / down counter 155 becomes hex "3".

Next, when the inverted signal of the fourth logic signal 73 is input to the clock input terminal of the up / down counter 155, the output of the up / down counter 155 becomes hex "2".

Then, when the inverted signal of the fourth logic signal 73 is input to the clock input terminal of the up / down counter 155, the output of the up / down counter 155 becomes hex "1".

When the output of the up / down counter 155 becomes "1" of hexa, the second 4-input AND circuit 157
Outputs a "high" enable signal to the fifth tri-state buffer block 159 and the fourth 2-input OR circuit 154.

Fifth Tri-State Buffer Block 1
59 outputs a hex “2” to the data input terminal of the up / down counter 155 by the enable signal, and when the enable signal is output at the same time, the inverted signal of the fourth selection signal 93 loads the up / down counter 155. It is output to the input terminal.

When the inverted signal of the fourth selection signal 93 is input to the load input terminal of the up / down counter 155, the output of the up / down counter 155 outputs hex "2" so that the up / down counter 155 does not overflow. It has become.

As described above, when the output of the up / down counter 155 is determined, the fifth DFF 165 becomes the ninth output.
In synchronization with the rising edge of the logic signal 78 of
The output 152 of the FF 165 is set to “high”, and the fifth logic signal 7 corresponding to the number of output values of the up / down counter 155 is output.
When 4 is input, the duty of the charging time is determined by resetting the fifth DFF 165 and setting the output 152 to "low".

The driving method will be described below with reference to the pulse width control circuit shown in FIG. 8 and the up-count waveform shown in FIG.

Up / down counter 155 shown in FIG.
Is initially a hexadecimal "C", and the inverted signal of the fourth logic signal 73 is the up / down counter 1
When input to the clock input terminal of 55, the output of the up / down counter 155 becomes hexadecimal "D".

Next, when the inverted signal of the fourth logic signal 73 is input to the clock input terminal of the up / down counter 155, the output of the up / down counter 155 becomes hexadecimal "E".

Then, when the inverted signal of the fourth logic signal 73 is input to the clock input terminal of the up / down counter 155, the output of the up / down counter 155 becomes a hexagonal "F".

When the output of the up / down counter 155 becomes "F" of hexa, the first 4-input AND circuit 156
Outputs a "high" enable signal to the fourth tri-state buffer block 158 and the fourth 2-input OR circuit 154.

Fourth tri-state buffer block 1
58 outputs a hexadecimal "E" to the data input terminal of the up / down counter 155 by the enable signal, and at the same time, when the enable signal is output, the inverted signal of the fourth selection signal 93 loads the up / down counter 155. It is output to the input terminal.

When the inverted signal of the fourth selection signal 93 is input to the load input terminal of the up / down counter 155, the output of the up / down counter 155 outputs hex "E" so that the up / down counter 155 does not overflow. It has become.

As described above, when the output of the up / down counter 155 is determined, the fifth DFF 165 outputs the ninth signal.
In synchronization with the rising edge of the logic signal 78 of
The output 152 of the FF 165 is set to “high”, and the fifth logic signal 7 corresponding to the number of output values of the up / down counter 155 is output.
When 4 is input, the duty of the charging time is determined by resetting the fifth DFF 165 and setting the output 152 to "low".

As described above, when the output 152 of the fifth DFF 165 is determined, the first switch control signal 38 shown in FIG. 6 is the same signal as the output 152 of the fifth DFF 165, and the switching means shown in FIG. 8 is output to the first switch 30 and the first switch 3 is output only when it is "high".
Conduct 0.

The third switch control signal 39 shown in FIG. 6 outputs the inverted signal of the output 152 of the fifth DFF 165 to the third switch 32 constituting the switch means 8 shown in FIG. , 3rd switch 3 only when "High"
Conduct 2

The minimum resolution for increasing or decreasing the charging time for charging the storage means 3 and the clock output means 4 in the embodiment of the present invention is determined by the frequency of the fifth logic signal 74. In the present invention, 8 Hz is set. Since it is used, the minimum step is 62.5 milliseconds.

Further, the number of steps is 16 divisions from 0 to F, but it is not particularly limited to this value, and a pulse width control circuit is used by using logic signals of higher frequency and more logic signals. By increasing the number of bits of the up / down counter 155 constituting 149, a smaller step width and a larger number of steps can be obtained.

In addition, the inverter 60 constituting the D / A conversion circuit 77 of the voltage detection circuit 6 in the embodiment of the present invention,
61, 62 and 63 are P-MOST 55 and N-MOST
56 and two resistors 57 and 58, P-
It is obvious that the same operation as that of the embodiment of the present invention can be achieved by adjusting the channel width / channel length of the MOST 55 and the N-MOST 56 so that the inverter has a desired ON resistance.

Further, in the embodiment of the present invention, the data output circuit 110 which constitutes the voltage detection control circuit 122 of the control means 7.
Tristate buffer blocks 117, 118, 1
19 and a pulse width control circuit 1 forming a switch control circuit
49 tri-state buffer blocks 158, 159
By using a non-volatile memory element such as MONOS, NMOS, or flash ROM as a memory element, it is possible to provide an electronic timepiece capable of rewriting data according to specifications.

[0235]

According to the embodiments of the present invention, as the control means, a pulse signal which changes stepwise in accordance with the output of the voltage detection for detecting the voltages of the storage means and the timepiece output means is generated, and the storage means and the timepiece are clocked. By controlling the charging time of the output means, it is possible to efficiently charge the storage means with the generated energy.

Further, when the above control means is used, the time for charging the timepiece output means can be set within one second, so that the stabilizing capacity is only required to be charged with one pulse of pulse motor drive power, and the stabilizing capacity is stabilized. The capacity value of the capacity can be reduced to less than half of the conventional value. For this reason, the time constant for charging becomes small, and even when there is almost no energy in the accumulating means, it is charged quickly and reaches the minimum operating voltage of the timepiece output means.
Improves self-startability.

Furthermore, the voltage detection circuit has four C-MOSs.
Since 16 kinds of reference voltage can be generated from the constant voltage circuit by using the D / A conversion circuit in which T is connected in parallel, the energy source generation voltage, the booster output voltage, the storage output voltage, etc. can be generated by one voltage comparison circuit. It is possible to detect the voltage and the like in a time division manner.

Furthermore, when the energy source has a constant output, the backflow prevention diode is short-circuited by the output of the timepiece output means to prevent the resistance loss due to the backflow prevention diode, and the generated energy storage means and the clock output. The utilization efficiency of the means can be improved.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a circuit configuration of an electronic timepiece according to an embodiment of the present invention.

FIG. 2 is a circuit diagram showing an internal configuration of an energy source and boosting means in an embodiment of the present invention.

FIG. 3 is a circuit diagram showing an internal configuration of a storage means, a clock output means, and a switch means in the embodiment of the present invention.

FIG. 4 is a circuit diagram showing internal configurations of a constant voltage circuit and a voltage detection circuit according to an embodiment of the present invention.

FIG. 5 is a D / A of the voltage detection circuit according to the embodiment of the present invention.
6 is a table showing a relationship between an input signal and an output voltage of the conversion circuit.

FIG. 6 is a circuit diagram showing an internal configuration of control means in the embodiment of the present invention.

FIG. 7 is a circuit diagram showing a circuit configuration of a data output circuit which constitutes a voltage detection control circuit of the control means in the embodiment of the present invention.

FIG. 8 is a circuit diagram showing a circuit configuration of a pulse width control circuit which constitutes a switch control circuit of a control means in an example of the present invention.

FIG. 9 is a waveform diagram showing drive waveforms of the boost control signal bus when the generated voltage of the energy source of the electronic timepiece of the invention rises and falls.

FIG. 10 is a waveform diagram showing how the pulse width control circuit in the embodiment of the present invention performs a down count.

FIG. 11 is a waveform diagram showing how the pulse width control circuit in the embodiment of the invention counts up.

FIG. 12 is a waveform diagram of a control signal of the conventional charging circuit.

FIG. 13 is a circuit diagram of a charging circuit of a conventional electronic timepiece.

[Explanation of symbols]

 1 Energy Source 2 Boosting Means 3 Storage Means 4 Clock Output Means 5 Constant Voltage Circuit 6 Voltage Detection Circuit 7 Control Means 8 Switch Means 17 Boosted Voltage Signals 18 Power Supply Voltage Signals 19 Ground Signals 35 Accumulated Voltage Signals 36 Clock Voltage Signals 46 Reference Voltage Signals 69 voltage detection signal 200 boost control signal bus 202 logic signal bus 204 selection signal bus 206 data signal bus 208 switch control signal bus

Claims (10)

[Claims] 1. An energy source for outputting a generated voltage to a power supply voltage signal by external energy, boosting means for outputting a boosted voltage signal to a boosted voltage signal by a boosting control signal bus, and boosting of the boosted voltage signal. An accumulating means for accumulating a voltage via the switch means and a clock output means for outputting a plurality of logic signals by inputting the voltage of the power supply voltage signal, the boosted voltage signal or the accumulated voltage signal to the clock voltage signal via the switch means. And a constant voltage circuit that outputs a reference voltage from the voltage of the clock voltage signal, a voltage of a power supply voltage signal, a boost voltage signal, a storage voltage signal, and a clock voltage signal are selected, and a voltage detection signal is generated by a signal bus and a data signal bus. The voltage detection circuit for outputting, the boost control signal bus, the selection signal bus, the data signal bus, and the switch are controlled by a plurality of logic signals and voltage detection signals. A control means for outputting a control signal bus, and a switch means having a plurality of switches for controlling charging time to the storage means and the timepiece output means by the switch control signal bus. 2. An energy source for outputting a generated voltage to a power supply voltage signal by external energy, a boosting unit for outputting a boosted voltage signal to a boosted voltage signal by a boosting control signal bus, and a boosted voltage signal booster. An accumulating means for accumulating a voltage via the switch means and a clock output means for outputting a plurality of logic signals by inputting the voltage of the power supply voltage signal, the boosted voltage signal or the accumulated voltage signal to the clock voltage signal via the switch means. And a constant voltage circuit that outputs a reference voltage from the voltage of the clock voltage signal, a voltage of a power supply voltage signal, a boost voltage signal, a storage voltage signal, and a clock voltage signal are selected, and a voltage detection signal is generated by a signal bus and a data signal bus. The voltage detection circuit for outputting, the boost control signal bus, the selection signal bus, the data signal bus, and the switch are controlled by a plurality of logic signals and voltage detection signals. A control means for outputting a control signal bus and a switch means having a plurality of switches for controlling charging time to the storage means and the clock output means by the switch control signal bus. Signal, boosted voltage signal, accumulated voltage signal, and clock voltage signal, a voltage dividing circuit having a transmission gate for selecting a voltage of a selection signal bus and a resistor for dividing the selected voltage into two, and a reference voltage for a constant voltage circuit A D / A conversion circuit including a plurality of inverters each having a low-potential-side power source connected to resistors of the same value on the high-potential side and the low-potential side with respect to the output and connected to the data signal bus by an input; And the resistance value of each inverter is 2 in order.
An electronic watch characterized in that the output of each inverter is connected to the inverting input terminal of the comparator, and the output of the voltage divider circuit is connected to the non-inverting input terminal of the comparator. 3. An energy source for outputting a generated voltage to a power supply voltage signal by external energy, a boosting means for outputting a boosted voltage to a boosted voltage signal by a boosting control signal bus for boosting the voltage of the power supply voltage signal, and boosting of the boosted voltage signal. An accumulating means for accumulating a voltage via the switch means and a clock output means for outputting a plurality of logic signals by inputting the voltage of the power supply voltage signal, the boosted voltage signal or the accumulated voltage signal to the clock voltage signal via the switch means. And a constant voltage circuit that outputs a reference voltage from the voltage of the clock voltage signal, a voltage of a power supply voltage signal, a boost voltage signal, a storage voltage signal, and a clock voltage signal are selected, and a voltage detection signal is generated by a signal bus and a data signal bus. A voltage detection circuit for outputting a voltage detection circuit for outputting, and a selection signal bus and a data signal bus for controlling the voltage detection circuit by a logic signal bus. An output control circuit, a boost control circuit for outputting a boost control signal bus for controlling the boost means by a voltage detection signal, a selection signal bus, and a logic signal bus,
A switch control which has a pulse width control circuit and outputs a switch control signal bus for controlling the charging time to the storage means and the clock output means by controlling the switch means by the voltage detection signal, the selection signal bus and the logic signal bus. An electronic timepiece comprising: a control unit including a circuit; and a switch unit including a plurality of switches that control a charging time for the storage unit and the timepiece output unit by a switch control signal bus. 4. An energy source for outputting a generated voltage to a power supply voltage signal by external energy, boosting means for outputting a boosted voltage to a boosted voltage signal by a boosting control signal bus for boosting the voltage of the power supply voltage signal, and boosting of the boosted voltage signal. An accumulating means for accumulating a voltage via the switch means and a clock output means for outputting a plurality of logic signals by inputting the voltage of the power supply voltage signal, the boosted voltage signal or the accumulated voltage signal to the clock voltage signal via the switch means. And a constant voltage circuit that outputs a reference voltage from the voltage of the clock voltage signal, a voltage of a power supply voltage signal, a boost voltage signal, a storage voltage signal, and a clock voltage signal are selected, and a voltage detection signal is generated by a signal bus and a data signal bus. The voltage detection circuit for outputting, the boost control signal bus, the selection signal bus, the data signal bus, and the switch are controlled by a plurality of logic signals and voltage detection signals. A first switch located between the boost voltage signal and the accumulated voltage signal by connecting the control means for outputting the H control signal bus and the first switch control signal output by the control means, and the control means for outputting The second switch control signal connected to the second switch located between the accumulated voltage signal and the clock voltage signal is connected to the third switch control signal output by the control means to connect the boosted voltage signal to the clock. The third switch located between the voltage signal and the fourth switch control signal output from the control means are connected, and the fourth switch located between the power supply voltage signal and the clock voltage signal and the fourth switch. An electronic timepiece comprising: a switch unit including a backflow prevention diode connected in parallel to the switch. 5. An energy source for outputting a generated voltage to a power supply voltage signal by external energy, boosting means for outputting a boosted voltage to a boosted voltage signal by a boosting control signal bus for boosting the voltage of the power supply voltage signal, and boosting of the boosted voltage signal. An accumulating means for accumulating a voltage via the switch means and a clock output means for outputting a plurality of logic signals by inputting the voltage of the power supply voltage signal, the boosted voltage signal or the accumulated voltage signal to the clock voltage signal via the switch means. And a constant voltage circuit that outputs a reference voltage from the voltage of the clock voltage signal, a voltage of a power supply voltage signal, a boost voltage signal, a storage voltage signal, and a clock voltage signal are selected, and a voltage detection signal is generated by a signal bus and a data signal bus. The voltage detection circuit for outputting, the boost control signal bus, the selection signal bus, the data signal bus, and the switch are controlled by a plurality of logic signals and voltage detection signals. H control signal bus and a switch means having a plurality of switches for controlling charging time to the storage means and the clock output means by the switch control signal bus. The clock output means is a power supply voltage signal. When the voltage of is a constant voltage, the logic signal bus is output to the control means, and the voltage detection control circuit that constitutes the control means changes the selection signal bus to the voltage divider circuit that constitutes the voltage detection circuit according to the signal of the logic signal bus. D / A which outputs and outputs the data signal bus corresponding to the selection signal bus to the voltage detection circuit
The voltage value output to the conversion circuit and selected by the selection signal bus is D
The voltage detection signal is output to the boost control circuit and the switch control circuit which are detected by the / A conversion circuit and constitute the control means, and the boost control circuit outputs the voltage detection signal, the second selection signal of the selection signal bus, and the fourth selection signal. The boost control signal bus is output to the boosting means by the selection signal, and the switch control circuit operates the switch control circuit by the voltage detection signal, the first selection signal, the third selection signal, and the fourth selection signal of the selection signal bus. A method for charging an electronic timepiece, characterized by outputting a switch control signal bus to a switch means by controlling a constituent pulse width control circuit to control a charging time for the storage means and the timepiece output means. 6. An energy source for outputting a generated voltage to a power supply voltage signal by external energy, a boosting means for outputting a boosted voltage to a boosted voltage signal by a boosting control signal bus for boosting the voltage of the power supply voltage signal, and boosting of the boosted voltage signal. An accumulating means for accumulating a voltage via the switch means and a clock output means for outputting a plurality of logic signals by inputting the voltage of the power supply voltage signal, the boosted voltage signal or the accumulated voltage signal to the clock voltage signal via the switch means. And a constant voltage circuit that outputs a reference voltage from the voltage of the clock voltage signal, a voltage of a power supply voltage signal, a boost voltage signal, a storage voltage signal, and a clock voltage signal are selected, and a voltage detection signal is generated by a signal bus and a data signal bus. The voltage detection circuit for outputting, the boost control signal bus, the selection signal bus, the data signal bus, and the switch are controlled by a plurality of logic signals and voltage detection signals. H control signal bus and a switch means having a plurality of switches for controlling charging time to the storage means and the clock output means by the switch control signal bus. The clock output means is a power supply voltage signal. When the voltage of is a constant voltage, the logic signal bus is output to the control means, and the voltage detection control circuit that constitutes the control means changes the selection signal bus to the voltage divider circuit that constitutes the voltage detection circuit according to the signal of the logic signal bus. D / A which outputs and outputs the data signal bus corresponding to the selection signal bus to the voltage detection circuit
The voltage value output to the conversion circuit and selected by the selection signal bus is D
The voltage detection signal is output to the boost control circuit and the switch control circuit which are detected by the / A conversion circuit and constitute the control means, and the boost control circuit outputs the voltage detection signal, the second selection signal of the selection signal bus, and the fourth selection signal. The boost control signal bus is output to the boosting means in response to the selection signal, and when the voltage of the accumulated voltage signal is equal to or lower than the constant voltage and the voltage of the clock voltage signal is equal to or lower than the constant voltage, the switch control circuit outputs the voltage detection signal and the selection signal bus. The pulse width control circuit that constitutes the switch control circuit is controlled as a down counter by the first selection signal, the third selection signal, and the fourth selection signal, and the boosted voltage signal and the accumulated voltage signal that constitute the switch means are It is controlled so that the conduction time of the first switch located between them is reduced and the conduction time of the third switch located between the boosted voltage signal and the clock voltage signal that constitutes the switch means is increased. The method of charging the electronic watch, characterized in that. 7. An energy source for outputting a generated voltage to a power supply voltage signal by external energy, boosting means for outputting a boosted voltage signal to a boosted voltage signal by a boosting control signal bus, and boosting of the boosted voltage signal. An accumulating means for accumulating a voltage via the switch means and a clock output means for outputting a plurality of logic signals by inputting the voltage of the power supply voltage signal, the boosted voltage signal or the accumulated voltage signal to the clock voltage signal via the switch means. And a constant voltage circuit that outputs a reference voltage from the voltage of the clock voltage signal, a voltage of a power supply voltage signal, a boost voltage signal, a storage voltage signal, and a clock voltage signal are selected, and a voltage detection signal is generated by a signal bus and a data signal bus. The voltage detection circuit for outputting, the boost control signal bus, the selection signal bus, the data signal bus, and the switch are controlled by a plurality of logic signals and voltage detection signals. H control signal bus and a switch means having a plurality of switches for controlling charging time to the storage means and the clock output means by the switch control signal bus. The clock output means is a power supply voltage signal. When the voltage of is a constant voltage, the logic signal bus is output to the control means, and the voltage detection control circuit that constitutes the control means changes the selection signal bus to the voltage divider circuit that constitutes the voltage detection circuit according to the signal of the logic signal bus. D / A which outputs and outputs the data signal bus corresponding to the selection signal bus to the voltage detection circuit
The voltage value output to the conversion circuit and selected by the selection signal bus is D
The voltage detection signal is output to the boost control circuit and the switch control circuit which are detected by the / A conversion circuit and constitute the control means, and the boost control circuit outputs the voltage detection signal, the second selection signal of the selection signal bus, and the fourth selection signal. The boost control signal bus is output to the boosting means by the selection signal, and when the voltage of the accumulated voltage signal is equal to or lower than the constant voltage and the voltage of the clock voltage signal is equal to or higher than the constant voltage, the switch control circuit outputs the voltage detection signal and the selection signal bus. The pulse width control circuit forming the switch control circuit is controlled as an up counter by the third selection signal and the fourth selection signal, and is located between the boosted voltage signal and the accumulated voltage signal forming the switch means. Control is performed so as to increase the conduction time of the switch and reduce the conduction time of the third switch, which is located between the boosted voltage signal and the clock voltage signal, which constitutes the switch means. The method of charging the electronic watch that. 8. An energy source for outputting a generated voltage to a power supply voltage signal by external energy, boosting means for outputting a boosted voltage signal to a boosted voltage signal by a boosting control signal bus, and boosting of the boosted voltage signal. An accumulating means for accumulating a voltage via the switch means and a clock output means for outputting a plurality of logic signals by inputting the voltage of the power supply voltage signal, the boosted voltage signal or the accumulated voltage signal to the clock voltage signal via the switch means. And a constant voltage circuit that outputs a reference voltage from the voltage of the clock voltage signal, a voltage of a power supply voltage signal, a boost voltage signal, a storage voltage signal, and a clock voltage signal are selected, and a voltage detection signal is generated by a signal bus and a data signal bus. The voltage detection circuit for outputting, the boost control signal bus, the selection signal bus, the data signal bus, and the switch are controlled by a plurality of logic signals and voltage detection signals. H control signal bus and a switch means having a plurality of switches for controlling charging time to the storage means and the clock output means by the switch control signal bus. The clock output means is a power supply voltage signal. When the voltage of is a constant voltage, the logic signal bus is output to the control means, and the voltage detection control circuit that constitutes the control means changes the selection signal bus to the voltage divider circuit that constitutes the voltage detection circuit according to the signal of the logic signal bus. D / A which outputs and outputs the data signal bus corresponding to the selection signal bus to the voltage detection circuit
The voltage value output to the conversion circuit and selected by the selection signal bus is D
The voltage detection signal is output to the boost control circuit and the switch control circuit which are detected by the / A conversion circuit and constitute the control means, and the boost control circuit outputs the voltage detection signal, the second selection signal of the selection signal bus, and the fourth selection signal. The boost control signal bus is output to the boosting means according to the selection signal, and when the voltage of the accumulated voltage signal is equal to or lower than a certain voltage and the voltage of the boost voltage signal is equal to or less than the certain voltage, the switch control circuit outputs the voltage detection signal and the selection signal bus. By the second selection signal, the third selection signal and the fourth selection signal, the fourth switch located between the power supply voltage signal and the clock voltage signal forming the switch means is rendered conductive, and the backflow prevention diode is activated. A method of charging an electronic timepiece, which is controlled so as to be short-circuited. 9. An energy source for outputting a generated voltage to a power supply voltage signal by external energy, a boosting means for outputting a boosted voltage to a boosted voltage signal by a boosting control signal bus, and a boosted voltage signal. An accumulating means for accumulating a voltage via the switch means and a clock output means for outputting a plurality of logic signals by inputting the voltage of the power supply voltage signal, the boosted voltage signal or the accumulated voltage signal to the clock voltage signal via the switch means. And a constant voltage circuit that outputs a reference voltage from the voltage of the clock voltage signal, a voltage of a power supply voltage signal, a boost voltage signal, a storage voltage signal, and a clock voltage signal are selected, and a voltage detection signal is generated by a signal bus and a data signal bus. The voltage detection circuit for outputting, the boost control signal bus, the selection signal bus, the data signal bus, and the switch are controlled by a plurality of logic signals and voltage detection signals. H control signal bus and a switch means having a plurality of switches for controlling charging time to the storage means and the clock output means by the switch control signal bus. The clock output means is a power supply voltage signal. When the voltage of is a constant voltage, the logic signal bus is output to the control means, and the voltage detection control circuit that constitutes the control means changes the selection signal bus to the voltage divider circuit that constitutes the voltage detection circuit according to the signal of the logic signal bus. D / A which outputs and outputs the data signal bus corresponding to the selection signal bus to the voltage detection circuit
The voltage value output to the conversion circuit and selected by the selection signal bus is D
The voltage detection signal is output to the boost control circuit and the switch control circuit which are detected by the / A conversion circuit and constitute the control means, and the boost control circuit outputs the voltage detection signal, the second selection signal of the selection signal bus, and the fourth selection signal. The boost control signal bus is output to the boosting means according to the selection signal, and when the voltage of the accumulated voltage signal is equal to or lower than a certain voltage and the voltage of the boost voltage signal is equal to or higher than the certain voltage, the switch control circuit outputs the voltage detection signal and It is characterized in that the fourth switch located between the power supply voltage signal and the clock voltage signal forming the switch means is made non-conductive by the second selection signal, and the backflow prevention diode is inserted. How to charge an electronic watch. 10. An energy source for outputting a generated voltage to a power supply voltage signal by external energy, a boosting means for outputting a boosted voltage to a boosted voltage signal by a boosting control signal bus for boosting the voltage of the power supply voltage signal, and boosting of the boosted voltage signal. An accumulating means for accumulating a voltage via the switch means and a clock output means for outputting a plurality of logic signals by inputting the voltage of the power supply voltage signal, the boosted voltage signal or the accumulated voltage signal to the clock voltage signal via the switch means. And a constant voltage circuit that outputs a reference voltage from the voltage of the clock voltage signal, a voltage of a power supply voltage signal, a boost voltage signal, a storage voltage signal, and a clock voltage signal are selected, and a voltage detection signal is generated by a signal bus and a data signal bus. The voltage detection circuit for output, the boost control signal bus, the selection signal bus, the data signal bus, and the switch are controlled by a plurality of logic signals and voltage detection signals. Switch control signal bus, and switch means having a plurality of switches for controlling the charging time to the storage means and the clock output means by the switch control signal bus. When the voltage of the signal becomes a constant voltage, the logic signal bus is output to the control means, and the voltage detection control circuit forming the control means uses the signal of the logic signal bus to select the selection signal bus from the voltage dividing circuit forming the voltage detection circuit. The data signal bus corresponding to the selection signal bus to the D /
The voltage detection signal is output to the A conversion circuit, the voltage value selected by the selection signal bus is detected by the D / A conversion circuit, and the voltage detection signal is output to the boost control circuit and the switch control circuit that constitute the control means. The boost control signal bus is output to the boosting means by the voltage detection signal, the second selection signal of the selection signal bus, and the fourth selection signal, and when the voltage of the accumulated voltage signal is a certain voltage or more, the switch control circuit detects the voltage. The pulse width control circuit forming the switch control circuit is deselected by the signal and the third selection signal of the selection signal bus, and the second switch is located between the storage means forming the switch means and the timepiece output means. Is turned on, the fourth switch located between the energy source and the timepiece output means is turned off, and control is performed so that the backflow prevention diode is inserted.