JPH09148526A - Manufacture of semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve withstand voltage to voltage application higher than or equal to a rated voltage, like static electricity from the outside of equipment. SOLUTION: A first conductivity type MOSFET and a second conductivity type MOSFET are constituted as follows. In a second conductivity type lightly doped region 304, a first and a second heavinlydoped regions 301, 302 of a first conductivity type, and a third heavily doped region are electrically isolated and formed by element isolation regions. First conductivity type heavily doped regions 321, 322 are connected with an I/O pad via a metal wiring layer in a lateral bipolar transistor. Drain regions are connected with an I/O pad. The first conductivity type heavily doped regions 321, 322, and only the part under the contact hole periphery of the drain region are made deeper than the other parts. By making the part under the contact hole periphery of a diode formed between the heavily doped region and the lightly doped region of different polarity deep, breakdown due to a spike caused by the application of a voltage higher than or equal to a rated voltage, like static electricity, can be restrained.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly, to an electrostatic breakdown voltage of the lateral bipolar transistor, the first conductivity type MOSFET, and the second conductivity type MOSFET.

[0002]

2. Description of the Related Art As shown in FIG. 9, a MOSFET in an input / output circuit and a power supply circuit in a conventional semiconductor device has high-concentration impurity regions 903 and 904 to be drain or source regions on the surface side of a substrate and on the inner side thereof. There are low-concentration impurity regions 907 having different polarities from the high-concentration impurity regions that are well regions, and diodes are formed by the different-polarity impurity regions under the contact holes in the high-concentration impurity regions. As shown in FIG. 10, the lateral bipolar transistor in the input / output circuit and the power supply circuit in the conventional semiconductor device has a first conductivity type first high concentration impurity region 1001 and a second high concentration impurity region on the substrate surface side. The impurity region 1002 and the second-conductivity-type low-concentration impurity region 1004 exist inside, and the contact hole in the high-concentration impurity region is present. Of forms a diode with the impurity regions between the different poles under the peripheral, the lower surface of the joint surface or high-concentration impurity region in any of the diodes is substantially flat.

The MOSFET and the lateral bipolar transistor in the input / output circuit and the power supply circuit in the conventional semiconductor device as described above are disclosed in Japanese Patent Laid-Open No. 59-59359 when a voltage higher than the rated voltage such as static electricity is applied from the input / output pad.
-111351, the drain region 903 of the MOSFET and the first high-concentration impurity region 100 are formed.
M is usually connected to the power supply wiring with 1 as the collector
The source region 904 of the OSFET and the second high-concentration impurity region 1002 are used as emitters, and the well region 907 of the MOSFET and the lateral bipolar second-conductivity low-concentration impurity region 1004 which are normally connected to the power supply wiring are used as bases. As a second high-concentration impurity region 1002 and a source region 90 of the MOSFET, each of which operates as a bipolar transistor and acts as an emitter.
The transient current flowing by the applied voltage from 4 is discharged to the outside of the device through the power supply wiring. Further, when a higher voltage is applied to the conventional semiconductor device, as shown in FIG. 11, the metal wiring layer 1103 and the semiconductor substrate are alloyed by heat generation due to a transient current, and the alloy spike 1101 is downwardly moved from the contact hole. The high-voltage side power supply circuit-low-voltage side by growing and penetrating through the diode composed of the high-concentration impurity region 1106 and the low-concentration impurity region 1107 having a polarity different from that of the high-concentration region normally connected to the power supply wiring. There is a possibility of electrical connection between the power supply circuits or between the power supply circuit and the input / output circuit.

[0004]

SUMMARY OF THE INVENTION Therefore, the present invention is intended to solve such a problem, and its purpose is to connect a high concentration impurity region connected to an input / output pad and a power supply line. By increasing the distance between the contact surface of the diode, which consists of low-concentration impurity regions of different polarity, and the contact hole, that is, the depth of the high-concentration impurity region under the periphery of the contact hole, it is possible to obtain more than the rated value such as static electricity from the input / output pad. The purpose of this is to prevent breakdown of the diode due to spikes growing downward from the contact hole when a high voltage is applied, and to improve the withstand voltage of the semiconductor device against application of a high voltage above the rating such as static electricity.

[0005]

In a semiconductor device in which a plurality of input / output circuits and power supply circuits are arranged around a semiconductor substrate, a high-concentration impurity region is deeper only under a contact hole than other parts. And a region deeper than the other portion in the high-concentration impurity region has a high concentration after the step of depositing an insulating layer for electrically separating the semiconductor substrate and the first metal wiring layer. By a photoetching process using a photomask for a contact hole for electrically connecting the impurity region and the metal wiring layer,
It is characterized in that it is formed by implanting impurity ions from above the insulating layer having an opening at a contact hole position,
Further, a region deeper than the other portion below the periphery of the contact hole in the high-concentration impurity region is formed after the shallow region of the high-concentration impurity region is formed by the impurity ion implantation process, It is characterized in that it is formed by ion implantation at a high accelerating voltage.In addition, the input / output circuit and the power supply circuit are configured such that the first conductivity type first and second high concentration impurities are formed in the second conductivity type low concentration region. A lateral bipolar transistor in which a region and a third high-concentration impurity region of the second conductivity type are electrically separated by an element isolation region, a plurality of first conductivity type MOSFETs, a plurality of second conductivity type MOSFETs, etc. The first high-concentration impurity region and the plurality of drain regions are directly or through an impurity diffusion region or a resistor formed of a polycrystalline semiconductor layer or the like. Is indirectly connected to the input / output pad by a metal wiring layer, and is characterized in that only under the periphery of the contact hole in each region is deeper than other portions, and in other regions of the high-concentration impurity region. A region deeper than the portion may have an opening at a contact hole position in the high-concentration impurity region connected to the input / output pad by a photo-etching process after the step of implanting impurity ions in the high-concentration impurity region. It is characterized in that it is formed by implanting impurity ions from a mask material such as a shaped oxide semiconductor layer, and a region deeper than other portions below the periphery of the contact hole in the high-concentration impurity region is an impurity. After the shallow region of the high-concentration impurity region is formed by the ion implantation process, it is formed by implanting ions at a higher acceleration voltage than when forming the shallow region. The features.

[0006]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to FIGS. 1, 2, 3, 4, 5, 7, and 8.

FIG. 1 is an overall view of a semiconductor device according to the present invention. The semiconductor device includes an outer peripheral portion 1 of a semiconductor substrate 101.
Reference numeral 02 denotes an area of an input / output circuit and a power supply circuit having pads connected to the outside of the device, and an internal circuit area is provided inside the area 103 of the input / output circuit and the power supply circuit.

FIG. 2 is a schematic diagram of a MOSFET in an input / output circuit in a semiconductor device according to a first embodiment of the present invention, and FIG. 2 (a) shows insulation between a first metal wiring layer and a semiconductor substrate. FIG. 2 is a plan view immediately before the layer deposition process, and FIG.
(B) is a sectional view immediately after the deposition step of the first metal wiring layer. Reference numeral 201 denotes a contact hole for applying a potential to the gate terminal 202, and 211, 212, 213,
Reference numerals 214, 215, 216, 217, and 218 denote high-concentration impurity regions 2 serving as drain regions or source regions, respectively.
Numerals 203 and 204 are contact holes for applying a potential, 205 is an element isolation region, 206 is a first metal wiring layer such as Al, and 208 is an insulation between the metal wiring layer 206 and the semiconductor substrate. It is a layer. 221, 22
Reference numeral 2 denotes a high-concentration impurity region having the same polarity as that of 203 and 204, which exists only under the periphery of the contact hole and is in contact with the lower surface of 203 and 204, and the impurities which form the drain region or the source region are contained in the respective regions. It seems to diffuse deep under the contact hole.

FIG. 3 shows first and second high-concentration impurity regions of the first conductivity type in the second-conductivity-type low-concentration impurity region in the input / output circuit of the semiconductor device according to the first embodiment of the present invention. FIG. 3A is a schematic view of a lateral bipolar transistor in which a third high-concentration impurity region of the second conductivity type is electrically isolated by an element isolation region, and FIG. 3A is a first metal wiring layer and a semiconductor. FIG. 3B is a plan view immediately before the deposition step of the insulating layer between the substrates, and FIG. 3B is a cross-sectional view immediately after the deposition step of the first metal wiring layer. 311, 312,
Reference numerals 313, 314, 315, 316, 317, and 318 are contact holes for applying a potential to the high-concentration impurity regions 301 and 302 of the first conductivity type, which are collector regions or emitter regions, and 303 is an element isolation region. , 305 is a first metal wiring layer such as Al, and 306 is an insulating layer between the metal wiring layer 305 and the semiconductor substrate. Numerals 321 and 322 are high-concentration impurity regions of the first conductivity type, and 30 are provided only under the periphery of the contact hole.
Impurities of the first conductivity type existing in contact with the lower surface of 1, 302 and forming the first or second high-concentration impurity regions are deeply diffused under the periphery of the contact hole.

FIG. 7 is a sectional view of the MOSFET in the input / output circuit of the semiconductor device according to the first embodiment of the present invention, in the order of FIGS. 7 (a), 7 (b) and 7 (c). Shows a manufacturing process of a deep region under the periphery of the contact hole in the high concentration impurity region. Reference numeral 701 is a gate electrode, 702 and 703 are high-concentration impurity regions serving as drain regions or source regions, 704 is a low-concentration impurity region having a different polarity serving as a well region, and 705 is a first metal wiring layer. And 706 is an insulating layer between the semiconductor substrate and the semiconductor substrate, and 706 is an element isolation region. First, with respect to the semiconductor substrate in the state shown in FIG. 7A after the step of depositing the insulating layer 705, an opening portion 707 is formed in the contact hole position by a photoetching step in the insulating layer 705 as shown in FIG. 7B. , 708 are formed, and the high-concentration impurity region 70 is formed on the insulating layer 705.
702, 703 with higher accelerating voltage than when forming 2, 703
Impurity ions of the same polarity as the above are implanted, and as shown in FIG. 7C, under the periphery of the contact hole positions 707 and 708,
Deeper than the existing high-concentration impurity regions 702 and 703, 70
High-concentration impurity regions 709 and 710 having the same polarity as that of 2, 703 are formed. Also in the lateral bipolar transistor, a high-concentration impurity region having a region deeper than other portions is formed under the periphery of the contact hole by the same process.

FIG. 4 is a schematic view of a MOSFET in an input / output circuit in a semiconductor device which is a second embodiment of the present invention, and FIG. 4 (a) shows insulation between a first metal wiring layer and a semiconductor substrate. FIG. 4 is a plan view immediately before the layer deposition process, and FIG.
(B) is a sectional view immediately after the deposition step of the first metal wiring layer. Reference numeral 401 denotes a contact hole for applying a potential to the gate terminal 402, which includes 411, 412, 413, and
Reference numerals 414, 416, 41 denote contact holes for applying a potential to the drain region 403, respectively.
Reference numerals 7 and 418 are contact holes for applying a potential to the source region 404, 405 is an element isolation region, 406 is a first metal wiring layer such as Al, and 408 is the metal wiring layer 406. An insulating layer between semiconductor substrates. 421 is a high-concentration impurity region having the same polarity as the drain region, and contact holes 411, 412, 41 on the drain region 403 connected to the input / output pad.
Impurities that exist only under the periphery of 3,414 and are in contact with the lower surface of 403 and that form the drain region are deeply diffused under the periphery of the contact hole.

FIG. 5 is a schematic view of the lateral bipolar transistor in the input / output circuit of the semiconductor device according to the second embodiment of the present invention. FIG. 5 (a) shows the first metal wiring layer and the semiconductor substrate. FIG. 5B is a plan view immediately before the step of depositing the insulating layer between them, and FIG. 5B is a cross-sectional view immediately after the step of depositing the first metal wiring layer. 511, 512, 51
Reference numerals 3 and 514 denote contact holes for applying a potential to the first high-concentration region 501 of the first conductivity type that serves as a collector region, and 515, 516, 517, and 518 each have a first conductivity type that serves as an emitter region. A contact hole for applying a potential to the second high-concentration impurity region 502, 503 is an element isolation region, 505 is a first metal wiring layer such as Al, and 506 is the metal wiring layer 505. An insulating layer between semiconductor substrates. Reference numeral 521 denotes a high-concentration impurity region of the first conductivity type, which is connected to the input / output pad and is in contact with the lower surface of 501 only under the periphery of the contact holes 511, 512, 513, 514 on the first high-concentration impurity region 501. The first-conductivity-type impurities that exist in the first high-concentration impurity region are deeply diffused under the periphery of the contact hole.

FIG. 8 is a cross-sectional view of the MOSFET in the input / output circuit of the semiconductor device according to the second embodiment of the present invention. FIG. 8 (a), FIG. 8 (b), FIG. 8 (c), FIG. 8 (d) shows the manufacturing process of the deep region under the periphery of the contact hole in the high concentration impurity region in the order of 8 (d). Reference numeral 801 is a gate electrode, 802 is a drain region, 803 is a high-concentration impurity region serving as a source region, 804 is a low-concentration impurity region having a polarity different from that of the drain region serving as a well region, and 805 is an element isolation region. Is. First, a mask material 806 such as an oxide semiconductor is deposited on the semiconductor substrate in the state shown in FIG. 8A after the ion implantation process of the high concentration impurity regions 802 and 803, and a contact hole position in the diffusion region is formed by a photoetching process. It is shaped so as to have the opening 807, and in the state shown in FIG. 8B, the acceleration voltage 802, 8 is higher than that at the time of forming the high-concentration impurity regions 802, 803 from above.
A high-concentration impurity region 809 is formed below the periphery of the opening 807 and deeper than the existing high-concentration impurity regions 802 and 803 by implanting impurity ions having the same polarity as that of 03. By doing so, the impurities forming the drain region are deeply diffused under the periphery of the contact hole. After that, the insulating layer 80 between the first metal wiring layer and the semiconductor substrate shown in FIG.
After depositing 8, the openings 810 and 811 of the insulating layer at the contact hole positions shown in FIG. 8D are formed by a photoetching process. Also in the lateral bipolar transistor, the first high-concentration impurity region connected to the input / output pad having a region deeper than the other portions under the periphery of the contact hole is formed by the same process.

[0014]

The first conductivity type MOSF as described above.
The first and second high-concentration impurity regions of the first conductivity type and the third high-concentration impurity region of the second conductivity type are respectively provided in the low-concentration impurity regions of the ET structure and the second-conductivity type MOSFET structure and the second conductivity type. According to the lateral bipolar transistor structure which is electrically isolated by the element isolation region, as shown in FIG. 6, a first conductivity type MOSFET and a second conductivity type M are provided.
By forming the diode junction surface 603 under the periphery of the drain region connected to the input / output pads of the OSFET and the lateral bipolar transistor and the contact hole of the first high-concentration impurity region in a deep portion, it is possible to reduce static electricity from the input / output pad. When a high voltage above the rating is applied,
The spike 601 suppresses the destruction of the diode under the contact hole, which is most likely to be destroyed, and improves the breakdown voltage of the semiconductor device against the application of a high voltage exceeding the rating such as static electricity. Further, the present invention is effective even if each diffusion region becomes shallow.

[Brief description of the drawings]

FIG. 1 is an overall view of a semiconductor device according to the present invention.

FIG. 2 is a plan view and a sectional view of a MOSFET of a semiconductor device which is a first embodiment according to the present invention.

FIG. 3 is a diagram showing a semiconductor device according to a first embodiment of the present invention, in which a second conductivity type low concentration impurity region is formed in a first conductivity type first and second high concentration impurity regions and a second conductivity type third region. FIG. 2 is a plan view and a cross-sectional view of a lateral bipolar transistor in which the high-concentration impurity regions are electrically isolated by element isolation regions.

FIG. 4 is a plan view and a cross-sectional view of a MOSFET of a semiconductor device which is a second embodiment according to the present invention.

FIG. 5 is a second embodiment of a semiconductor device according to the present invention in which a second conductivity type low concentration impurity region is formed in a first conductivity type first and second high concentration impurity regions and a second conductivity type third region. FIG. 2 is a plan view and a cross-sectional view of a lateral bipolar transistor in which the high-concentration impurity regions are electrically isolated by element isolation regions.

6A and 6B are first and second high-concentration impurity regions of the first conductivity type and second high-concentration impurity regions of the second conductivity type of the semiconductor device of the first and second embodiments of the present invention. Of the lateral bipolar transistor in which the third high-concentration impurity regions of the above are electrically isolated by the element isolation regions and the impurity regions of the first-conductivity-type and second-conductivity-type MOSFETs in the vicinity of contact holes It is a schematic diagram of the generation state of a spike when a high voltage is applied.

FIG. 7 is a cross-sectional view showing the first manufacturing process of the first conductivity type and second conductivity type MOSFETs of the semiconductor device according to the first embodiment of the present invention.

FIG. 8 is a second conductivity type MOSFET and a second conductivity type MOSF of the semiconductor device according to the second embodiment of the present invention.
It is sectional drawing which showed the manufacturing process of ET.

FIG. 9 is a plan view and a cross-sectional view of a first conductivity type MOSFET and a second conductivity type MOSFET of a semiconductor device according to a conventional technique.

FIG. 10 illustrates first and second high-concentration impurity regions of a first conductivity type and a third high-concentration impurity region of a second conductivity type in a second-conductivity-type low-concentration impurity region of a semiconductor device according to the prior art. FIG. 3 is a plan view and a cross-sectional view of a lateral bipolar transistor provided electrically separated by an element isolation region.

FIG. 11 illustrates first and second high-concentration impurity regions of a first conductivity type and a third high-concentration impurity region of a second conductivity type in a second-conductivity-type low-concentration impurity region of a semiconductor device according to the related art. Lateral bipolar transistor and first conductivity type and second conductivity type M provided electrically separated by an insulating film
FIG. 9 is a schematic diagram of a breakdown mode due to a spike when a high voltage higher than a rating such as static electricity is applied in the vicinity of a contact hole in an impurity region of an OSFET.

[Explanation of symbols]

101: Semiconductor substrate 102: Input / output circuit and power supply circuit region 103: Internal circuit region 201: Gate terminal contact hole 202: Gate terminal 203, 204: High-concentration impurity region 205: Element isolation region 206: First Metal wiring layer 207: Low concentration impurity region 208: Insulating layer 211, 212, 213, 214, 215, 216, 2
17, 218: Contact holes for high-concentration impurity region 221, 222: High-concentration impurity region 230: Auxiliary line showing cross section 301: First high-concentration impurity region of first conductivity type 302: Second high-concentration impurity region of first conductivity type High concentration impurity region 303: Element isolation region 304: Second conductivity type low concentration impurity region 305: First metal wiring layer 306: Insulating layer 311, 312, 313, 314, 315, 316, 3
17, 318: First-conductivity-type high-concentration impurity region contact holes 321, 322: First-conductivity-type high-concentration impurity region 330: Auxiliary line showing cross section 401: Gate terminal contact hole 402: Gate terminal 403: Drain Region 404: Source region 405: Element isolation region 406: First metal wiring layer 407: Low concentration impurity region 408: Insulating layer 411, 412, 413, 414: Drain region contact hole 415, 416, 417, 418: Source region contact hole 421: High concentration impurity region 430: Auxiliary line showing cross section 501: First conductivity type first high concentration impurity region 502: First conductivity type second high concentration impurity region 503: Element isolation Region 504: Second conductivity type low-concentration impurity region 505: First metal wiring layer 506: Edge layers 511, 512, 513, 514: first conductivity type first high-concentration impurity region contact holes 515, 516, 517, 518: first conductivity type second high-concentration impurity region contact holes 521: High-concentration impurity region of first conductivity type 530: Auxiliary line showing cross section 601: Spike by alloy of semiconductor substrate and metal wiring 602: Diode bonding surface 603: Diode bonding surface 604: First metal wiring layer 605: Barrier metal Layer 606: Insulating layer 607: High concentration impurity region 608: High concentration impurity region 609: Low concentration impurity region 701: Gate terminal 702, 703: High concentration impurity region 704: Low concentration impurity region 705: Insulating layer 706: Element isolation region 707 and 708: Contact holes for high-concentration impurity regions 709 and 710: High-concentration impurities Region 801: Gate terminal 802, 803: High concentration impurity region 804: Low concentration impurity region 805: Element isolation region 806: Mask material 807: Opening portion of mask material 808: Insulating layer 809: High concentration impurity region 810, 811: High-concentration impurity region contact hole 901: Gate terminal contact hole 902: Gate terminal 903, 904: High-concentration impurity region 905: Element isolation region 906: First metal wiring layer 907: Low-concentration impurity region 908: Insulating layer 911, 912, 913, 914, 915, 916, 9
17, 918: Contact hole for high concentration impurity region 930: Auxiliary line showing cross section 1001: First high concentration impurity region of first conductivity type 1002: Second high concentration impurity region of first conductivity type 1003: Element isolation Region 1004: Second conductivity type low concentration impurity region 1005: First metal wiring layer 1006: Insulating layer 1011, 1012, 1013, 1014, 1015
Reference numerals 1016, 1017, 1018: Contact holes for high-concentration impurity regions of the first conductivity type 1030: Auxiliary lines showing a section 1101: Spikes due to an alloy of a semiconductor substrate and metal wiring 1102: Diode bonding surface 1103: First metal wiring layer 1104: Barrier metal layer 1105: Insulating layer 1106: High concentration impurity region 1107: Low concentration impurity region

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Internal reference number FI technical indication H01L 27/06

Claims (6)

[Claims] 1. A semiconductor device having a plurality of input / output circuits and a power supply circuit arranged around a semiconductor substrate, wherein the high-concentration impurity region is deeper than the other portions only under the periphery of the contact hole. Semiconductor device. 2. A semiconductor device having a plurality of input / output circuits and power supply circuits arranged around a semiconductor substrate, wherein the high-concentration impurity region is deeper than the other portions only under the periphery of the contact hole. A region deeper than the other portions in the region electrically connects the high-concentration impurity region and the metal wiring layer after the step of depositing an insulating layer for electrically separating the semiconductor substrate and the first metal wiring layer. A semiconductor device characterized by being formed by implanting impurity ions from above the insulating layer having an opening at a contact hole position by a photoetching process using a photomask for a contact hole for connection. Production method. 3. A semiconductor device comprising a plurality of input / output circuits and a power supply circuit arranged around a semiconductor substrate, wherein the input / output circuit and the power supply circuit have a first conductivity type first concentration region in a second conductivity type low concentration region. A lateral bipolar transistor in which a second high-concentration impurity region and a third high-concentration impurity region of the second conductivity type are electrically separated by an element isolation region, a plurality of first conductivity type MOSFETs, and a plurality of MOSFETs Second conductivity type MO
The first high-concentration impurity region and the plurality of drain regions are formed by an SFET or the like, and these first high-concentration impurity regions and a plurality of drain regions are directly or indirectly connected by a metal wiring layer through a resistor formed of a polycrystalline semiconductor layer or the like. A semiconductor device, which is connected to an output pad and is deeper than other portions only under the periphery of a contact hole in each region. 4. A semiconductor device comprising a plurality of input / output circuits and a power supply circuit arranged around a semiconductor substrate, wherein the input / output circuit and the power supply circuit have a first conductivity type first region in a second conductivity type low concentration region. A lateral bipolar transistor in which a second high-concentration impurity region and a third high-concentration impurity region of the second conductivity type are electrically separated by an element isolation region, a plurality of first conductivity type MOSFETs, and a plurality of MOSFETs Second conductivity type MO
The first high-concentration impurity region and the plurality of drain regions are formed by an SFET or the like, and these first high-concentration impurity regions and a plurality of drain regions are directly or indirectly connected by a metal wiring layer through a resistor formed of a polycrystalline semiconductor layer or the like. A region that is connected to the output pad and is deeper than other portions only below the periphery of the contact hole in each region, and a region deeper than the other portions in the high-concentration impurity region is the impurity ion of the high-concentration impurity region. After the implanting step, a photoetching step is performed to remove impurity ions from a mask material such as an oxide semiconductor layer shaped so as to have an opening at a contact hole position in the high-concentration impurity region connected to the input / output pad. A method for manufacturing a semiconductor device, which is formed by implantation. 5. The method of manufacturing a semiconductor device according to claim 2, wherein a region deeper than other portions below the contact hole in the high-concentration impurity region is deeper than the high-concentration impurity region by an impurity ion implantation step. The method for manufacturing a semiconductor device is characterized in that after the shallow region is formed, it is formed by ion implantation at an acceleration voltage higher than that at the time of forming the shallow region. 6. The method of manufacturing a semiconductor device according to claim 4, wherein a region deeper than other portions below the contact hole in the high-concentration impurity region is deeper than the high-concentration impurity region by a step of implanting impurity ions. The method for manufacturing a semiconductor device is characterized in that after the shallow region is formed, it is formed by ion implantation at an acceleration voltage higher than that at the time of forming the shallow region.