JPH09148456A - Semiconductor memory - Google Patents

Abstract

PROBLEM TO BE SOLVED: To suppress the increase of the power supply current of a high- resistance load type SRAM memory at standby time by commonly using a connecting section for connecting a pair of high-resistance elements formed in the extending direction of a word line to power supply wiring. SOLUTION: High-resistance areas 3 and 4 and 5 and 6 in two adjacent memory cells arranged in the extending direction of a word line 14 are constituted to have common connecting sections for respectively connecting the areas 3 and 4 and 5 and 6 to power supply wiring 1. Therefore, the increase of the power supply current of a semiconductor memory can be suppressed, because the lengths of the high-resistance areas can be prolonged by L2 in the word line extending direction in addition to the conventional length L1 in the bit line extending direction and a high-resistance element can be formed without lowering the resistance value even when the sizes of memory cells are reduced. In addition, when the resistance of the area in which the other ends of high- resistance loads are commonly connected to a power source is lowered, the voltage drop at the branch point of a high-resistance load can be reduced and the data holding characteristic of the memory can be improved.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated device, and more particularly to the structure of a semiconductor memory.

[0002]

2. Description of the Related Art A high resistance load type CMOS static R
The AM memory cell has the circuit configuration shown in FIG. The sources of the N-channel drive transistors N1 and N2 are connected to the ground potential, and one ends of the high resistance loads R1 and R2 are connected to the power supply. The drain of N1 and the other end of R1 are connected at contact A, and the drain of N2 and the other end of R2 are connected at contact B. The N-channel type transfer transistor N3 is connected between the contact A and the bit line BL, N4 is connected between the contact B and the bit line / BL, and each gate is connected to the word line WL.

FIG. 5 is an example of a conventional pattern plan view of FIG. Reference numeral 11 indicates a unit of the memory cell. 1
Reference numerals 7, 18, 19, 20, and 21 are N-type diffusion layers. The polysilicon gates 30, 31, 32, and 33 form drive transistors, and the word lines 14 form transfer transistors. The drain of the transfer transistor has contact holes 22, 23,
Connected to a bit line (not shown) by 24, 25,
The source of the drive transistor has a contact hole 3
Connected to a ground power source (not shown) by 4, 35.
Reference numerals 1, 3, 4, 5, 6 are polycrystalline polysilicon, and 2 is a mask pattern for forming a high resistance load element. For high integration of the memory cell, the power supply line and the high resistance load element are usually integrally formed of the same conductive layer. That is, since the polycrystalline polysilicon has a high resistance when it is deposited, the regions 3, 4, 5 and 6 for forming the high resistance load element have a resistance value using 2 as a mask so as to maintain a high resistance. Introducing N-type impurities such as As or P to reduce Therefore, of the polycrystalline polysilicon, only 3, 4, 5 and 6 are high resistance elements having a length L1.
1 is the word line 1 because other regions have low resistance
4 is formed as a low-resistance power wiring extending in the same direction as that of 4, and each of the high-resistance elements 3, 4, 5, 6 is independently connected to the power wiring 1. Reference numerals 7, 8, 9, 10 denote high resistance elements 3, 4, 5, 6 and the gate electrode 3 of the drive transistor formed thereunder via the low resistance regions.
0, 31, 32, 33 are contact holes for connecting to the gate electrode, and the gate electrode has a contact opening 2
6, 27, 28, 29 and 36 are connected to the source of the transfer transistor and the drain of the drive transistor to form the storage nodes A and B in FIG.

[0004]

A major feature of the CMOS static RAM is that the standby power supply current can be suppressed to a low level. In the case of a high resistance load type CMOS static RAM, the resistance value of the high resistance load can be reduced. Whether it can be increased or not is an important technical issue. In order to realize high resistance, means for narrowing the width of the element and reducing the thickness have been taken, but there are limitations in terms of processing accuracy and manufacturing problems. Moreover, as the size of the memory cell is reduced along with the miniaturization due to the progress of the manufacturing technology, the length L1 of the high resistance element is shortened with the above-mentioned conventional configuration, so that the high resistance value is reduced. It becomes very difficult to keep it, and there is a problem that the standby power supply current increases.

[0005]

According to the present invention, first and second transistors of a first conductivity type formed on a semiconductor substrate and an upper layer of the first and second transistors are provided. The first and second high resistance loads are formed of a conductive layer different from that of the second gate electrode.
The source of the second transistor is connected to a first potential, one end of the first high resistance load is connected to the drain of the first transistor and the gate electrode of the second transistor, and the second high resistance load is connected to the drain of the first transistor. In one of the semiconductor memory in which a plurality of memory cells connected to the drain of the second transistor and the gate electrode of the first transistor are arrayed, one end of the power supply line for supplying a second potential is the first and second power supply lines. Of the same conductive layer as that of the high resistance load and having a low resistance and extending in the same direction as the word line.
The other end of the first or second high resistance load formed in the memory cell is connected to the other end of the first or second high resistance load in the second memory cell adjacent in the word line direction. It is characterized in that they are commonly connected to the power supply wiring.

The present invention also relates to first and second transistors of the first conductivity type formed on a semiconductor substrate, and the first transistor.
First and second upper layers formed of a conductive layer different from the first and second gate electrodes, respectively.
Sources of the first and second transistors are connected to a first potential, and one end of the first high resistance load is connected to the drain of the first transistor and the second transistor. In the semiconductor memory connected to the gate electrode and having one end of the second high resistance load connected to the drain of the second transistor and the gate electrode of the first transistor, a power supply line for supplying a second potential is connected. It is formed in the same conductive layer as the first and second high resistance loads so as to have low resistance and extend in the same direction as the word line, and the other end of the first and second high resistance loads is connected to the power supply wiring. It is characterized in that it is commonly connected to.

Further, the present invention is characterized in that a region where the other end of the high resistance load is commonly connected to a power source has a low resistance.

[0008]

According to the above-mentioned structure of the present invention, the high resistance region is lengthened by making the connection portion of the pair of high resistance elements formed in the extending direction of the word line common to the power supply wiring. Therefore, even if the memory cell size is reduced, the resistance value of the load element can be formed without lowering the resistance value, which has the effect of suppressing an increase in the standby power supply current.

[0009]

1 is a pattern plan view of a first embodiment of the present invention. The present embodiment is a case where the present invention is applied to the above-mentioned conventional example, and the portions corresponding to the conventional example are denoted by the same reference numerals, and therefore the description thereof will be omitted and the characteristic points of the present invention will be described. The feature of the present invention is that the high resistance regions in two memory cells adjacent to each other in the direction in which the word line 14 extends, that is, 3 and 4 and 5 and 6 share the connection portion to the power supply wiring 1. is there. Therefore, the length of each high resistance region can be increased by L2 in the word line direction in addition to the conventional length L1 in the bit line direction, and the high resistance element does not decrease in resistance value even if the memory cell is reduced. Can be formed.

Here, a part of FIG. 1 is enlarged and shown in FIG.
R3 is a resistance formed from a boundary C between the high resistance region and the low resistance region to a point D where the high resistance elements 5 and 6 are connected. R4 is a resistor formed from the connection point D to the storage node E. For example, it is assumed that the data of the storage node E to which one end of the high resistance load 5 is connected is “0” and the data of the storage node F to which the high resistance load 6 is connected is “1”. Considering the resistance value and contact resistance in the low resistance region, which is sufficiently smaller than the resistance value of the high resistance load, and the leakage of the transistor, the current I flows from the power supply wiring 1 to the high resistance load 5. Therefore, the potential at the point D where the high resistance loads 5 and 6 branch off becomes VDD-I.R3, and the potential at the storage node F drops by I.R3 from the power supply voltage. This voltage drop may be a problem due to data retention characteristics. Therefore, FIG. 3 shows a pattern plan view of the second embodiment of the present invention. In this embodiment, the length of the mask region 2 for forming the high resistance in the bit line direction is reduced from the conventional L1 to L3, and the common lead-out region for connecting the high resistance region to the power supply line has the low resistance. I have to. Therefore, the influence of R3 in FIG. 2 is almost negligible, and the above-mentioned voltage drop problem is improved. In this case, L3 is shorter than L1.
Since the minimum width that can be processed separately from and is sufficient, it is shorter than the length L2 extended in the word line direction described above, and the high resistance of the load, which is the object of the present invention, is sufficiently achieved.

In the above-mentioned first and second embodiments, the example in which the high resistance elements in the adjacent different memory cells are commonly connected to the power supply wiring has been described, but the present invention is not limited to this. It will be easily understood that the same effect can be obtained even if the pair of high resistance load elements in the same memory cell are commonly connected to the power supply wiring.

[0012]

As described above, according to the present invention, even if the memory cell size is reduced, the length of the high resistance load element can be increased, so that the high resistance value is maintained. This makes it possible to suppress an increase in standby power supply current.

[Brief description of the drawings]

FIG. 1 is a pattern plan view showing an embodiment of the present invention.

FIG. 2 is an enlarged view of a high resistance region in FIG.

FIG. 3 is a pattern plan view showing another embodiment of the present invention.

FIG. 4 is a circuit diagram showing an SRAM memory cell.

FIG. 5 is a plan view of a conventional pattern.

[Explanation of symbols]

1 ... Power supply wiring 2 ... Mask pattern for forming high resistance load element 3, 4, 5, 6 ... High resistance load element 7, 8, 9, 10 ... Contact hole 11 ... Memory cell unit 14 ... Word line 17, 18, 19, 20, 21 ... N-type diffusion region 22, 23, 24, 25 ... Contact hole with bit line 26, 27, 28, 29 , 36 ... Contact opening 30, 31, 32, 33 ... Gate electrode 34, 35 ... Contact hole to ground line L1, L2, L3, L4 ... Dimension A, B ... Memory Nodes N1, N2, N3, N4 ... N-channel type transistors R1, R2 ... High resistance load BL, / BL ... Bit line WL ... Word line R3, R4 ... Resistance I ... Current C, D, E, F ... Connection point

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁶ Identification code Agency reference number FI Technical display location H01L 27/092

Claims (3)

[Claims] 1. A first conductivity type first and second transistor formed on a semiconductor substrate and a first gate electrode and a second gate electrode which are different from each other in an upper layer of the first and second transistors. The first and second high resistance loads are formed of a conductive layer, the sources of the first and second transistors are connected to a first potential, and one end of the first high resistance load is the first A memory cell connected to the drain of the second transistor and the gate electrode of the second transistor, and one end of the second high resistance load is connected to the drain of the second transistor and the gate electrode of the first transistor. In a plurality of arrayed semiconductor memories, a power supply line for supplying a second potential is formed in the same conductive layer as the first and second high resistance loads with low resistance and extending in the same direction as the word line. , The other end of the first or second high resistance load formed in the first memory cell has the other end of the first or second high resistance load in the second memory cell adjacent in the word line direction. A semiconductor memory characterized in that it is connected to the power supply wiring in common with the other end. 2. A first conductivity type first and second transistor formed on a semiconductor substrate and a first gate electrode and a second gate electrode which are different from each other in an upper layer of the first and second transistors. The first and second high resistance loads are formed of a conductive layer, the sources of the first and second transistors are connected to a first potential, and one end of the first high resistance load is the first In the semiconductor memory, the drain of the second transistor and the gate electrode of the second transistor are connected, and one end of the second high resistance load is connected to the drain of the second transistor and the gate electrode of the first transistor. , A power supply line for supplying a second potential to the first
And the second high resistance load is formed in the same conductive layer as the low resistance and extends in the same direction as the word line, and the other ends of the first and second high resistance loads are commonly used for the power supply wiring. A semiconductor memory characterized by being connected. 3. The semiconductor memory according to claim 1, wherein a region where the other end of the high resistance load is commonly connected to a power source has low resistance.