JPH09148456A - Semiconductor memory - Google Patents

Semiconductor memory

Info

Publication number
JPH09148456A
JPH09148456A JP7303156A JP30315695A JPH09148456A JP H09148456 A JPH09148456 A JP H09148456A JP 7303156 A JP7303156 A JP 7303156A JP 30315695 A JP30315695 A JP 30315695A JP H09148456 A JPH09148456 A JP H09148456A
Authority
JP
Japan
Prior art keywords
high resistance
transistor
power supply
resistance
gate electrode
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP7303156A
Other languages
Japanese (ja)
Inventor
Satoru Kodaira
覚 小平
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Epson Corp
Original Assignee
Seiko Epson Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Epson Corp filed Critical Seiko Epson Corp
Priority to JP7303156A priority Critical patent/JPH09148456A/en
Publication of JPH09148456A publication Critical patent/JPH09148456A/en
Pending legal-status Critical Current

Links

Landscapes

  • Semiconductor Integrated Circuits (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Semiconductor Memories (AREA)

Abstract

PROBLEM TO BE SOLVED: To suppress the increase of the power supply current of a high- resistance load type SRAM memory at standby time by commonly using a connecting section for connecting a pair of high-resistance elements formed in the extending direction of a word line to power supply wiring. SOLUTION: High-resistance areas 3 and 4 and 5 and 6 in two adjacent memory cells arranged in the extending direction of a word line 14 are constituted to have common connecting sections for respectively connecting the areas 3 and 4 and 5 and 6 to power supply wiring 1. Therefore, the increase of the power supply current of a semiconductor memory can be suppressed, because the lengths of the high-resistance areas can be prolonged by L2 in the word line extending direction in addition to the conventional length L1 in the bit line extending direction and a high-resistance element can be formed without lowering the resistance value even when the sizes of memory cells are reduced. In addition, when the resistance of the area in which the other ends of high- resistance loads are commonly connected to a power source is lowered, the voltage drop at the branch point of a high-resistance load can be reduced and the data holding characteristic of the memory can be improved.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【発明の属する技術分野】本発明は半導体集積装置に関
し、特に半導体メモリの構造に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated device, and more particularly to the structure of a semiconductor memory.

【0002】[0002]

【従来の技術】高抵抗負荷型のCMOSスタティックR
AMのメモリセルは図4に示す回路構成をとる。Nチャ
ンネル型ドライブトランジスタN1,N2のソースは接
地電位に接続され、高抵抗負荷R1,R2の一端は電源
に接続さる。N1のドレインとR1の他端は接点Aにお
いて接続され、N2のドレインとR2の他端は接点Bに
おいて接続される。Nチャンネル型トランスファトラン
ジスタN3は接点Aとビット線BLの間に、N4は接点
Bとビット線/BLの間に接続され、各々のゲートはワ
ード線WLに接続されている。
2. Description of the Related Art A high resistance load type CMOS static R
The AM memory cell has the circuit configuration shown in FIG. The sources of the N-channel drive transistors N1 and N2 are connected to the ground potential, and one ends of the high resistance loads R1 and R2 are connected to the power supply. The drain of N1 and the other end of R1 are connected at contact A, and the drain of N2 and the other end of R2 are connected at contact B. The N-channel type transfer transistor N3 is connected between the contact A and the bit line BL, N4 is connected between the contact B and the bit line / BL, and each gate is connected to the word line WL.

【0003】図5は図4の従来のパターン平面図の一例
である。11はメモリセルの一単位を示している。1
7,18,19,20,21はN型の拡散層であり、ポ
リシリコンゲート30,31,32,33によってドラ
イブトランジスタが形成され、ワード線14によってト
ランスファトランジスタが形成される。前記トランスフ
ァトランジスタのドレインはコンタクト孔22,23,
24,25によってビット線(図示せず)に接続され、
前記ドライブトランジスタのソースはコンタクト孔3
4,35によって接地電源(図示せず)に接続される。
1,3,4,5,6は多結晶ポリシリコンであり、2は
高抵抗負荷素子を形成するためのマスクパターンであ
る。メモリセルの高集積化のため、通常電源配線と高抵
抗負荷素子とは同一導電層で一体に形成される。すなわ
ち、前記多結晶ポリシリコンは堆積された段階では高抵
抗を有するため、高抵抗負荷素子を形成するための領域
3,4,5,6は高抵抗を保つように、2をマスクとし
て抵抗値を低減するためのN型の不純物であるAsまた
はP等を導入する。従って前記多結晶ポリシリコンのう
ち、3,4,5,6のみ長さL1の高抵抗素子となり、
その他の領域が低抵抗になるため、1がワードライン1
4と同一方向に延在する低抵抗な電源配線として形成さ
れ、、高抵抗素子3,4,5,6のそれぞれが独立に電
源配線1と接続している。また、7,8,9,10は前
記低抵抗領域を介して高抵抗素子3,4,5,6とその
下層に形成されるドライブトランジスタのゲート電極3
0,31,32,33とを接続するためのコンタクト孔
であり、さらに前記ゲート電極がコンタクト開口部2
6,27,28,29,36によってトランスファトラ
ンジスタのソース及びドライブトランジスタのドレイン
に接続されて図4中の記憶ノードA,Bを形成する。
FIG. 5 is an example of a conventional pattern plan view of FIG. Reference numeral 11 indicates a unit of the memory cell. 1
Reference numerals 7, 18, 19, 20, and 21 are N-type diffusion layers. The polysilicon gates 30, 31, 32, and 33 form drive transistors, and the word lines 14 form transfer transistors. The drain of the transfer transistor has contact holes 22, 23,
Connected to a bit line (not shown) by 24, 25,
The source of the drive transistor has a contact hole 3
Connected to a ground power source (not shown) by 4, 35.
Reference numerals 1, 3, 4, 5, 6 are polycrystalline polysilicon, and 2 is a mask pattern for forming a high resistance load element. For high integration of the memory cell, the power supply line and the high resistance load element are usually integrally formed of the same conductive layer. That is, since the polycrystalline polysilicon has a high resistance when it is deposited, the regions 3, 4, 5 and 6 for forming the high resistance load element have a resistance value using 2 as a mask so as to maintain a high resistance. Introducing N-type impurities such as As or P to reduce Therefore, of the polycrystalline polysilicon, only 3, 4, 5 and 6 are high resistance elements having a length L1.
1 is the word line 1 because other regions have low resistance
4 is formed as a low-resistance power wiring extending in the same direction as that of 4, and each of the high-resistance elements 3, 4, 5, 6 is independently connected to the power wiring 1. Reference numerals 7, 8, 9, 10 denote high resistance elements 3, 4, 5, 6 and the gate electrode 3 of the drive transistor formed thereunder via the low resistance regions.
0, 31, 32, 33 are contact holes for connecting to the gate electrode, and the gate electrode has a contact opening 2
6, 27, 28, 29 and 36 are connected to the source of the transfer transistor and the drain of the drive transistor to form the storage nodes A and B in FIG.

【0004】[0004]

【発明が解決しようとする課題】CMOS型スタティッ
クRAMの大きな特徴は、待機時電源電流を低く抑えら
れることであり、高抵抗負荷型のCMOSスタティック
RAMの場合には高抵抗負荷の抵抗値をいかに大きくす
ることができるかが重要な技術的課題である。高抵抗を
実現するために、素子の幅を細く、厚さを薄くする手段
がとられてきたが、加工精度の問題や製造上の問題から
いずれも限界がある。しかも、製造技術の進歩による微
細化に伴って、メモリセルのサイズが縮小されるにした
がい、前述した従来の構成のままでは高抵抗素子の長さ
L1が短くなってしまうため、高抵抗値を保つことが非
常に困難になり、待機時電源電流の増加するという問題
が生じる。
A major feature of the CMOS static RAM is that the standby power supply current can be suppressed to a low level. In the case of a high resistance load type CMOS static RAM, the resistance value of the high resistance load can be reduced. Whether it can be increased or not is an important technical issue. In order to realize high resistance, means for narrowing the width of the element and reducing the thickness have been taken, but there are limitations in terms of processing accuracy and manufacturing problems. Moreover, as the size of the memory cell is reduced along with the miniaturization due to the progress of the manufacturing technology, the length L1 of the high resistance element is shortened with the above-mentioned conventional configuration, so that the high resistance value is reduced. It becomes very difficult to keep it, and there is a problem that the standby power supply current increases.

【0005】[0005]

【課題を解決するための手段】本発明は、半導体基板上
に形成された第1導電型の第1及び第2のトランジスタ
と、前記第1及び第2のトランジスタの上層に、前記第
1及び第2のゲート電極とは異なる導電層で形成される
第1及び第2の高抵抗負荷から成り、前記第1及び第2
のトランジスタのソースが第1の電位に接続され、前記
第1の高抵抗負荷の一端は前記第1のトランジスタのド
レイン及び前記第2のトランジスタのゲート電極に接続
され、前記第2の高抵抗負荷の一端は前記第2のトラン
ジスタのドレイン及び前記第1のトランジスタのゲート
電極に接続されたメモリセルを複数個アレイした半導体
メモリにおいて、第2の電位を供給する電源配線を前記
第1及び第2の高抵抗負荷と同一導電層で低抵抗にかつ
ワードラインと同一方向に延在するように形成し、第1
のメモリセル内に形成される前記第1または第2の高抵
抗負荷の他端は、ワードライン方向に隣接する第2のメ
モリセル内の前記第1または第2の高抵抗負荷の他端と
共通に前記電源配線に接続したことを特徴とする。
According to the present invention, first and second transistors of a first conductivity type formed on a semiconductor substrate and an upper layer of the first and second transistors are provided. The first and second high resistance loads are formed of a conductive layer different from that of the second gate electrode.
The source of the second transistor is connected to a first potential, one end of the first high resistance load is connected to the drain of the first transistor and the gate electrode of the second transistor, and the second high resistance load is connected to the drain of the first transistor. In one of the semiconductor memory in which a plurality of memory cells connected to the drain of the second transistor and the gate electrode of the first transistor are arrayed, one end of the power supply line for supplying a second potential is the first and second power supply lines. Of the same conductive layer as that of the high resistance load and having a low resistance and extending in the same direction as the word line.
The other end of the first or second high resistance load formed in the memory cell is connected to the other end of the first or second high resistance load in the second memory cell adjacent in the word line direction. It is characterized in that they are commonly connected to the power supply wiring.

【0006】また本発明は、半導体基板上に形成された
第1導電型の第1及び第2のトランジスタと、前記第1
及び第2のトランジスタの上層に、前記第1及び第2の
ゲート電極とは異なる導電層で形成される第1及び第2
の高抵抗負荷から成り、前記第1及び第2のトランジス
タのソースが第1の電位に接続され、前記第1の高抵抗
負荷の一端は前記第1のトランジスタのドレイン及び前
記第2のトランジスタのゲート電極に接続され、前記第
2の高抵抗負荷の一端は前記第2のトランジスタのドレ
イン及び前記第1のトランジスタのゲート電極に接続さ
れた半導体メモリにおいて、第2の電位を供給する電源
配線を前記第1及び第2の高抵抗負荷と同一導電層で低
抵抗にかつワード線と同一方向に延在するように形成
し、前記第1及び第2の高抵抗負荷の他端を前記電源配
線に共通に接続したことを特徴とする。
The present invention also relates to first and second transistors of the first conductivity type formed on a semiconductor substrate, and the first transistor.
First and second upper layers formed of a conductive layer different from the first and second gate electrodes, respectively.
Sources of the first and second transistors are connected to a first potential, and one end of the first high resistance load is connected to the drain of the first transistor and the second transistor. In the semiconductor memory connected to the gate electrode and having one end of the second high resistance load connected to the drain of the second transistor and the gate electrode of the first transistor, a power supply line for supplying a second potential is connected. It is formed in the same conductive layer as the first and second high resistance loads so as to have low resistance and extend in the same direction as the word line, and the other end of the first and second high resistance loads is connected to the power supply wiring. It is characterized in that it is commonly connected to.

【0007】また本発明は、前記高抵抗負荷の他端が電
源に共通に接続される領域は低抵抗であることを特徴と
する。
Further, the present invention is characterized in that a region where the other end of the high resistance load is commonly connected to a power source has a low resistance.

【0008】[0008]

【作用】本発明の上記の構成によれば、ワード線が延在
する方向に形成される一対の高抵抗素子どうしの電源配
線への接続部分を共通にすることで、高抵抗領域を長く
することができるため、メモリセルサイズが縮小されて
も負荷素子の抵抗値を下げることなく形成できることに
より、待機時電源電流の増加を抑える作用がある。
According to the above-mentioned structure of the present invention, the high resistance region is lengthened by making the connection portion of the pair of high resistance elements formed in the extending direction of the word line common to the power supply wiring. Therefore, even if the memory cell size is reduced, the resistance value of the load element can be formed without lowering the resistance value, which has the effect of suppressing an increase in the standby power supply current.

【0009】[0009]

【発明の実施の形態】図1は本発明の第一の実施例のパ
ターン平面図である。本実施例は前述した従来例に本発
明を適用した場合であり、従来例に対応する箇所には同
一符号を付けているため説明は省略し、本発明の特徴と
なる点を説明する。本発明の特徴は、ワード線14が延
在する方向に隣接する2つのメモリセル内の高抵抗領
域、即ち3と4及び5と6が電源配線1への接続部分を
共有していることにある。従って、それぞれの高抵抗領
域長は従来のビット線方向の長さL1に加えてワード線
方向にL2だけ長くすることが可能となり、メモリセル
が縮小しても抵抗値を下げることなく高抵抗素子を形成
することが可能である。
1 is a pattern plan view of a first embodiment of the present invention. The present embodiment is a case where the present invention is applied to the above-mentioned conventional example, and the portions corresponding to the conventional example are denoted by the same reference numerals, and therefore the description thereof will be omitted and the characteristic points of the present invention will be described. The feature of the present invention is that the high resistance regions in two memory cells adjacent to each other in the direction in which the word line 14 extends, that is, 3 and 4 and 5 and 6 share the connection portion to the power supply wiring 1. is there. Therefore, the length of each high resistance region can be increased by L2 in the word line direction in addition to the conventional length L1 in the bit line direction, and the high resistance element does not decrease in resistance value even if the memory cell is reduced. Can be formed.

【0010】ここで図1の一部を拡大して図2に示す。
R3は高抵抗領域と低抵抗領域との境界Cから高抵抗素
子5と6とが接続される点Dまでの間に形成される抵
抗。R4は前記接続点Dから記憶ノードEまでに形成さ
れる抵抗である。例えば高抵抗負荷5の一端が接続され
る記憶ノードEのデータが”0”で、高抵抗負荷6が接
続される記憶ノードFのデータが”1”であると仮定す
る。高抵抗負荷の抵抗値に比べて十分小さい低抵抗領域
の抵抗値及びコンタクト抵抗と、トランジスタのリーク
等を無視して考えると、電源配線1から電流Iが高抵抗
負荷5に流れることになる。従って高抵抗負荷5と6が
分岐する点Dの電位は、 VDD−I・R3 となってしまうため、記憶ノードFの電位は電源電圧よ
りI・R3だけ降下することになる。データ保持特性上
この電圧降下が問題となる場合がある。そこで、図3に
本発明の第二の実施例のパターン平面図を示す。本実施
例では、高抵抗を形成するためのマスク領域2のビット
線方向の長さを従来のL1からL3に縮小し、高抵抗領
域から電源配線に接続するための共通の引きだし領域を
低抵抗にしている。したがって図2中のR3の影響はほ
とんど無視できるため、前述した電圧降下の問題は改善
される。この場合L3はL1に比べて短くなってしまう
が、引き出しの長さL4は、製造上ポリシリコン1と6
とを分離して加工できる最小幅だけあれば良いため、前
述したワード線方向に延長される長さL2比べると短
く、本発明の目的である負荷の高抵抗化は十分に達成さ
れる。
Here, a part of FIG. 1 is enlarged and shown in FIG.
R3 is a resistance formed from a boundary C between the high resistance region and the low resistance region to a point D where the high resistance elements 5 and 6 are connected. R4 is a resistor formed from the connection point D to the storage node E. For example, it is assumed that the data of the storage node E to which one end of the high resistance load 5 is connected is “0” and the data of the storage node F to which the high resistance load 6 is connected is “1”. Considering the resistance value and contact resistance in the low resistance region, which is sufficiently smaller than the resistance value of the high resistance load, and the leakage of the transistor, the current I flows from the power supply wiring 1 to the high resistance load 5. Therefore, the potential at the point D where the high resistance loads 5 and 6 branch off becomes VDD-I.R3, and the potential at the storage node F drops by I.R3 from the power supply voltage. This voltage drop may be a problem due to data retention characteristics. Therefore, FIG. 3 shows a pattern plan view of the second embodiment of the present invention. In this embodiment, the length of the mask region 2 for forming the high resistance in the bit line direction is reduced from the conventional L1 to L3, and the common lead-out region for connecting the high resistance region to the power supply line has the low resistance. I have to. Therefore, the influence of R3 in FIG. 2 is almost negligible, and the above-mentioned voltage drop problem is improved. In this case, L3 is shorter than L1.
Since the minimum width that can be processed separately from and is sufficient, it is shorter than the length L2 extended in the word line direction described above, and the high resistance of the load, which is the object of the present invention, is sufficiently achieved.

【0011】尚、上記第一及び第2の実施例では、隣接
した異なるメモリセル内の高抵抗素子の電源配線への接
続を共通にする例について説明したが、本発明はこれに
限られるものではなく、同一メモリセル内の一対の高抵
抗負荷素子の電源配線への接続を共通にしても、同様な
効果が得られることは容易に理解できるであろう。
In the above-mentioned first and second embodiments, the example in which the high resistance elements in the adjacent different memory cells are commonly connected to the power supply wiring has been described, but the present invention is not limited to this. It will be easily understood that the same effect can be obtained even if the pair of high resistance load elements in the same memory cell are commonly connected to the power supply wiring.

【0012】[0012]

【発明の効果】以上述べてきた様に、本発明によればメ
モリセルサイズが縮小しても、高抵抗負荷素子の長さを
長く形成することが可能であるため、高抵抗値を維持す
ることができ、待機時電源電流の増加を抑えることが可
能となった。
As described above, according to the present invention, even if the memory cell size is reduced, the length of the high resistance load element can be increased, so that the high resistance value is maintained. This makes it possible to suppress an increase in standby power supply current.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明の一実施例を示すパターン平面図。FIG. 1 is a pattern plan view showing an embodiment of the present invention.

【図2】図1の高抵抗領域の拡大図。FIG. 2 is an enlarged view of a high resistance region in FIG.

【図3】本発明の他の実施例を示すパターン平面図。FIG. 3 is a pattern plan view showing another embodiment of the present invention.

【図4】SRAMのメモリセルを示す回路図。FIG. 4 is a circuit diagram showing an SRAM memory cell.

【図5】従来のパターン平面図。FIG. 5 is a plan view of a conventional pattern.

【符号の説明】[Explanation of symbols]

1・・・電源配線 2・・・高抵抗負荷素子を形成するためのマスクパター
ン 3,4,5,6・・・高抵抗負荷素子 7,8,9,10・・・コンタクト孔 11・・・メモリセル単位 14・・・ワード線 17,18,19,20,21・・・N型の拡散領域 22,23,24,25・・・ビット線とのコンタクト
孔 26,27,28,29,36・・・コンタクト開口部 30,31,32,33・・・ゲート電極 34,35・・・接地線へのコンタクト孔 L1,L2,L3,L4・・・寸法 A,B・・・記憶ノード N1,N2,N3,N4・・・Nチャンネル型トランジ
スタ R1,R2・・・高抵抗負荷 BL,/BL・・・ビット線 WL・・・ワード線 R3,R4・・・抵抗 I・・・電流 C,D,E,F・・・接続点
1 ... Power supply wiring 2 ... Mask pattern for forming high resistance load element 3, 4, 5, 6 ... High resistance load element 7, 8, 9, 10 ... Contact hole 11 ... Memory cell unit 14 ... Word line 17, 18, 19, 20, 21 ... N-type diffusion region 22, 23, 24, 25 ... Contact hole with bit line 26, 27, 28, 29 , 36 ... Contact opening 30, 31, 32, 33 ... Gate electrode 34, 35 ... Contact hole to ground line L1, L2, L3, L4 ... Dimension A, B ... Memory Nodes N1, N2, N3, N4 ... N-channel type transistors R1, R2 ... High resistance load BL, / BL ... Bit line WL ... Word line R3, R4 ... Resistance I ... Current C, D, E, F ... Connection point

───────────────────────────────────────────────────── フロントページの続き (51)Int.Cl.6 識別記号 庁内整理番号 FI 技術表示箇所 H01L 27/092 ──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. 6 Identification code Agency reference number FI Technical display location H01L 27/092

Claims (3)

【特許請求の範囲】[Claims] 【請求項1】半導体基板上に形成された第1導電型の第
1及び第2のトランジスタと、前記第1及び第2のトラ
ンジスタの上層に、前記第1及び第2のゲート電極とは
異なる導電層で形成される第1及び第2の高抵抗負荷か
ら成り、前記第1及び第2のトランジスタのソースが第
1の電位に接続され、前記第1の高抵抗負荷の一端は前
記第1のトランジスタのドレイン及び前記第2のトラン
ジスタのゲート電極に接続され、前記第2の高抵抗負荷
の一端は前記第2のトランジスタのドレイン及び前記第
1のトランジスタのゲート電極に接続されたメモリセル
を複数個アレイした半導体メモリにおいて、第2の電位
を供給する電源配線を前記第1及び第2の高抵抗負荷と
同一導電層で低抵抗にかつワードラインと同一方向に延
在するように形成し、第1のメモリセル内に形成される
前記第1または第2の高抵抗負荷の他端は、ワードライ
ン方向に隣接する第2のメモリセル内の前記第1または
第2の高抵抗負荷の他端と共通に前記電源配線に接続し
たことを特徴とする半導体メモリ。
1. A first conductivity type first and second transistor formed on a semiconductor substrate and a first gate electrode and a second gate electrode which are different from each other in an upper layer of the first and second transistors. The first and second high resistance loads are formed of a conductive layer, the sources of the first and second transistors are connected to a first potential, and one end of the first high resistance load is the first A memory cell connected to the drain of the second transistor and the gate electrode of the second transistor, and one end of the second high resistance load is connected to the drain of the second transistor and the gate electrode of the first transistor. In a plurality of arrayed semiconductor memories, a power supply line for supplying a second potential is formed in the same conductive layer as the first and second high resistance loads with low resistance and extending in the same direction as the word line. , The other end of the first or second high resistance load formed in the first memory cell has the other end of the first or second high resistance load in the second memory cell adjacent in the word line direction. A semiconductor memory characterized in that it is connected to the power supply wiring in common with the other end.
【請求項2】半導体基板上に形成された第1導電型の第
1及び第2のトランジスタと、前記第1及び第2のトラ
ンジスタの上層に、前記第1及び第2のゲート電極とは
異なる導電層で形成される第1及び第2の高抵抗負荷か
ら成り、前記第1及び第2のトランジスタのソースが第
1の電位に接続され、前記第1の高抵抗負荷の一端は前
記第1のトランジスタのドレイン及び前記第2のトラン
ジスタのゲート電極に接続され、前記第2の高抵抗負荷
の一端は前記第2のトランジスタのドレイン及び前記第
1のトランジスタのゲート電極に接続された半導体メモ
リにおいて、第2の電位を供給する電源配線を前記第1
及び第2の高抵抗負荷と同一導電層で低抵抗にかつワー
ド線と同一方向に延在するように形成し、前記第1及び
第2の高抵抗負荷の他端を前記電源配線に共通に接続し
たことを特徴とする半導体メモリ。
2. A first conductivity type first and second transistor formed on a semiconductor substrate and a first gate electrode and a second gate electrode which are different from each other in an upper layer of the first and second transistors. The first and second high resistance loads are formed of a conductive layer, the sources of the first and second transistors are connected to a first potential, and one end of the first high resistance load is the first In the semiconductor memory, the drain of the second transistor and the gate electrode of the second transistor are connected, and one end of the second high resistance load is connected to the drain of the second transistor and the gate electrode of the first transistor. , A power supply line for supplying a second potential to the first
And the second high resistance load is formed in the same conductive layer as the low resistance and extends in the same direction as the word line, and the other ends of the first and second high resistance loads are commonly used for the power supply wiring. A semiconductor memory characterized by being connected.
【請求項3】前記高抵抗負荷の他端が電源に共通に接続
される領域は低抵抗であることを特徴とする特許請求項
1または請求項2に記載の半導体メモリ。
3. The semiconductor memory according to claim 1, wherein a region where the other end of the high resistance load is commonly connected to a power source has low resistance.
JP7303156A 1995-11-21 1995-11-21 Semiconductor memory Pending JPH09148456A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7303156A JPH09148456A (en) 1995-11-21 1995-11-21 Semiconductor memory

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7303156A JPH09148456A (en) 1995-11-21 1995-11-21 Semiconductor memory

Publications (1)

Publication Number Publication Date
JPH09148456A true JPH09148456A (en) 1997-06-06

Family

ID=17917561

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7303156A Pending JPH09148456A (en) 1995-11-21 1995-11-21 Semiconductor memory

Country Status (1)

Country Link
JP (1) JPH09148456A (en)

Similar Documents

Publication Publication Date Title
US6128209A (en) Semiconductor memory device having dummy bit and word lines
KR20020034313A (en) Method of manufacturing sram cell
US6791200B2 (en) Semiconductor memory device
US6445041B1 (en) Semiconductor memory cell array with reduced parasitic capacitance between word lines and bit lines
JPH0419711B2 (en)
US6445017B2 (en) Full CMOS SRAM cell
JP2748885B2 (en) Semiconductor integrated circuit device
JPH06104405A (en) Static memory
JPS5884456A (en) Integrated circuit bipolar memory cell
JP3058119B2 (en) Method for manufacturing semiconductor device
US5761113A (en) Soft error suppressing resistance load type SRAM cell
JP3400894B2 (en) Static semiconductor memory device
US5675533A (en) Semiconductor device
JPH09148456A (en) Semiconductor memory
US5239201A (en) Semiconductor memory device
US5267208A (en) Semiconductor memory device
KR900002008B1 (en) The static memory cell having a double poly-crystal structure
JP2001024070A (en) Semiconductor memory
JP3200862B2 (en) Semiconductor storage device
JP2723678B2 (en) Semiconductor storage device
JPH07240476A (en) Semiconductor integrated circuit device and its fabrication
KR200157364Y1 (en) Structure of a sram semiconductor device
JPH0513722A (en) Semiconductor storage device
KR960011106B1 (en) Semiconductor memory device
JPH0448650A (en) Semiconductor memory