JPH09148445A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce the number of manufacturing processes of a semiconductor device having a fuse provided for redundant circuit and, at the same time, to improve the degree of integration of the device. SOLUTION: Part of a first wiring layer is formed in guard rings 15A and 16B having annular shapes surrounding a prescribed area of a semiconductor substrate 11 and a plurality of melting fuse wiring 19 is formed on the substrate 11 within the area surrounded by the rings 16A and 16B. Then an interlayer insulating film 14 is formed on the wiring 19 and rings 16A and 16B and first and second insulating films 15 and 16 are successively formed on the film 14. In addition, an opening 18 is formed through the insulating films 15 and 16 in an area containing the area surrounded by the rings 16A and 16B and a fuse in which the interlayer insulating film 14 is exposed from the opening 18 is provided.

Description

Detailed Description of the Invention

[0001]

The present invention relates to a semiconductor device,
More specifically, it relates to improvement of a semiconductor device having a fuse provided for a redundant circuit. 2. Description of the Related Art In recent years, semiconductor integrated circuits have become faster and more highly integrated with advances in miniaturization technology. In particular, in the field of memory, high integration and high yield are required, and a redundant technique for providing a redundant circuit to improve the yield is indispensable.

[0002]

2. Description of the Related Art A conventional semiconductor device will be described below. In order to prevent a decrease in the yield of semiconductor devices due to process defects, the circuit of the device is provided with redundancy,
A redundant design technique is adopted so that the function of the LSI is not impaired even if there are a few defects. For example, RA
For M, EPROM, etc., there is a method of preparing a spare memory and using the spare array when the main body memory array has a defect. One of the methods of switching the spare memory array is a fuse blowing method using a laser. .

In this case, in order to simplify the handling,
In the semiconductor device, the above fuses are put together in one place as shown in FIG. FIG. 5 shows a top view of a fuse portion of a conventional semiconductor device. 6 is a sectional view taken along the line BB of FIG. As shown in FIG. 6, this cross-sectional structure has a LOCOS (Local oxidation of Silicon) structure on a semiconductor substrate (1).
n) The film (2, 7A, 7B) is formed, and the diffusion layer (6C) is formed on the surface of the semiconductor substrate (1) between the LOCOS film (2) and the LOCOS film (7A), and the LOCOS film (7A).
And a LOCOS film (7B), a diffusion layer (6D) is formed on the surface of the semiconductor substrate (1), and BPSG (Bo
ron Phoso-Silicate Glass) film (3) is formed thereon, and openings are formed in the diffusion layer (6C) forming region and the diffusion layer (6D) forming region and the aluminum is formed in the opening. A guard ring (6A, 6B) is formed, and a passivation film (4) such as a SiN film is formed on the guard ring (6A, 6B) so as to cover the guard ring (6A, 6B), and a polyimide film (5) is formed thereon. Are formed.

The polyimide film (5) is provided with a repair window (8) for facilitating the blowout of a fuse wiring (9) which will be described later. At the same time, the passivation film (4) is also blown by the fuse. (OP) is opened, and the BPSG film (3) is exposed from this opening (OP). When viewed from above, as shown in FIG. 5, the guard rings (6A, 6B) are annularly formed inside the repair window (8) so as to doubly surround the fuse formation region. A plurality of fuse wirings (9) made of polycide or the like are formed in parallel across each other. Although not shown in FIG. 6, the fuse wiring (9) is formed under the BPSG film (3).

To fuse the fuse wiring (9), an argon laser or the like is exposed through the repair window (8).
The desired fuse wiring (9) is irradiated through the film (3). As a result, the irradiated fuse wiring (9) is blown and a desired redundant circuit is selected.

[0006]

However, in order to manufacture the fuse having the above-mentioned conventional structure, the repair window (8) is formed in the polyimide film (5) in the region where the fuse is formed so that the fuse can be blown. A total of two steps are required: a step and a step of forming an opening (OP) in the passivation film (4) to expose the BPSG film (3), and the polyimide film (5) and the passivation film (4) are simultaneously formed. There has been a demand for reducing the number of steps by etching and forming a fuse in one etching step.

However, when the polyimide film (5) and the passivation film (4) are simultaneously etched, as shown in FIG. 7, the repair window (8) is passed through the guard ring (6A, 6B).
Will be exposed. In order to avoid this, the guard rings (6A, 6B) are arranged outside the fuses shown in FIGS. 6 and 7 to avoid the region where the repair window (8) is formed, and the guard rings (6A, 6B) are not exposed. However, since the guard ring (6A, 6B) expands, the chip size increases, which hinders integration.

[0008]

The present invention has been made in view of the above-mentioned drawbacks of the prior art. As illustrated in FIG. 1, a first wiring layer formed on a semiconductor substrate and the first wiring layer are provided. A semiconductor device having a multilayer wiring structure in which a second wiring layer is formed on a wiring layer via an interlayer insulating film, wherein a part of the first wiring layer surrounds a predetermined region of the semiconductor substrate and has a ring shape. A plurality of fusing fuse wires are formed on the semiconductor substrate in a region surrounded by the guard ring, and the interlayer insulating film is formed on the fusing fuse wires and the guard ring. A first insulating film and a second insulating film are sequentially formed on the interlayer insulating film, and openings are formed in the first and second insulating films in a region including a region surrounded by the guard ring. The interlayer insulating film is opened from this opening. The semiconductor device including a fuse made out, a reduced number of manufacturing steps, intended to form the fuse without increasing the chip size.

[0009]

DESCRIPTION OF THE PREFERRED EMBODIMENTS A fuse, which is a semiconductor device according to an embodiment of the present invention, will be described below with reference to the drawings. In order to prevent a decrease in the yield of semiconductor devices due to process defects, a redundancy design technique is employed in which the circuit of the device is provided with redundancy so that the function of the LSI is not impaired even if there are a few defects. . This is a method in which a spare memory is prepared in RAM, EPROM, etc., and the spare array is used when the main body memory array is defective. One of the methods for switching to the spare memory array is a fuse blowing method using a laser.

In this case, in order to simplify the handling,
In the semiconductor device, the above fuses are put together in one place as shown in FIG. The semiconductor device of this embodiment is a semiconductor device having a multilayer wiring structure in which an upper layer wiring is formed on a lower layer wiring formed on a semiconductor substrate (11) via a plasma TEOS film (14) which is an interlayer insulating film. is there.

FIG. 1 is a top view of a fuse portion of a semiconductor device which is a feature of the present invention. FIG. 2 is a sectional view taken along line AA of FIG. As shown in FIG. 2, the cross-sectional structure is such that LOCOS (Local oxidation of S) is formed on the semiconductor substrate (11).
(ilicon) film (12, 17A, 17B) is formed, and LO
A diffusion layer (16C) is formed on the surface of the semiconductor substrate (11) between the COS film (12) and the LOCOS film (17A).
Diffusion layers (16D) are formed on the surface of the semiconductor substrate (11) between the S film (17A) and the LOCOS film (17B), and a BPSG (Boron Phoso-Silicate Glass) film (13) is formed on them. An opening is formed in the BPSG film (13) in the formation area of the diffusion layer (16C) and the formation area of the diffusion layer (16D), and a guard ring (6A, 6B) made of aluminum or the like is formed in the opening. A plasma TEOS film (14) serving as the above-described interlayer insulating film is formed thereon, and a passivation film (15) and a polyimide film (16) are sequentially formed thereon.

A repair window (18) is formed in the polyimide film (16) and the passivation film (15) in order to facilitate melting of a fuse wiring (19) described later.
From this repair window (18), the plasma TEOS film (14)
Is exposed. When viewed from above, the guard rings (16A, 16B) have repair windows (1
8) is formed in a ring shape so as to doubly surround the fuse formation region, and a plurality of fuse wirings (19) made of polycide are arranged in parallel across the fuse formation region. Although not shown in FIG. 2, the fuse wiring (19) is formed by plasma TEOS film (1).
4) Formed in the lower layer.

To fuse the fuse wire (19), an argon laser or the like is applied to the desired fuse wire (19) through the plasma TEOS film (14) exposed through the repair window (18). As a result, the irradiated fuse wiring (19) is blown and a desired redundant circuit is selected. In order to manufacture the fuse as shown in FIGS. 1 and 2, the LOC is formed on the semiconductor substrate (11) by the selective oxidation method.
An OS film (12, 17A, 17B) is formed, an impurity is injected into a region where a guard ring is formed, and a diffusion layer (16C,
16D), a polycide layer is formed and then patterned to form a fuse wiring (19), and a BPSG film (13) is formed by an ordinary method.

Next, the BP of the area where the guard ring is formed
An opening is formed in the SG film (13), an aluminum layer to be a lower wiring layer is formed by a sputtering method, and patterning is performed to form a lower wiring layer in another region (not shown), and at the same time, a region where a fuse is formed. Guard rings (16A, 16B) are formed so as to surround the. Next, a plasma TEOS film (14) serving as an interlayer insulating film of another lower wiring layer (not shown) is formed by a conventional method to form a guard ring (16A, 16A).
B), etc., and then the passivation film (1
5) and a polyimide film (16) are sequentially formed (FIG. 3).

After that, a photoresist is applied and exposed.
The resist film (P) is developed and patterned so that an opening is formed in a region of the fuse portion where a repair window is formed.
R) is formed, and then anisotropic etching is performed.
By removing and forming a repair window (18), a fuse as shown in FIGS. 1 and 2 is formed. As described above, according to the semiconductor device of the present embodiment, the plasma TEOS film (14) serving as the interlayer insulating film of the two-layer wiring is
Since it is used as a surface protective film for covering the guard ring (16A, 16B) of the fuse portion, the repair window (1
8), even if the polyimide film (16) and the passivation film (15) are simultaneously etched as shown in FIGS. 3 and 4, the plasma TEOS film (1
Since 4) is formed, the guard rings (16A, 16B) are prevented from being exposed in this etching process.

Therefore, the guard rings (16A, 16B)
Since it is not necessary to spread the guard rings (16A, 16B) to the area outside the repair window (18) to prevent the exposure of the chip, it is possible to suppress the increase in the chip size caused by this layout. Will be possible. Moreover, since the plasma TEOS film (14) has a high transmittance, it is possible to sufficiently fuse the lower fuse wiring (19) by irradiating it with laser.

Although the plasma TEOS film (14) is used as the interlayer insulating film in the present embodiment, the present invention is not limited to this, and the insulating film has a film quality that functions as an interlayer insulating film and has good laser transmittance. As long as it is a film, almost the same effect can be obtained.

[0018]

As described above, according to the semiconductor device of the present invention, a plurality of fusing fuse wirings are formed on the semiconductor substrate in the region surrounded by the guard ring, and the fusing fuse wiring and the upper layer of the guard ring are formed. Since the interlayer insulating film of the multi-layer wiring is formed on the first insulating film and the second insulating film are sequentially formed on the interlayer insulating film, the first and second regions of the region including the region surrounded by the guard ring are formed. When forming an opening in the insulating film that is easy to blow a fuse, even if these openings are simultaneously etched to form the opening in the first and second insulating films, the interlayer insulating film serves as a surface protection film for the guard ring. It is possible to form the opening without exposing it by one etching process.

Therefore, since it is not necessary to spread the guard ring to the region outside the opening in order to prevent the guard ring from being exposed, it is possible to suppress the increase in the chip size caused by this arrangement. become.

[Brief description of the drawings]

FIG. 1 is a top view illustrating a structure of a semiconductor device according to an embodiment of the present invention.

FIG. 2 is a sectional view illustrating a structure of a semiconductor device according to an embodiment of the present invention.

FIG. 3 is a first cross-sectional view illustrating the method for manufacturing the semiconductor device according to the embodiment of the present invention.

FIG. 4 is a second sectional view illustrating the method for manufacturing the semiconductor device according to the embodiment of the present invention.

FIG. 5 is a top view illustrating a structure of a semiconductor device according to a conventional example.

FIG. 6 is a sectional view illustrating a structure of a semiconductor device according to a conventional example.

FIG. 7 is a first diagram illustrating a conventional problem.

FIG. 8 is a second diagram illustrating a conventional problem.

Claims (2)

[Claims] 1. A semiconductor device having a multilayer wiring structure in which a first wiring layer formed on a semiconductor substrate and a second wiring layer are formed on the first wiring layer with an interlayer insulating film interposed therebetween. A part of the first wiring layer constitutes a guard ring formed in an annular shape surrounding a predetermined region of the semiconductor substrate, and a plurality of guard rings are formed on the semiconductor substrate in a region surrounded by the guard ring. A blow fuse wire is formed, the interlayer insulating film is formed on the blow fuse wire and the guard ring, and a first insulating film and a second insulating film are sequentially formed on the interlayer insulating film. A semiconductor device comprising: a fuse formed by forming an opening in the first and second insulating films in a region including a region surrounded by a ring, and exposing the interlayer insulating film from the opening. 2. The semiconductor device according to claim 1, wherein the interlayer insulating film is a plasma TEOS film.