JPH0883843A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE: To provide a method for manufacturing a semiconductor device wherein the progression of etching of a layer which protects electrodes is prevented when a contact hole is formed by the self-alignment method and thereby an yield and the reliability of a semiconductor device are increased. CONSTITUTION: An oxide film 107 is formed for insulation of the entire surface. On the oxide film 107, an etching stopper film 108 which is constituted of a silicon nitride film is formed to protect the layers formed under the oxide film 107 from etching. Furthermore, a polycrystalline silicone film 90 is formed on the etching stopper film 108. The existence of the polycrystalline silicone film 90 prevents the etching stopper layer from being removed and interconnect layers from being exposed. Therefore, the shorts between the interconnect layers can be prevented, resulting in the increase in an yield and the reliability of a semiconductor device.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a semiconductor device in which a contact hole is formed by a self-alignment method.

[0002]

2. Description of the Related Art With the recent increase in the degree of integration of semiconductor devices, the pattern size has become finer and the margin for misalignment in photolithography has decreased. Therefore, as a method of forming a contact hole exposing a semiconductor substrate, a self-alignment method has been proposed in which an etching mask pattern larger than an actual contact hole size is formed and a contact hole is formed using a peripheral pattern.

A conventional method of forming a contact hole by the self-alignment method will be described below in order of steps with reference to FIGS. 36 to 41 which are partial cross-sectional views of a manufacturing process of a semiconductor device.

First, in a step shown in FIG. 36, a device isolation region 102 is formed on a semiconductor substrate 101, thereafter, an oxide film (not shown) to be gate oxide films 103a and 103b is deposited, and a gate electrode is overlaid thereon. A polycrystalline silicon layer (not shown) to be 104a and 104b is deposited, and an oxide film (not shown) to be protective films 105a and 105b is further stacked. Then, a resist pattern (not shown) is formed thereon, and etching is performed using the resist pattern as an etching mask to form gate oxide films 103a and 103b, gate electrodes 104a and 104b, and protective films 105a and 105b having a predetermined pattern.

Next, in a step shown in FIG. 37, an oxide film (not shown) is formed on the entire surface in order to protect the gate electrodes 104a and 104b, and then reactive ion etching (hereinafter referred to as RIE) which is anisotropic etching is performed. Called)
By the method, the oxide film is removed so that the sidewalls 106a and 106b remain on the side surfaces of the gate electrode 104a and the protective film 105a and the sidewalls 106c and 106d remain on the side surfaces of the gate electrode 104b and the protective film 105b.

Next, in a step shown in FIG. 38, an oxide film 107 for insulation is deposited on the entire surface, and an etching film composed of a nitride film is formed on the oxide film 107 to protect the layers below the oxide film 107 from etching. A stopper film 108 is deposited, and an interlayer film 109 of silicon oxide film is further deposited. The surface of the interlayer film 109 is not flat because of the unevenness due to the pattern formed therebelow. Therefore, the surface of the interlayer film 109 is flattened by the etch back by the RIE method or the reflow method by the heat treatment.

Next, in a step shown in FIG. 39, a photoresist is applied on the flattened interlayer film 109 and patterned to form a resist pattern 111. In the self-alignment method, this resist pattern 1
The dimension d ′ of the opening 11 is slightly larger than the dimension d of the contact hole to be formed. Further, in FIG. 39, the original position of the opening of the resist pattern 111 is shown by a broken line, the actual position of the opening due to misalignment is shown by a solid line, and the magnitude of the misalignment is shown by a distance X. At this time, the inclined portion 108S of the etching stopper film 108 is located below the side surface of the opening of the resist pattern 111.

Next, in the step shown in FIG. 40, etching is performed by the RIE method using the resist pattern 111 as an etching mask. In this case, since the purpose is to form a contact hole, overetching is performed so that the semiconductor substrate 101 is exposed. Here, the dimension d ′ of the opening of the resist pattern 111 is larger than the dimension d of the contact hole.
The inclined portion 108S of the etching stopper film 108 is exposed first.

The RIE method, which is reactive etching, has some selectivity due to the difference in the material of the portion to be etched. Here, the gate electrodes 104a and 1
Etching stopper film 108 for protecting 04b
The etching does not proceed so much, but the interlayer film 10
For 9, the etching will proceed. Therefore, even after the interlayer film 109 within the range of the dimension d ′ of the opening of the resist pattern 111 is completely removed, the inclined portion 108S and the flat portion F of the etching stopper film 108 remain.

Next, in the step shown in FIG. 41, when etching is further continued, the flat portion 108F of the etching stopper film 108 is removed, and a contact hole of approximately dimension d is completed. On the other hand, the slanted portion 108S of the etching stopper film 108 is not completely removed because the slanted portion 108S has a substantially large thickness in the etching direction (vertical direction) due to the slant, and a part thereof remains.

As described above, according to the self-alignment method, the inclined portion 1 of the etching stopper film 108 is formed.
Since 08S is not completely removed and a part of 08S remains, gate electrodes 104a and 104b are protected. Therefore, the contact hole having the dimension d can be formed by using the resist pattern 111 having the opening having the dimension d ′ larger than the dimension d of the contact hole. Also, FIG.
As shown in FIG. 9, even when the resist pattern 111 is misaligned, a contact hole having a predetermined dimension d can be obtained if the size of the misalignment is within the allowable range.

[0012]

In the conventional method of manufacturing a semiconductor device, in order to form the contact hole having the dimension d, the interlayer film 109 is removed and only the flat portion 108F of the etching stopper film 108 is removed. The sloped portion 108S of the etching stopper film 108 is preferably not completely removed in order to protect the gate electrodes 104a and 104b.

In dry etching by the RIE method, the etching rate in the inclined portion 108S of the etching stopper film 108 is higher than the etching rate in the flat portion 108F, so that the etching stopper film 10 is formed.
8 is thin, the inclined portion 108S of the etching stopper film 108 is also removed due to the misalignment of the resist pattern 111, the positional relationship between the gate electrodes 104a and 104b, etc., and the etching is performed on the sidewall 106c or 106b as shown in FIG. May reach.

In this state, there is a possibility that the gate electrodes 104a and 104b and the wiring formed in the contact hole in a later step may be short-circuited due to defective withstand voltage and may not operate normally.

In order to prevent such a problem, the etching stopper film 108 is thickened, the protective films 105a and 105b, and the sidewalls 106a-1.
It is conceivable to increase the film thickness of 06d. However, in this case, although a short circuit between the gate electrodes 104a and 104b and the wiring to be formed next can be prevented, a step difference on the surface becomes remarkably large, which causes a process problem for a later process.

As described above, when the contact hole is formed by dry etching by the RIE method, the inclined portion 108S of the etching stopper film 108 is formed.
Since the etching rate at the gate electrode 104a is higher than the etching rate at the flat portion 108F,
And 104b and a wiring formed in the next step may be short-circuited due to defective withstand voltage and may not operate normally, and there is a problem that the yield and reliability of the semiconductor device are reduced.

The present invention has been made to solve the above-mentioned problems, and prevents the etching of a layer for protecting an electrode from proceeding when a contact hole is formed by a self-alignment method, so that a semiconductor can be formed. An object of the present invention is to provide a method for manufacturing a semiconductor device with improved device yield and reliability.

[0018]

According to a first aspect of the present invention, there is provided a method of manufacturing a semiconductor device, comprising: (a) a step of disposing wiring layers on a semiconductor substrate with a space therebetween; and (b) the wiring. Covering the wiring layer with an etching stop layer for preventing the layer from being etched, and (c) forming an interlayer film between the etching stop layer and a layer formed further above. And (d) a step of selectively removing the interlayer film and the etching stopper layer in order to form a contact hole reaching the semiconductor substrate between the wiring layers,
(c) includes (e) a step of forming a non-oxidized layer having an etching selection ratio of 5 or more with respect to the etching stop layer on the etching stop layer, and (f) after the step (d) The method further comprises the step of oxidizing the non-oxidized layer to form the interlayer film.

A method of manufacturing a semiconductor device according to a second aspect of the present invention is the method of manufacturing a semiconductor device according to the first aspect, wherein the step (b) is a step of forming the etching stopper layer with silicon nitride. And the step (e) includes a step of forming the non-oxidized layer with polycrystalline silicon.

According to a third aspect of the present invention, there is provided a method of manufacturing a semiconductor device, comprising: (a) a step of disposing wiring layers on a semiconductor substrate with a space therebetween; and (b) etching of the wiring layers does not occur. A step of covering the wiring layer with a first etching stop layer for performing the above, and (c) a step of forming an interlayer film between the etching stop layer and a layer formed thereabove.
(d) a step of selectively removing the interlayer film and the first etching stop layer in order to form a contact hole reaching the semiconductor substrate between the wiring layers, the step (d)
(E) a step of selectively removing the resist layer formed on the interlayer film via a second etching stop layer to form a first opening reaching the second etching stop layer;
(f) The second etching stop layer is continuous with the first opening, and the cross-sectional shape is such that the opening size on the first opening side is equal to the first opening, and the interlayer film is formed. The step of forming a tapered second opening portion whose opening size gradually decreases as it goes to.

According to a fourth aspect of the present invention, there is provided a method of manufacturing a semiconductor device, comprising: (a) a step of disposing wiring layers on a semiconductor substrate at intervals, and (b) etching of the wiring layers does not occur. A step of covering the wiring layer with a first etching stop layer for performing the above, and (c) a step of forming an interlayer film between the etching stop layer and a layer formed thereabove.
(d) a step of selectively removing the interlayer film and the first etching stop layer in order to form a contact hole reaching the semiconductor substrate between the wiring layers, the step (d)
(E) a step of selectively removing the resist layer formed on the interlayer film via a second etching stop layer to form a first opening reaching the second etching stop layer;
(f) After forming a second opening continuous with the first opening in the second etching stop layer, the opening size of the first opening is widened to form the second etching stop layer. The method for manufacturing a semiconductor device according to claim 5, further comprising: (a) over the semiconductor substrate. Arranging a first wiring layer with a space between them, and (b) the first wiring layer.
For preventing the wiring layer from being etched
Covering the first wiring layer with an etching stop layer of
(c) a step of forming a first interlayer film between the first etching stop layer and a layer formed thereabove, (d)
A step of disposing a second wiring layer on the first interlayer film so as to intersect with the first wiring layer with the first interlayer film sandwiched therebetween, and a second wiring layer with a space therebetween; ) A step of covering the second wiring layer with a second etching stop layer for preventing the second wiring layer from being etched, and (f) the second etching stop layer, and further on top. A step of forming a second interlayer film with the layer to be formed, and (g) the second interlayer film, the second etching stop layer, the first interlayer film, the first etching stop Selectively removing layers in order to form a contact hole reaching the semiconductor substrate between the first wiring layers, the step (g) comprising:
(h) a step of selectively removing the resist layer formed on the second interlayer film via a third etching stop layer to form a first opening reaching the third etching stop layer; (I) The third etching stop layer is continuous with the first opening and has a cross-sectional shape whose opening dimension on the first opening side is equal to that of the first opening. Forming a tapered second opening whose opening size gradually decreases toward the second interlayer film.

According to a sixth aspect of the present invention, there is provided a method of manufacturing a semiconductor device, comprising: (a) a step of disposing a first wiring layer on a semiconductor substrate with a space therebetween, and (b) the first wiring. A step of covering the first wiring layer with a first etching stop layer for preventing the layer from being etched, and (c) the first etching stop layer and the layer formed on the upper side. A step of forming a first interlayer film therebetween, and (d) an interval is provided on the first interlayer film so as to intersect with the first wiring layer with the first interlayer film interposed therebetween. A step of opening a second wiring layer and (e) a step of covering the second wiring layer with a second etching stopper layer for preventing the second wiring layer from being etched. , (F) a step of forming a second interlayer film between the second etching stop layer and a layer further formed thereon, and (g) the step of forming the second interlayer film. Interlayer film, the second
Selectively removing the etching stop layer, the first interlayer film, and the first etching stop layer to form a contact hole reaching the semiconductor substrate between the first wiring layers. The step (g) selectively removes the resist layer formed on the second interlayer film via the third etching stop layer in the step (g) to reach the third etching stop layer through the first opening. A step of forming a portion, and (i) after forming a second opening continuous with the first opening in the third etching stop layer, widening the opening size of the first opening. The method further includes the step of exposing the third etching stopper layer and forming an eaves portion that becomes an eaves portion with respect to the layer formed below.

[0023]

According to the method of manufacturing a semiconductor device according to claim 1 of the present invention, the step (c) includes the step (e) on the etching stop layer,
Since it includes a step of forming a non-oxidized layer having an etching selection ratio of 5 or more with respect to the etching stop layer, and (f) after the step (d), the step of oxidizing the non-oxidized layer to form an interlayer film is provided. ,
Since the non-oxidized layer is mainly etched, the etching stop layer is removed to prevent the wiring layer from being exposed,
A short circuit between wiring layers is prevented.

According to the method of manufacturing a semiconductor device of the second aspect of the present invention, the step (b) is a step of forming the etching stop layer with silicon nitride, and the step (e) is a step of forming the non-oxidized layer. Since it includes the step of forming with polycrystalline silicon,
A non-oxidized layer having an etching selection ratio of 5 or more with respect to the etching stop layer is formed.

According to the method of manufacturing a semiconductor device according to the third aspect of the present invention, the step (d) selectively removes the resist layer formed on the (e) interlayer film via the second etching stop layer. To form a first opening reaching the second etching stop layer, and (f) in the second etching stop layer,
A second tapered portion which is continuous with the first opening and has a cross-sectional shape whose opening dimension on the first opening side is equal to that of the first opening and which gradually decreases toward the interlayer film. Since the step of forming the opening is included, when the interlayer film is etched through the first and second openings, the layer formed under the taper is protected from etching,
The first etching stop layer located under the taper of the second opening is removed together to prevent the wiring layer from being exposed and prevent the wiring layers from being short-circuited.

According to the method for manufacturing a semiconductor device according to the fourth aspect of the present invention, in the step (d), the resist layer formed on the (e) interlayer film via the second etching stop layer is selectively formed. To form a first opening reaching the second etching stop layer, and (f) in the second etching stop layer,
After forming a continuous second opening in the first opening, the opening size of the first opening is expanded to expose the second etching stop layer, and the eaves are formed on the layer formed below. Since the step of forming such an eaves portion is included, when the interlayer film is etched through the first and second openings, the layer formed below the eaves portion of the second opening is formed. The first opening, which is protected from etching and is located under the eaves of the second opening
The etching stopper layer is removed together to prevent the wiring layer from being exposed, thereby preventing a short circuit between the wiring layers.

According to the method for manufacturing a semiconductor device according to the fifth aspect of the present invention, the step (g) includes: (h) a resist layer formed on the second interlayer film via a third etching stop layer. Are selectively removed to reach the third etch stop layer.
And (i) the third etching stop layer is continuous with the first opening and has a cross-sectional shape whose opening dimension on the side of the first opening is equal to that of the opening. When the second interlayer film is etched through the first and second openings, the step of forming the tapered second opening whose opening size gradually decreases toward the film is included. In addition, the layer formed under the taper is protected from etching, and the second etching stop layer located under the taper in the second opening is also removed to prevent the second wiring layer from being exposed. And further, when the first interlayer film is etched, it is prevented that the first etching stop layer located under the taper of the second opening is removed together and the first wiring layer is exposed. Prevents short circuit between the first and second wiring layers It is.

According to the method of manufacturing a semiconductor device according to claim 6 of the present invention, the step (g) comprises: (h) a resist layer formed on the second interlayer film via a third etching stop layer. Are selectively removed to reach the third etch stop layer.
And (i) forming a second opening continuous with the first opening in the third etching stop layer, and then expanding the opening size of the first opening to form a second opening. Since the step of exposing the etching stop layer of No. 3 and forming an eaves portion to be an eaves to the layer formed thereunder is included, the second interlayer layer is formed through the first and second opening portions. When the film is etched, the layer formed under the eaves of the second opening is protected from etching, and the second etching stop layer located under the eaves of the second opening is removed together. Then, the wiring layer is prevented from being exposed, and when the first interlayer film is further etched, the first etching stopper layer located under the eaves portion of the second opening is also removed to remove the first interlayer insulating film. Of the wiring layer is prevented from being exposed, and a short circuit between the wiring layers is prevented.

[0029]

【Example】

<First Embodiment> A semiconductor device manufacturing process by a self-alignment method, which is a first embodiment of a semiconductor device manufacturing method according to the present invention, is a partial cross-sectional view of the process.
~ It demonstrates in order using FIG.

In FIG. 1, an element isolation region 102 is formed on a semiconductor substrate 101, and gate oxide films 103a and 103a are formed on the semiconductor substrate 101 and the element isolation region 102.
03b, the gate electrodes 104a and 104b are formed, and the protective films 105a and 105b are further formed thereon.
Are formed. Gate electrodes 104a and 104b
For protecting the gate electrode 104a and the protective film 1
05a includes oxide film sidewalls 106a and 106b on the side surface of the gate electrode 104b and a protective film 105B.
On the side surface of the oxide film side walls 106c and 10
6d is formed. Further, an oxide film 107 for insulation is formed on the entire surface, and an etching stopper film 108 made of a silicon nitride film is formed on the oxide film 107 to protect layers below the oxide film 107 from etching. Further, a polycrystalline silicon film 90 is formed on the etching stopper film 108.

The process for obtaining the above-described structure is shown in FIG.
6 to 38, the manufacturing process of the semiconductor device by the conventional self-alignment method is almost the same as that of FIG.
6 to FIG. 38 are the same as those denoted by the same reference numerals, and the description of the overlapping steps will be omitted.
Here, the etching stopper film 1 is different from the conventional example.
That is, instead of forming the interlayer film 109 on the upper part of 08, the polycrystalline silicon film 90 is formed.

Next, in a step shown in FIG. 2, a resist pattern 1 is formed on the polycrystalline silicon film 90 by patterning.
11 is formed, and the polycrystalline silicon 90 and the etching stopper film 108 which is a silicon nitride film are dry-etched by the RIE method using plasma of Cl ₂ / O ₂ gas or the like with the resist pattern 111 as an etching mask. The etching selection ratio between the polycrystalline silicon and the silicon nitride film is high, and the value is 5 or more. Since the silicon nitride film is hardly etched, the etching stopper film 108 is removed even if the polycrystalline silicon film 90 is completely removed. Has a sufficient thickness, and the inclined portion 108S and the flat portion 108F remain.

Next, in the step shown in FIG. 3, after removing the resist pattern 111, the polycrystalline silicon film 90 is oxidized by a method such as thermal oxidation to form a silicon oxide interlayer film 90.
Denature to 0. At this time, the etching stopper film 108, which is a silicon nitride film, also functions as an anti-oxidation film that prevents oxidation of the layers below the etching stopper film 108 due to thermal oxidation or the like.

Next, in the step shown in FIG. 4, the flat portion 108F of the etching stopper film 108 is removed by highly selective anisotropic etching using cl ₂ gas to remove the oxide film 1
07 is exposed. At this time, the etching stopper film 1
Although the 08 slanted portion 108S is also etched, the slanted portion 108S substantially increases the thickness in the etching direction (vertical direction), so that a sufficient thickness remains.

Next, in the step shown in FIG. 5, the oxide film 10 is formed.
7 is etched by using fluorocarbon-based plasma such as C ₄ F ₈ to complete the contact hole having the opening dimension d.

As described above, by forming the interlayer film of polycrystalline silicon having a high etching selection ratio with respect to the silicon nitride film which is the etching stopper film 108,
Since the silicon nitride film is hardly etched but the polycrystalline silicon is etched, the polycrystalline silicon film 90
Even if the etching is completely removed, the etching stopper film 108
Can leave a sufficient thickness. Therefore, the breakdown voltage between the gate electrodes 104a and 104b and the wiring formed in a later step can be maintained, and a defect due to a wiring short circuit can be prevented.

<Second Embodiment> A semiconductor device manufacturing process by a self-alignment method, which is a second embodiment of the semiconductor device manufacturing method according to the present invention, will be described below with reference to FIGS. It demonstrates in order using FIG.

In FIG. 6, device isolation region 102 is formed on semiconductor substrate 101, and gate oxide films 103a and 103a are formed on semiconductor substrate 101 and device isolation region 102.
03b, the gate electrodes 104a and 104b are formed, and the protective films 105a and 105b are further formed thereon.
Are formed. Gate electrodes 104a and 104b
For protecting the gate electrode 104a and the protective film 1
Oxide film sidewalls 106a and 106b are provided on the side surface of the gate electrode 104b and the protective film 105b.
On the side surface of the oxide film side walls 106c and 10
6d is formed. Further, an oxide film 107 for insulation is formed on the entire surface, and a first etching stopper film 208 made of a silicon nitride film is formed on the oxide film 107 to protect layers below the oxide film 107 from etching. ing. Further, the first etching stopper film 2
An interlayer film 109 is formed on the upper part of 08.

The process for obtaining the above-described structure is shown in FIG.
6 to 38, the manufacturing process of the semiconductor device by the conventional self-alignment method is almost the same as that of FIG.
6 to 38 are designated by the same reference numerals,
The description of the overlapping steps is omitted. Here, the difference from the conventional example is that the name of the etching stopper film 108 is the first etching stopper film 208.

In the step shown in FIG. 7, a second etching stopper film 210 made of a nitride film is deposited on the interlayer film 109.

Next, in a step shown in FIG. 8, a photoresist is applied on the second etching stopper film 210 and a resist pattern 111 is formed by patterning. In the self-alignment method, the dimension d ′ of the opening of the resist pattern 111 is formed slightly larger than the dimension d of the contact hole to be formed. Further, in FIG. 8, the original position of the opening of the resist pattern 111 is shown by a broken line, the actual position of the opening due to misalignment is shown by a solid line, and the magnitude of the misalignment is shown by X.

Next, in the step shown in FIG. 9, using the resist pattern 111 as an etching mask, a gas such as CF ₄ is used for the second etching stopper film 210, and the opening size gradually decreases toward the interlayer film 109. Dry etching is performed so as to form an opening having such a taper 210T.

Next, in the step shown in FIG. 10, the etching ratio of the oxide film to the nitride film (selection ratio) is increased by dry etching using a gas such as C ₄ F ₈ (>).
Under the etching condition 5), the interlayer film 109 is etched to expose the first etching stopper film 208.

In the dry etching by the RIE method, the etching rate at the inclined portion 208S of the first etching stopper film 208 is higher than the etching rate at the flat portion 208F, so that the selection ratio between the inclined portion 208S and the interlayer film 109 is lowered. However, since the taper 210T of the second etching stopper film 210 is formed so as to cover the inclined portion 208S, the inclined portion 208S is protected from etching. Therefore, the inclined portion 2
At this point, 08S is etched and disappears, the sidewalls 106b and 106c are etched, and the gate electrodes 104a and 104b are prevented from being exposed.

Next, in the step shown in FIG. 11, the etching ratio (selection ratio) of the oxide film to the nitride film is reduced by dry etching using a gas such as CF ₄ (...
Under the etching condition 1), the first etching stopper film 208 and the protective film 107 are etched to expose the semiconductor substrate 101.

As described above, in the case of forming a contact hole by using the self-alignment method,
The second etching stopper film 210 is tapered 210T
By forming the gate electrode 104 when the interlayer film 209 is removed by dry etching.
It is possible to prevent the first etching stopper film 208, which is a protective film for a and 104b, from being completely removed, and to maintain the breakdown voltage between the gate electrodes 104a and 104b and the wiring formed in a later step, It is possible to prevent problems due to wiring short circuits.

Further, the second etching stopper film 21
0, the interlayer film 209, the first etching stopper film 20.
8. Since the RIE method is used for etching the protective film 107, these etchings can be continuously performed, and the time spent for contact hole formation can be shortened.

<Third Embodiment> A semiconductor device manufacturing process by a self-alignment method, which is a third embodiment of the semiconductor device manufacturing method according to the present invention, will now be described with reference to FIGS. It demonstrates in order using FIG.

In FIG. 12, a second etching stopper film 210 composed of a nitride film is formed on the interlayer film 109, and patterning is performed on the second etching stopper film 210, whereby the dimension of the opening is d '. Resist pattern 111 is formed. In the self-alignment method, the dimension d ′ of the opening of the resist pattern 111 is formed slightly larger than the dimension d of the contact hole to be formed.

The steps for obtaining the structure described above are almost the same as those of the second embodiment of the method for manufacturing a semiconductor device according to the present invention described with reference to FIGS. The same components as those of the above are denoted by the same reference numerals, and the description of the overlapping steps will be omitted.

Next, in the step shown in FIG. 13, the second etching stopper film 210 is removed by dry etching using a gas such as CF ₄ using the resist pattern 111 as an etching mask to expose the interlayer film 109.

Next, in the step shown in FIG. 14, the opening size of the resist pattern 111 is increased by pseudo anisotropic etching using O ₂ gas without changing the opening size of the second etching stopper film 210. Exposing the second etching stopper film 210 like an eaves,
Form 10E.

Next, in the step shown in FIG. 15, the ratio of etching of the oxide film to the nitride film (selection ratio) is increased by dry etching using a gas such as C ₄ F ₈ (>).
5) Under the etching conditions as described above, the interlayer film 109 is etched to expose the first etching stopper film 208.

In dry etching by the RIE method, the etching rate at the inclined portion 208S of the first etching stopper film 208 is higher than the etching rate at the flat portion 208F, so that the selection ratio between the inclined portion 208S and the interlayer film 109 is lowered. However, since the eaves portion 210E of the second etching stopper film 210 is formed so as to cover the inclined portion 208S, the inclined portion 208S is protected from etching. Therefore, the inclined portion 20
8S is prevented from being etched away at this point. Then, by dry etching using a gas such as CF ₄ , under the etching conditions such that the etching ratio (selection ratio) of the oxide film with respect to the nitride film is small (˜1), the first etching stopper film 208 and the protection film are protected. The film 107 is etched to expose the semiconductor substrate 101.

As described above, in the case of forming a contact hole by using the self-alignment method,
By increasing the opening size of the resist pattern 111, the second etching stopper film 210 is made to cover the eaves portion 210.
By forming so as to have E, when the interlayer film 209 is removed by dry etching, the gate electrode 104 is removed.
It is possible to prevent the first etching stopper film 208, which is a protective film for a and 104b, from being completely removed, and to maintain the breakdown voltage between the gate electrodes 104a and 104b and the wiring formed in a later step, It is possible to prevent problems due to wiring short circuits.

Further, the second etching stopper film 21
0, the interlayer film 209, the first etching stopper film 20.
8. Since the RIE method is used for etching the protective film 107, these etchings can be continuously performed, and the time spent for contact hole formation can be shortened.

<Fourth Embodiment> In the first and second embodiments described above, the self-alignment method for a single-layer wiring has been described, but a contact hole can be formed for a multi-layer wiring by the self-alignment method.

FIG. 16 is a partial plan view showing an example of a wiring layout of a semiconductor device having a multilayer wiring structure. FIG.
In, the first layer wirings 501a and 501b in the lower layer are arranged in parallel with a certain space in the horizontal direction with respect to the drawing, and the second layer wirings 502a and 502b in the upper layer are arranged in the vertical direction with respect to the drawing. They are arranged in parallel at intervals. First layer wirings 501a and 501b and second layer wiring 5
Near the center of the part where 02a and 502b intersect,
Originally, the position where the contact hole is provided is the broken line region 5
03, the contact hole 503A actually provided is shown at a position displaced from the broken line region 503 by a distance X on the left side in the horizontal direction and a distance Y on the upper side in the vertical direction with respect to the figure due to misalignment of the resist pattern. Has been done.

Fourth Method of Manufacturing Semiconductor Device According to Present Invention
As an example of the above, in the semiconductor device having the multilayer wiring structure as described above, a manufacturing process in the case of providing a contact hole by a self-alignment method will be sequentially described with reference to FIGS. 17 to 27 which are partial cross-sectional views of the process. .

FIG. 17A shows a sectional view taken along the line AA 'shown in FIG. 16, and FIG. 17B shows a sectional view taken along the line BB'. Hereinafter, a cross-sectional view taken along the line AA ′ and a cross-sectional view taken along the line BB ′ are shown as (a) and (b) in FIGS. 18 to 26, respectively. In addition,
The contact hole 502 shown in FIG. 16 is formed in the final step and is not shown in FIG. In addition, in FIGS. 17 to 26, first layer wirings 501a and 501b and second layer wirings 502a and 502b shown in FIG. 16 are gate electrodes 104a and 104, respectively.
4b and metal wirings 201a and 201b.

In FIG. 17A, the semiconductor substrate 101
A device isolation region 102 is formed on the semiconductor substrate 101.
Gate oxide film 103a on the upper surface and the device isolation region 102
And 103b through gate electrodes 104a and 104
4b is formed, and protective films 105a and 105b are further formed thereon. In order to protect the gate electrodes 104a and 104b, sidewalls 106 of an oxide film are formed on the side surfaces of the gate electrode 104a and the protective film 105a.
a and 106b, and sidewalls 106c and 106d of oxide film are formed on the side surfaces of the gate electrode 104b and the protective film 105b. An oxide film 107 for insulation is formed on the entire surface, and the oxide film 1 is formed on the oxide film 107.
The first etching stopper film 208 formed of a silicon nitride film for protecting the layers of 07 or less from etching
Are formed. Further, a first interlayer film 209 is formed on the first etching stopper film 208.

In FIG. 17B, the semiconductor substrate 101
An oxide film 107 for insulation is formed on the entire surface of, and a first etching stopper film 208 made of a silicon nitride film is formed on the oxide film 107 for protection of layers below the oxide film 107 from etching. There is. Further, a first interlayer film 209 is formed on the first etching stopper film 208.

The process for obtaining the structure described above is shown in FIG.
6 to 38, the manufacturing process of the semiconductor device by the conventional self-alignment method is almost the same as that of FIG.
6 to FIG. 38 are the same as those denoted by the same reference numerals, and the description of the overlapping steps will be omitted.
Here, the etching stopper film 1 is different from the conventional example.
The name 08 is the first etching stopper film 208 and the interlayer film 109 is the first interlayer film 209.

In the step shown in FIGS. 18A and 18B, a metal film 201 made of polycrystalline silicon and serving as metal wirings 201a and 201b is deposited on the entire surface of the first interlayer film 209, and further, An oxide film 202 to be protective films 202a and 202b is deposited thereon.

Next, in a step shown in FIGS. 19A and 19B, a resist pattern (not shown) is formed on the oxide film 202 and etching is performed using the resist pattern as an etching mask to form a second layer wiring. Predetermined pattern of metal wirings 201a and 202a and protective film 201
b and 202b are formed.

Next, in the step shown in FIGS. 20A and 20B, an oxide film (not shown) is formed on the entire surface to protect the metal wirings 201a and 201b, and then a metal electrode is formed by RIE. The oxide film is removed so that the sidewalls 203a and 203b are left on the side surfaces of the 201a and the protective film 202a and the sidewalls 203c and 203d are left on the side surfaces of the metal electrode 201b and the protective film 202b. At this time, the first interlayer film 209 is etched by overetching.

Next, in the step shown in FIGS. 21A and 21B, the first interlayer film 209 and the protective films 202a and 20a are formed.
2b, a second etching stopper film 210 composed of a silicon nitride film is deposited to protect layers of the sidewalls 203a to 203d and below from etching.
The second interlayer film 2 on the etching stopper film 210 of
05 is deposited.

The surface of the second interlayer film 205 is not flat because of the unevenness due to the pattern formed therebelow. Therefore, the surface of the second interlayer film 205 is flattened by etching back by RIE or reflowing by heat treatment, and then a silicon nitride film is used to protect the layers below the second interlayer film 205 from etching. The constituted third etching stopper film 206 is deposited.

Next, in a step shown in FIGS. 22A and 22B, a photoresist is applied on the third etching stopper film 206 and patterned to form a resist pattern 211. In the self-alignment method, the dimension d ′ of the opening of the resist pattern 211
Is slightly larger than the dimension d of the contact hole to be formed.

Further, as shown in FIG. 16, the contact hole 503A actually provided has a distance X from the broken line region 503 where the contact hole is originally provided to the left side in the horizontal direction with respect to the figure due to misalignment of the resist pattern. , The position of the actual opening is indicated by a solid line in FIG. 22A, and the magnitude of the misalignment is indicated by the distance Y.
22 and is indicated by a distance X in FIG.

Next, in the step shown in FIGS. 23A and 23B, using the resist pattern 211 as an etching mask, a gas such as CF ₄ is used for the third etching stopper film 206, and the second interlayer film 205 is formed. Dry etching is performed so as to form an opening having a taper 206T whose opening size gradually decreases as it goes.

Next, in the steps shown in FIGS. 24A and 24B, the etching ratio of the oxide film to the nitride film (selection ratio) is increased by dry etching using a gas such as C ₄ F ₈ (>). 5) The second interlayer film 205 is etched under such etching conditions to expose the second etching stopper film 210.

In dry etching by the RIE method, since the etching rate of the inclined portion 210S of the second etching stopper film 210 is higher than the etching rate of the flat portion 210F, the inclined portion 210S and the second portion
Although the selection ratio of the third etching stopper film 206 to the interlayer film 205 decreases, the taper 206T of the third etching stopper film 206 causes the inclined portion 21
Since it is formed so as to cover 0S, it is protected from etching. Therefore, the sloped portion 210S is prevented from being etched and disappeared at this point.

Next, in the steps shown in FIGS. 25A and 25B, the etching rate of the oxide film with respect to the nitride film (selection ratio) is small (to 1) by dry etching using a gas such as CF _4. Under such etching conditions, the flat portion 210F of the second etching stopper film 210 is removed to expose the first interlayer film 209.

Next, in the steps shown in FIGS. 26A and 26B, the etching ratio of the oxide film with respect to the nitride film (selection ratio) is increased by dry etching using a gas such as C ₄ F ₈ (>). 5) The first interlayer film 209 is etched under such etching conditions to expose the first etching stopper film 208.

In the dry etching by the RIE method, the sloped portion 210S of the second etching stopper film 210 and the sloped portion 20 of the first etching stopper film 208 are formed.
Since the etching rate in 8S is higher than the etching rates in the flat portions 210F and 208F,
Although the selection ratio between the inclined portion 208S and the first interlayer film 209 and the selection ratio between the inclined portion 208S and the first interlayer film 209 are reduced, the second interlayer film 205 and the second etching stopper film 208 are present. Therefore, it is protected from etching. Therefore, the inclined portions 210S and 208
It is prevented that S is etched at this point and disappears.

Next, in the steps shown in FIGS. 27 (a) and 27 (b), the etching ratio (selection ratio) of the oxide film to the nitride film is small (to 1) by dry etching using a gas such as CF _4. Under such etching conditions, the first etching stopper film 208 and the oxide film 107 are formed.
Are removed to expose the semiconductor substrate 101.

As described above, in the case of forming a contact hole by using the self-alignment method,
Taper 206T on the third etching stopper film 206
The second interlayer film 2 is formed by etching so that
05, the second etching stopper film 210, the first interlayer film 209, and the first etching stopper film 208 are removed, the protective films of the metal wirings 201a and 201b and the protective films 105a of the gate electrodes 104a and 104b,
Since the contact hole can be formed without removing 105b, the metal wirings 201a and 20
1b and the gate electrodes 104a and 104b are prevented from being short-circuited, and the manufacturing yield and reliability of the semiconductor device are improved.

Further, the third etching stopper film 20
6 taper 206T, second interlayer film 205, second
Etching stopper film 210 and first interlayer film 20 of
9, first etching stopper film 208, oxide film 10
Since any of the steps of etching 7 is performed by RIE, these steps can be continuously performed.

<Fifth Embodiment> As a fourth embodiment of the method of manufacturing a semiconductor device according to the present invention, a manufacturing process for forming a contact hole by a self-alignment method in a semiconductor device having a multilayer wiring structure will be described. It demonstrates in order using FIGS. 28-35 which are partial sectional views. The wiring layout of the semiconductor device having the multilayer wiring structure is similar to that of FIG. 16 which is a partial plan view, and is a sectional view taken along the line AA ′ shown in FIG. 16 and taken along the line BB ′. A cross sectional view,
Hereinafter, FIGS. 28 to 35 show (a) and (b), respectively. Further, the steps leading to the configuration shown in FIG. 28 are the same as those of the fourth embodiment of the semiconductor device manufacturing method according to the present invention described with reference to FIGS. 17 to 21, and the same reference numerals are given to the same configurations. Will be attached and redundant description will be omitted.

In the steps shown in FIGS. 29A and 29B, a photoresist is applied on the third etching stopper film 206, and a resist pattern 211 is formed by patterning. In the self-alignment method, the dimension d ′ of the opening of the resist pattern 211
Is slightly larger than the dimension d of the contact hole to be formed.

Further, as shown in FIG. 16, the contact hole 503A actually provided has a distance X from the broken line region 503 where the contact hole is originally provided to the left side in the horizontal direction with respect to the figure due to misalignment of the resist pattern. , The position of the actual opening is indicated by a solid line in FIG. 29A, and the magnitude of the alignment deviation is indicated by the distance Y.
, And the distance X is shown in FIG.

Next, in the steps shown in FIGS. 30A and 30B, the third etching stopper film 206 is removed by dry etching using a gas such as CF ₄ with the resist pattern 211 as an etching mask. The second interlayer film 205 is exposed.

Next, in the steps shown in FIGS. 31A and 31B, by pseudo anisotropic etching using O ₂ gas,
The opening size of the third etching stopper film 206 is not changed, and the opening size of the resist pattern 211 is increased to expose the third etching stopper film 206 like an eaves to form an eave portion 206E.

Next, in the steps shown in FIGS. 32 (a) and 32 (b), the etching ratio of the oxide film to the nitride film (selection ratio) is increased by dry etching using a gas such as C ₄ F ₈ (>). 5) Under such etching conditions, the second interlayer film 205 is etched to expose the second etching stopper film 302.

In the dry etching by the RIE method, the etching rate at the inclined portion 210S of the second etching stopper film 210 is higher than the etching rate at the flat portion 210F.
Although the selectivity with respect to the interlayer film 205 of the third etching stopper film 206 is decreased, the eaves portion 206E of the third etching stopper film 206 is inclined to the inclined portion 210.
Since it is formed so as to cover S, the second interlayer film 205 immediately below the eaves portion 206E remains on the inclined portion 210S without being etched, and the inclined portion 210S is protected from etching. Therefore, the sloped portion 210S is prevented from being etched and disappeared at this point.

Next, in the steps shown in FIGS. 33A and 33B, the etching conditions such that the selection ratio of the oxide film to the nitride film is reduced (to 1) by dry etching using a gas such as CF _4. Then, the flat portion 210F of the second etching stopper film 210 is removed, and the first interlayer film 2 is removed.
09 is exposed.

Next, in the steps shown in FIGS. 34A and 34B, dry etching using a gas such as C ₄ F ₈ increases the selectivity of the oxide film to the nitride film (> 5). The first interlayer film 209 is etched under the etching conditions to expose the first etching stopper film 208. At this time, the eave portion 206E of the third etching stopper film 206 and the second interlayer film 2 immediately below it.
05 is also removed, and the second etching stopper film 210
Will be exposed.

In dry etching by the RIE method, the etching rate at the inclined portion 208S of the first etching stopper film 208 is higher than the etching rate at the flat portion 208F.
However, the second etching stopper film 210 is exposed like an eaves to form an eaves portion 210E and the eaves portion 210E covers the inclined portion 208S in the previous step. Since the first interlayer film 209 immediately below the eaves portion 210E is not etched to the inclined portion 208S, the inclined portion 208S is protected from etching. Therefore, the inclined portion 2
It is prevented that 08S is etched and disappears at this point.

Next, in the steps shown in FIGS. 35 (a) and 35 (b), the etching conditions such that the selectivity of the oxide film with respect to the nitride film is reduced (to 1) by dry etching using a gas such as CF _4. Then, the first etching stopper film 208 and the oxide film 107 are etched to expose the semiconductor substrate 101. At this time, the eaves portion 210E of the second etching stopper film 210 and the first interlayer film 209 immediately thereunder are also removed.

As described above, when the contact hole is formed by the self-alignment method,
Since the third etching stopper film 206 is etched to form the eaves portion 206E, the second interlayer film 20 is removed.
5, when removing the second etching stopper film 210, the first interlayer film 209, and the first etching stopper film 208, the protective films of the metal wirings 201a and 201b and the protective films 105a and 1b of the gate electrodes 104a and 104b.
Since the contact hole can be formed without removing 05b, the metal wirings 201a and 201a
b and the gate electrodes 104a and 104b are prevented from being short-circuited, and the manufacturing yield and reliability of the semiconductor device are improved.

Further, the third etching stopper film 20
6, the eaves 206E, the second interlayer film 205, the second etching stopper film 210, the first interlayer film 209,
Since both the steps of etching the first etching stopper film 208 and the oxide film 107 are performed by RIE, these steps can be continuously performed.

[0093]

According to the method of manufacturing a semiconductor device according to the first aspect of the present invention, the etching stopper layer is removed to prevent the wiring layer from being exposed and the wiring layer from being short-circuited. Therefore, there is an effect of improving the manufacturing yield and reliability of the semiconductor device.

According to the method of manufacturing a semiconductor device according to the second aspect of the present invention, the non-oxidized layer having an etching selection ratio of 5 or more with respect to the etching stop layer is formed by using polycrystalline silicon. It is possible to obtain a semiconductor device in which the etching stopper layer is removed and the wiring layer is prevented from being exposed.

According to the semiconductor device manufacturing method of the third aspect of the present invention, when the interlayer film is etched through the first and second openings, the layer formed under the taper is etched. The first etching stop layer located under the taper of the second opening is removed together to prevent the wiring layer from being exposed and prevent the wiring layer from being short-circuited. This has the effect of improving the manufacturing yield and reliability of the semiconductor device having the layer wiring structure.

According to the method for manufacturing a semiconductor device according to the fourth aspect of the present invention, when the interlayer film is etched through the first and second openings, the lower part of the eaves of the second opening is formed. The layer formed on the substrate is protected from etching, the first etching stop layer located under the eaves of the second opening is removed together to prevent the wiring layer from being exposed, and the wiring layer is short-circuited. This is effective in improving the manufacturing yield and reliability of the semiconductor device having a single-layer wiring structure.

According to the semiconductor device manufacturing method of the fifth aspect of the present invention, when the second interlayer film is etched through the first and second openings, the taper of the second opening is formed. The second etching stop layer located below the tape is removed to prevent the second wiring layer from being exposed, and when the first interlayer film is further etched, the layer formed below the taper is removed. Protected from etching, the first etching stop layer located under the taper of the second opening is removed together to prevent the first wiring layer from being exposed, and the first and second wiring layers are separated from each other. Since the short circuit is prevented, it is effective in improving the manufacturing yield and reliability of the semiconductor device having the multilayer wiring structure.

According to the semiconductor device manufacturing method of the sixth aspect of the present invention, when the second interlayer film is etched through the first and second openings, the eaves of the second opening are provided. The layer formed in the lower part of the portion is protected from etching, the second etching stop layer located under the eave portion of the second opening is removed together, and the wiring layer is prevented from being exposed. When etching the first interlayer film, the second
Since the first etching stop layer located under the eaves of the opening is removed together to prevent the first wiring layer from being exposed and the wiring layer from being short-circuited, the multilayer wiring structure There is an effect of improving the manufacturing yield and reliability of the semiconductor device.

[Brief description of drawings]

FIG. 1 is a cross-sectional view showing a manufacturing process of a first embodiment of a method for manufacturing a semiconductor device according to the present invention.

FIG. 2 is a cross-sectional view showing the manufacturing process of the first example of the method for manufacturing the semiconductor device according to the present invention.

FIG. 3 is a cross-sectional view showing the manufacturing process of the first example of the method for manufacturing the semiconductor device according to the present invention.

FIG. 4 is a cross-sectional view showing the manufacturing process of the first example of the method for manufacturing the semiconductor device according to the present invention.

FIG. 5 is a cross-sectional view showing the manufacturing process of the first example of the method for manufacturing the semiconductor device according to the present invention.

FIG. 6 is a cross-sectional view showing the manufacturing process of the second embodiment of the method of manufacturing a semiconductor device according to the present invention.

FIG. 7 is a cross-sectional view showing the manufacturing process of the second embodiment of the method of manufacturing a semiconductor device according to the present invention.

FIG. 8 is a cross-sectional view showing the manufacturing process of the second embodiment of the method of manufacturing a semiconductor device according to the present invention.

FIG. 9 is a cross-sectional view showing the manufacturing process of the second embodiment of the method of manufacturing a semiconductor device according to the present invention.

FIG. 10 is a second method of manufacturing a semiconductor device according to the present invention.
FIG. 7 is a cross-sectional view showing the manufacturing process of the example.

FIG. 11 is a second method of manufacturing a semiconductor device according to the present invention.
FIG. 7 is a cross-sectional view showing the manufacturing process of the example.

FIG. 12 is a third method of manufacturing a semiconductor device according to the present invention.
FIG. 7 is a cross-sectional view showing the manufacturing process of the example.

FIG. 13 is a third method for manufacturing a semiconductor device according to the present invention.
FIG. 7 is a cross-sectional view showing the manufacturing process of the example.

FIG. 14 is a third method for manufacturing a semiconductor device according to the present invention.
FIG. 7 is a cross-sectional view showing the manufacturing process of the example.

FIG. 15 is a third method for manufacturing a semiconductor device according to the present invention.
FIG. 7 is a cross-sectional view showing the manufacturing process of the example.

FIG. 16 is a plan view showing a layout pattern of a semiconductor device having a two-layer wiring structure.

FIG. 17 is a fourth method of manufacturing a semiconductor device according to the present invention.
FIG. 7 is a cross-sectional view showing the manufacturing process of the example.

FIG. 18 is a fourth method of manufacturing a semiconductor device according to the present invention.
FIG. 7 is a cross-sectional view showing the manufacturing process of the example.

FIG. 19 is a fourth method of manufacturing a semiconductor device according to the present invention.
FIG. 7 is a cross-sectional view showing the manufacturing process of the example.

FIG. 20 is a fourth method of manufacturing a semiconductor device according to the present invention.
FIG. 7 is a cross-sectional view showing the manufacturing process of the example.

FIG. 21 is a fourth method of manufacturing a semiconductor device according to the present invention.
FIG. 7 is a cross-sectional view showing the manufacturing process of the example.

FIG. 22 is a fourth method of manufacturing a semiconductor device according to the present invention.
FIG. 7 is a cross-sectional view showing the manufacturing process of the example.

FIG. 23 is a fourth method of manufacturing a semiconductor device according to the present invention.
FIG. 7 is a cross-sectional view showing the manufacturing process of the example.

FIG. 24 is a fourth method for manufacturing a semiconductor device according to the present invention.
FIG. 7 is a cross-sectional view showing the manufacturing process of the example.

FIG. 25 is a fourth method of manufacturing a semiconductor device according to the present invention.
FIG. 7 is a cross-sectional view showing the manufacturing process of the example.

FIG. 26 is a fourth method for manufacturing a semiconductor device according to the present invention.
FIG. 7 is a cross-sectional view showing the manufacturing process of the example.

FIG. 27 is a fourth method for manufacturing a semiconductor device according to the present invention.
FIG. 7 is a cross-sectional view showing the manufacturing process of the example.

FIG. 28 is a fifth method for manufacturing a semiconductor device according to the present invention.
FIG. 7 is a cross-sectional view showing the manufacturing process of the example.

FIG. 29 is a fifth method for manufacturing a semiconductor device according to the present invention.
FIG. 7 is a cross-sectional view showing the manufacturing process of the example.

FIG. 30 is a fifth method for manufacturing a semiconductor device according to the present invention.
FIG. 7 is a cross-sectional view showing the manufacturing process of the example.

FIG. 31 is a fifth method of manufacturing a semiconductor device according to the present invention.
FIG. 7 is a cross-sectional view showing the manufacturing process of the example.

FIG. 32 is a fifth method of manufacturing a semiconductor device according to the present invention.
FIG. 7 is a cross-sectional view showing the manufacturing process of the example.

FIG. 33 is a fifth method of manufacturing a semiconductor device according to the present invention.
FIG. 7 is a cross-sectional view showing the manufacturing process of the example.

FIG. 34 is a fifth method for manufacturing a semiconductor device according to the present invention.
FIG. 7 is a cross-sectional view showing the manufacturing process of the example.

FIG. 35 is a fifth method of manufacturing a semiconductor device according to the present invention.
FIG. 7 is a cross-sectional view showing the manufacturing process of the example.

FIG. 36 is a cross-sectional view showing a manufacturing process of a conventional method for manufacturing a semiconductor device.

FIG. 37 is a cross-sectional view showing the manufacturing process of the conventional method for manufacturing a semiconductor device.

FIG. 38 is a cross-sectional view showing the manufacturing process of the conventional method for manufacturing a semiconductor device.

FIG. 39 is a cross-sectional view showing the manufacturing process of the conventional method for manufacturing a semiconductor device.

FIG. 40 is a cross-sectional view showing the manufacturing process of the conventional method for manufacturing a semiconductor device.

FIG. 41 is a cross-sectional view showing the manufacturing process of the conventional method for manufacturing a semiconductor device.

[Explanation of symbols]

90 polycrystalline silicon film (non-oxidized layer), 104a, 10
4b gate electrode (wiring layer, first wiring layer), 108
Etching stopper film (etching stop layer), 10
9,900 interlayer film, 111, 211 resist pattern, 201 metal film, 202 oxide film, 201a, 20
1b Metal wiring (second wiring layer), 202a, 202b
Protective film, 203a to 203d Side wall, 20
5 second interlayer film, 206 third etching stopper film (third etching stop layer), 206T, 210T
Taper, 206S, 208S, 210S inclined part, 2
06F, 208F, 210F flat portion, 208 first etching stopper film (first etching stop layer),
209 first interlayer film, 210 second etching stopper film (second etching stop layer), 206E, 21
0E eaves part, 501a, 501b first layer wiring, 502
a, 502b Second layer wiring, original region where 503 contact hole is provided, position where 503A contact hole is provided.

Continuation of front page (51) Int.Cl. ⁶ Identification code Office reference number FI Technical display area H01L 21/306 F

Claims (6)

[Claims] 1. A step of: (a) arranging a wiring layer on a semiconductor substrate with a space therebetween; and (b) covering the wiring layer with an etching stopper layer for preventing the wiring layer from being etched. A step of: (c) forming an interlayer film between the etching stopper layer and a layer formed further thereon; (d) selectively removing the interlayer film and the etching stopper layer in order, and A step of forming a contact hole reaching the semiconductor substrate between wiring layers, wherein the step (c) comprises: (e) a non-etching ratio of 5 or more on the etching stop layer to the etching stop layer. A method of manufacturing a semiconductor device, comprising a step of forming an oxide layer, and comprising (f) a step of oxidizing the non-oxidized layer to form the interlayer film after the step (d). 2. The step (b) is a step of forming the etching stop layer of silicon nitride, and the step (e) includes a step of forming the non-oxidized layer of polycrystalline silicon. 1. The method for manufacturing a semiconductor device according to 1. 3. A step of: (a) arranging a wiring layer on a semiconductor substrate with a space therebetween; (b) a first etching stop layer for preventing the wiring layer from being etched; A step of covering the layer; (c) a step of forming an interlayer film between the etching stopper layer and a layer formed further above; (d) selecting the interlayer film and the first etching stopper layer in order. And removing the contact holes to reach the semiconductor substrate between the wiring layers, and the step (d) is (e) formed on the interlayer film via a second etching stop layer. Selectively remove the resist layer,
A step of forming a first opening reaching the second etching stop layer, and (f) the second etching stop layer being continuous with the first opening and having a cross-sectional shape of the first opening. A semiconductor device including a step of forming a tapered second opening whose opening size on the opening side is equal to that of the first opening and whose opening size gradually decreases toward the interlayer film. Manufacturing method. 4. (a) a step of arranging wiring layers on a semiconductor substrate with a space therebetween, and (b) the wiring with a first etching stop layer for preventing the wiring layer from being etched. A step of covering the layer; (c) a step of forming an interlayer film between the etching stopper layer and a layer formed further above; (d) selecting the interlayer film and the first etching stopper layer in order. And removing the contact holes to reach the semiconductor substrate between the wiring layers, and the step (d) is (e) formed on the interlayer film via a second etching stop layer. Selectively remove the resist layer,
Forming a first opening reaching the second etching stop layer, and (f) forming a second opening continuous with the first opening in the second etching stop layer, The method further comprises the step of expanding the opening size of the first opening to expose the second etching stop layer and forming an eave portion that becomes an eave with respect to the layer formed below. Manufacturing method of semiconductor device. 5. A step of: (a) disposing a first wiring layer on a semiconductor substrate at intervals, and (b) a first step for preventing the first wiring layer from being etched. Covering the first wiring layer with an etching stop layer; and (c) forming a first interlayer film between the first etching stop layer and a layer formed further above. d) disposing a second wiring layer with a space on the first interlayer film so as to intersect with the first wiring layer with the first interlayer film interposed therebetween; (e) a step of covering the second wiring layer with a second etching stopper layer for preventing the second wiring layer from being etched, and (f) the second etching stopper layer, A step of forming a second interlayer film between the second interlayer film and a layer formed on the upper layer, and (g) the second interlayer film, the second etching stop layer,
A step of selectively removing the first interlayer film and the first etching stop layer in sequence to form a contact hole reaching the semiconductor substrate between the first wiring layers; And (h) a step of selectively removing a resist layer formed on the second interlayer film via a third etching stop layer to form a first opening reaching the third etching stop layer. And (i) the third etching stop layer is continuous with the first opening and has a cross-sectional shape whose opening dimension on the first opening side is equal to that of the first opening. And a step of forming a tapered second opening whose opening size gradually decreases toward the second interlayer film. 6. (a) a step of disposing a first wiring layer on a semiconductor substrate with a space therebetween, and (b) a first step for preventing the first wiring layer from being etched. Covering the first wiring layer with an etching stop layer; and (c) forming a first interlayer film between the first etching stop layer and a layer formed further above. d) disposing a second wiring layer with a space on the first interlayer film so as to intersect with the first wiring layer with the first interlayer film interposed therebetween; (e) a step of covering the second wiring layer with a second etching stopper layer for preventing the second wiring layer from being etched, and (f) the second etching stopper layer, A step of forming a second interlayer film between the second interlayer film and a layer formed on the upper layer, and (g) the second interlayer film, the second etching stop layer,
A step of selectively removing the first interlayer film and the first etching stop layer in sequence to form a contact hole reaching the semiconductor substrate between the first wiring layers; And (h) a step of selectively removing a resist layer formed on the second interlayer film via a third etching stop layer to form a first opening reaching the third etching stop layer. (I) After forming a second opening continuous with the first opening in the third etching stop layer, the opening size of the first opening is widened to perform the third etching. A method of manufacturing a semiconductor device, which comprises the step of exposing the blocking layer and forming an eaves portion which becomes an eaves to the layer formed below.