JPH09148284A - Method and apparatus for chemical-mechanical polishing and manufacture of semiconductor substrate - Google Patents

Abstract

PROBLEM TO BE SOLVED: To make the thickness of the polishing insulating film farmed on a board uniform by chemical and mechanical polishing the board surface by controlling the polishing pressures at a plurality of two-dimensional areas in the surface. SOLUTION: A workpiece 1 supported by a chuck 2 is brought into contact with a polishing pad 5 while supplying polishing liquid 6 onto the rotating pad 5. Further, the polishing load is applied to the chuck 2 rotated by a motor 3. It is reciprocating moved relatively to a polishing surface plate 4 in the radial direction of the plate 4. The workpiece 1 is chemically and mechanically polished by adopting both the chemical polishing by the chemical reaction with the alkaline solution contained in the liquid 6 and the mechanical polishing by the abrasive of SiO2 or the like. Thus, the thickness of an insulating film or metal film can be made uniform and flat.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a polishing method for flattening a surface of an insulating film, a metal film or the like formed on a substrate for manufacturing a semiconductor integrated circuit or the like by chemical / mechanical polishing. The present invention relates to a semiconductor substrate manufacturing method for manufacturing a semiconductor substrate having the device and a semiconductor integrated circuit.

[0002]

2. Description of the Related Art For example, as a flattening technique for manufacturing a semiconductor substrate having a semiconductor integrated circuit or the like, conventionally, a plasma oxide film (P-SiO ₂ ) is formed and the surface thereof is formed so as to eliminate fine irregularities. This has been performed by a combination of forming a coated insulating film (SOG) by applying liquid glass on the glass and heating it, and performing etch back to reduce the thickness of the insulating film. However, in this flattening technique, a large step remains. Further, as the wiring width decreases, the need for improvement of step coverage has led to the development of Bias-ECRCVD technology and an organic source (TEOS) having a reflow effect. However, it has not been possible to sufficiently improve the step coverage with respect to the reduction of the wiring width accompanying the ultra-high integration. On the other hand, chemical and mechanical polishing (CMP: Chem) for flatly polishing the surfaces of semiconductor chips, ceramic packages, multilayer ceramic packages and other electronic components.
The mechanical mechanical polishing technique is known in the specification and drawings of US Pat. No. 4,954,142. This conventional technique is a CMP (Chemical Mechanical) which is supported on a polishing surface plate and presses the surface of the electronic component against a polishing cloth coated with an abrasive to chemically and mechanically polish the surface.
Polishing).

[0003]

The above prior art (CM)
In P), since the fluctuation of the polishing pressure due to the deformation of the workpiece during the chemical / mechanical polishing is not taken into consideration, the polishing amount of the insulating film on the surface of the workpiece can be controlled. Therefore, there is a problem that the thickness of the insulating film or the like cannot be made uniform.

[0004] An object of the present invention is to solve the above problems.
It is an object of the present invention to provide a chemical / mechanical polishing method and apparatus capable of achieving uniform polishing of the thickness of an insulating film or the like formed on a substrate. Another object of the present invention is to carry out a flat chemical / mechanical polishing process on the surface of the interlayer insulating film on the semiconductor substrate, which has no fine irregularities and has no large steps, and which is, for example, 0.35 μm or less. It is an object of the present invention to provide a chemical / mechanical polishing method and apparatus capable of forming ultrafine wiring. Another object of the present invention is to provide a method of manufacturing a semiconductor substrate, which can simplify the manufacturing of a semiconductor substrate having a multilayer wiring layer having an ultrafine wiring having a wiring width of 0.35 μm or less. .

[0005]

In order to achieve the above object, the present invention controls the polishing pressure in each of a plurality of two-dimensional regions in the surface of a substrate to chemically or mechanically act on the surface of the substrate. It is a chemical / mechanical polishing method characterized by performing various polishing processes. Further, according to the present invention, the distribution of the polishing pressure in each of the plurality of two-dimensional regions in the substrate surface is measured by in-process, and each of the two-dimensional regions is determined according to the distribution of the polishing pressure in each of the measured two-dimensional regions. The chemical / mechanical polishing method is characterized in that the polishing pressure is controlled to perform the chemical / mechanical polishing of the substrate surface. Further, the present invention is characterized in that the polishing pressure in each of a plurality of two-dimensional regions in the surface of the substrate is controlled to chemically and mechanically polish the surface of the insulating film on the substrate. Polishing method.

Further, according to the present invention, the distribution of the polishing pressure in each of the plurality of two-dimensional regions on the surface of the substrate is measured by in-process, and the two-dimensional calculation is performed according to the distribution of the polishing pressure in each of the measured two-dimensional regions. The chemical / mechanical polishing method is characterized in that the polishing pressure in each region is controlled to perform the chemical / mechanical polishing process on the surface of the insulating film on the substrate. Further, the present invention is characterized in that the polishing pressure in each of a plurality of two-dimensional regions in the surface of the substrate is controlled to chemically and mechanically polish the surface of the metal film on the substrate. Polishing method. Further, according to the present invention, the distribution of the polishing pressure in each of the plurality of two-dimensional regions in the substrate surface is measured by in-process, and each of the two-dimensional regions is determined according to the distribution of the polishing pressure in each of the measured two-dimensional regions. The chemical / mechanical polishing method is characterized in that the polishing pressure is controlled to perform chemical / mechanical polishing of the surface of the metal film on the substrate.

Further, according to the present invention, the polishing pressure in each of a plurality of two-dimensional regions in the substrate surface is controlled so that the variation in the polishing amount on the surface of the insulating film on the substrate is ± 5% or less, and the unevenness of the surface of the insulating film is controlled. Is 0.2 μm or less, and a chemical / mechanical polishing process is performed. Further, according to the present invention, the distribution of the polishing pressure in each of the plurality of two-dimensional regions in the substrate surface is measured by in-process, and each of the two-dimensional regions is determined according to the distribution of the polishing pressure in each of the measured two-dimensional regions. The polishing pressure is controlled to control the polishing amount variation of the insulating film surface on the substrate to be ± 5% or less, and the unevenness of the insulating film surface to be 0.2 μm or less for chemical / mechanical polishing. Is a chemical / mechanical polishing method. Further, the present invention is characterized in that, in the above-mentioned chemical / mechanical polishing method, the two-dimensional region is a substantially concentric region.

Further, according to the present invention, an interlayer insulating film forming step of forming an interlayer insulating film on a lower wiring on a substrate, and a plurality of two-dimensional regions on the interlayer insulating film formed in the interlayer insulating film forming step, respectively. And polishing by controlling the polishing pressure at the surface of the interlayer insulating film to be planarized by chemical / mechanical polishing, and the step of flattening by the chemical / mechanical polishing Upper layer wiring forming step of forming a desired upper layer wiring on the above-described interlayer insulating film, and a method of manufacturing a semiconductor substrate. The present invention also provides an interlayer insulating film forming step of forming an interlayer insulating film on a lower wiring on a substrate, and a polishing pressure in each of a plurality of two-dimensional regions on the interlayer insulating film formed in the interlayer insulating film forming step. And a chemical / mechanical polishing step of performing flattening by performing chemical / mechanical polishing on the surface of the interlayer insulating film,
A contact hole forming step of forming a contact hole in the interlayer insulating film flattened in the chemical / mechanical polishing step, and a contact by filling a conductive material in the contact hole formed in the contact hole forming step. A method for manufacturing a semiconductor substrate, comprising: a contact stud forming step of forming a stud; and an upper layer wiring forming step of forming a desired upper layer wiring on the interlayer insulating film after the contact stud forming step. .

Further, according to the present invention, an interlayer insulating film forming step of forming an interlayer insulating film on a lower wiring on a substrate, and a plurality of two-dimensional regions on the interlayer insulating film formed in the interlayer insulating film forming step, respectively. Chemical / mechanical polishing step of controlling the polishing pressure in the step of chemically / mechanically polishing the surface of the interlayer insulating film, and the interlayer flattened by the chemical / mechanical polishing step. and characterized in that it comprises a SiO ₂ film forming step of forming by CVD a SiO ₂ film on the insulating film, an upper layer wiring forming step of forming an upper layer wiring on the SiO ₂ film formed by the SiO ₂ film forming step And a method for manufacturing a semiconductor substrate. Further, the present invention comprises a control means for controlling the fluid pressure applied from the back surface of the substrate to control the polishing pressure in each of the plurality of two-dimensional regions in the surface of the substrate, and chemically controls the surface of the substrate to be flat. The chemical / mechanical polishing apparatus is characterized by being configured to perform mechanical polishing processing.

The present invention also provides a plurality of two in-plane substrates.
Measuring means for in-process measuring the distribution of the polishing pressure in each of the two-dimensional areas, and controlling the fluid pressure applied from the back surface of the substrate according to the distribution of the polishing pressure in each of the two-dimensional areas measured by the measuring means. And a control means for controlling the polishing pressure in each of the two-dimensional regions, and the chemical and mechanical polishing is performed on the surface of the substrate. It is a polishing device. As described above, according to the present invention, for example, the thickness of the interlayer insulating film in the semiconductor device can be made uniform, so that high reliability and high integration of the semiconductor device can be realized. That is, since the semiconductor integrated circuit forms a multilayer wiring layer, an interlayer insulating layer exists between the lower layer wiring and the upper layer wiring, and the surface of this interlayer insulating film has, for example, a polishing amount variation of ± 5% or less with accuracy. Moreover, the fine unevenness is 0.2
A wiring film having a uniform thickness can be formed on the interlayer insulating film, and a focus margin in exposure can be expanded to easily form a wiring width of 0.35 μm.
The following wiring can be formed. Further, a step of about 1 μm existing on the surface of the interlayer insulating film before polishing can be made into a minute unevenness of 0.1 μm or less after polishing, and as a result, a wiring width of 0.25 μm or less can be formed on the surface of the interlayer insulating layer. Wiring can be easily formed.

Further, according to the present invention, when a conductor such as tungsten is formed as a contact stand in the contact hole formed in the interlayer insulating layer by selective CVD, the fine defects on the interlayer insulating film grow as nuclei. There is an effect that the conductive film such as tungsten can be completely removed, and the wiring having high reliability can be formed on the interlayer insulating film. Further, according to the present invention, since high flatness can be obtained on the surface of the insulating film or the metal film, for example, defocusing can be prevented in the exposure process, exposure with high resolution can be realized, and high integration can be achieved. can do.

[0012]

Embodiments of the present invention will be described with reference to the drawings. An overall configuration and a polishing procedure showing an embodiment of a chemical / mechanical polishing apparatus according to the present invention will be described with reference to FIG. FIG. 1 is a conceptual diagram of a chemical and mechanical polishing apparatus. In FIG. 1, a workpiece 1 (a substrate such as a wafer (semiconductor substrate)) is a chuck 2
Attached to. On the polishing platen 4, a polishing pad 5 made of, for example, a hard polyurethane foam, which is resistant to acids and alkalis and has excellent wear resistance, is attached to improve the flatness. On the polishing pad 5, colloidal silica containing SiO ₂ abrasive grains in a solution containing alkali, and polishing liquid 6 containing alumina or cerium oxide abrasive grains in a solution containing acid are supplied. Load sensor 7 installed on the polishing surface plate 4
Is connected to the control device 11 via a signal line a8, a slip ring 9 and a signal line b10. The pressure control valve 14 is
It is connected to the control device 11 via a signal line c12. The fluid 13 is supplied to the chuck 2 via the flow rate control valve 14, the fluid supply pipe 15 and the rotary joint 16.
The motor 3 is connected to the control device 11 via a signal line d17. Reference numeral 2 is a chuck that is rotatable by a motor 3.

In the chemical / mechanical polishing process, the workpiece 1 supported by the chuck 2 is placed on the polishing pad 5 while supplying the polishing liquid 6 onto the rotating polishing pad 5 as shown in FIG. When the polishing load is applied to the chuck 2 which is brought into contact with the chuck 2 and is rotated by the motor 3, the polishing liquid is relatively reciprocated relative to the polishing platen 4 in the radial direction of the polishing platen 4 as shown by an arrow 43. Chemical mechanical polishing (CMP: Chemical Mechanical Polishing) is performed by a combination of chemical polishing by a chemical reaction with an alkaline solution contained in 6 and mechanical polishing by abrasive grains such as SiO _2. It is performed on a workpiece (for example, the surface of an insulating film on a semiconductor substrate such as a wafer) 1. That is, the workpiece 1 is an insulating film (for example, a plasma TEOS film) on the semiconductor substrate.
When the polishing liquid is supplied to the rotating polishing pad 5, the insulating film on the semiconductor substrate supported by the chuck 2 is brought into contact with the polishing pad 5 and the polishing load is applied to the rotating chuck 2 by the motor 3. Add arrow 43
When the polishing platen 4 is reciprocally moved relative to the polishing platen 4 in the radial direction, the surface of the insulating film undergoes a chemical reaction with the alkaline solution contained in the polishing liquid 6. While being carried out, mechanical polishing was carried out by the abrasive grains such as SiO ₂ contained in the polishing liquid 6 to proceed with chemical / mechanical polishing processing, and fine irregularities were flattened to 0.01 μm or less. Thus, it is possible to obtain an interlayer insulating film having a desired film thickness with a variation in polishing amount of ± 5% or less. In the case of chemical / mechanical polishing for a metal film, the polishing liquid 6 may be colloidal silica obtained by adding SiO ₂ abrasive grains to a solution containing alkali, or alumina or cerium oxide in a solution containing acid. Those containing abrasive grains are used.

During the chemical / mechanical polishing process, the workpiece 1 together with the chuck 2 reciprocates in the radial direction of the polishing table 4 as indicated by an arrow 43, and the load sensor 7 is moved.
Will reach the place where is installed and will contact the load sensor 7. When the workpiece 1 comes into contact with the load sensor 7 in this way, the load is detected by the load sensor 7 and the load signal is input to the slip ring 9 via the signal line 8. The load signal output from the slip ring 9 is input to the control device 11 via the signal line 10. Control device 1
1 is the workpiece 1 obtained by dividing the value of the load detected by the load sensor 7 by the area of the load sensor 7 which is a known value input by the input means 40 such as a keyboard.
The in-plane polishing pressure distributions P1 to Pn are calculated. After controlling the pressure of the fluid 13 with the fluid control valve 14 so that the obtained distributions P1 to Pn of the polishing pressure become uniform,
The fluid supply pipes 15 provided corresponding to the respective regions 1 to n introduce the fluid into the chuck 2 via the rotary joint 16 to the fluid supply ports 20 provided corresponding to the respective regions,
The fluid 13 is supplied to each region 1 to n on the back surface of the workpiece 1. While the load sensor 7 passes over the workpiece 1, the control device 11 sends a stop signal to the motor 3 via the signal line 17 to stop the rotation of the chuck 2 to stop the workpiece (wafer or the like). The in-plane pressure of the substrate 1) may be measured.
Reference numeral 41 denotes display means such as a display provided in the control device 11, which is controlled by the load value detected by the load sensor 7, the calculated polishing pressure distributions P1 to Pn, and the fluid control valve 14. The fluid pressure to the fluid supply port 20 corresponding to each area is displayed. The display means 41 can display the polishing time calculated according to the average polishing pressure Pave, or can display the polishing end point. A storage device 42 is provided in the control device 11 and stores various data described later.
The control program may be stored in the storage device 42 instead of being stored in the memory in the control device 11.

Next, the control of the polishing pressure by the chuck 2 will be described with reference to FIG. 2A is a sectional structural view of the chuck 2, and FIG. 2B is a plan view for explaining a region where the chuck 2 controls the polishing pressure. In the chuck 2, 18 is a substrate retainer for preventing the workpiece (substrate such as wafer) 1 from coming off the chuck 2 during polishing, and 19 supports the workpiece (substrate such as wafer) 1 during polishing. Is a support formed of an elastic body, 20 is a fluid supply port, and 21 is a fluid exhaust port. Reference numeral 22 denotes an annular belt-shaped area 1 which is a two-dimensional area for controlling the polishing pressure, 23 denotes an annular belt-shaped area 2 which is a two-dimensional area, and 24 denotes an annular belt-shaped area n which is a two-dimensional area. It should be noted that these regions may be band-shaped regions formed of regular polygons instead of being circular. These regions 1 to n are arranged substantially concentrically. The fluid having the pressures Ps1 to Psn is supplied to the fluid supply port 20, and the fluid having the pressures P1 to Pn is supplied to the back surface of the workpiece 1. A fluid exhaust port 21 is provided between the regions where the polishing pressure is controlled to prevent the fluid supplied to each region by the fluid supply port 20 from flowing into another region. be able to. That is, the fluid supplied to each region by the fluid supply port 20 is a workpiece (substrate such as wafer) 1
While being pressed against the back surface of No. 1 to give a polishing pressure, the fluid is exhausted from the fluid exhaust ports 21 provided at the inner and outer peripheries of the region and flows. Even if the fluid exhaust port 21 is not formed on the outermost periphery, the fluid supplied to the region n by the fluid supply port 20 escapes from the gap between the outer periphery of the workpiece 1 and the substrate retainer 18. Can be flushed.

FIG. 3 is an enlarged cross-sectional view of the support portion of the work piece 1. The support 19 is provided with a hole 26 and an annular recess 25 connected to the fluid supply port 20 and an annular groove 27 connected to the fluid exhaust port 21 corresponding to each region. Supply pressure P introduced into the area
The fluid of s1 to Psn passes through the hole 26 and the workpiece 1
Annular recess 2 between the back surface of the base and the support 19 which is an elastic body
5, the pressing force P1 to Pn is applied to the workpiece (substrate such as wafer) 1 in each region to obtain the polishing pressure P1 ′ to Pn ′, and the workpiece (substrate such as wafer) The fluid supplied to the back surface of No. 1 is an extremely small amount formed between the back surface of the workpiece 1 and the projections 28 formed on the inner and outer circumferences of the annular recess 25 provided corresponding to each region. It flows through the small gap into the annular groove 27 and is exhausted from the fluid exhaust port 21.

Here, the area a of the fluid supply port 20 is a value determined by the following equation (1). a = πd ^2/4 ··· (Equation 1) where, d is the diameter of the fluid supply port 20. Further, the outflow velocity coefficient φ of the orifice is a value determined from the adiabatic index κ of the fluid from the following (Equation 2). However, g is gravitational acceleration.

[0018]

(Equation 2)

Accordingly, the pressure Po (each of P1 to Pn) of the fluid supplied to each region on the back surface of the workpiece (substrate such as wafer) 1 is equal to that of the fluid supplied from the fluid supply port 20 to each region. The relationship between the supply pressure Ps (each of Ps1 to Psn) and the expression (3) shown below is established.

[0020]

(Equation 3)

Where Pa is the atmospheric pressure, μ is the viscosity coefficient of the fluid, γa is the specific weight of the fluid at atmospheric pressure and room temperature, Co is the flow coefficient of the orifice, R is the gas constant, To is the temperature of the fluid, and 2Ro is each. The distance between the fluid exhaust ports 21 provided on the inner and outer circumferences of the region, 2Ri is the diameter of the hole 26 formed in the support 19 connected to the liquid supply port 20, and h is the maximum of the annular recess 25. Depth. By inputting these various types of data using the input means 40 and storing them in the storage device 42, for example, the control device 11 causes each region controlled by the flow rate control valve 14 to be based on the equation (3). Supply pressure Ps of the fluid supplied from the fluid supply port 20 (Ps1
To Psn) can be calculated.

As is clear from the equation (3), the supply pressure Ps of the fluid supplied from the fluid supply port 20 to each region.
As (Ps1 to Psn) increases, the pressure Po (P1 to Pn) of the fluid supplied to each region on the back surface of the workpiece (substrate such as wafer) 1 also increases,
The value of the supply pressure Ps of the fluid in each of the above regions is set to the flow control valve 14
The value of the pressure Po of the fluid supplied to each of the above regions (the pressing force applied to each region of the workpiece 1) can be controlled by controlling by the above. The pressure of the fluid supplied to each region between the elastic body 19 and the workpiece (substrate such as wafer) 1 becomes concentric and independent pressures P1 to Pn as shown in the figure, and the fluid is supplied to each region. By controlling the distribution Ps1 to Psn of the supply pressure of the fluid supplied from the port 20 by the flow rate control valve 14, the distributions P1 to Pn of the polishing pressure can be controlled. In this case, during polishing, a polishing pressure corresponding to the values of the pressures P1 to Pn of the fluid supplied to each region between the elastic body 19 and the workpiece 1 is applied to each region of the workpiece 1. Will be.

FIG. 4 is a detailed view of the load sensor 7 shown in FIG. Reference numeral 29 is a contact of the load sensor 7, which is attached so as to contact the back surface of the polishing pad 5. When the workpiece (substrate such as a wafer (semiconductor substrate)) 1 passes over the load sensor 7 during the polishing process, the polishing pad 5 is deformed and the position of the contact 29 is displaced, resulting in a voltage corresponding to the polishing pressure. The signal is output via the signal line 8. Next, a method for measuring the polishing pressure and a method for controlling the polishing pressure will be described below. FIG.
It is an explanatory view of distribution of polishing pressure in a field of work piece 1 (wafer). Reference numeral 30 is the locus of the load sensor 7, and 31 is the distribution of the polishing pressure. The distribution of the polishing pressure when the locus 30 of the load sensor 7 passes through the center of the workpiece 1 during the chemical / mechanical polishing process is measured from the end point A to the end point A ′ of the work piece 1. The polishing pressures measured and measured in the regions 1 to n are defined as polishing pressures P1 ′ to Pn ′, respectively. Next, assuming that the number of regions is n, the average value Pave of the polishing pressures P1 ′ to Pn ′ can be calculated by the control device 11 from the relationship of the following (Formula 4).

Pave = (P1 ′ + P2 ′ + ... + Pn ′) / n ... (Equation 4) The control device 11 controls the load sensor 7 in the area 1, for example.
When the polishing pressure P1 ′ measured in step S4 is smaller than the average value Pave of the measured values of the polishing pressure, the pressure control valve 14 is adjusted (controlled) to supply pressure Ps of the fluid supplied to the region n.
1 is increased to increase the pressure P1 of the fluid supplied to the back surface of the workpiece (substrate such as wafer) 1 and then P1 ′ is increased again.
And Pave are measured, P1 'and Pave are compared, and P
When 1 ′ is smaller than Pave, Ps1 is further increased, and when P1 ′ is larger than Pave, Ps1 is increased.
By reducing s1, P1 'and Pave were made equal. Similarly, the control device 11 controls the pressure control valve 14
Is controlled to control the supply pressures Ps2 to Psn of the fluid supplied to the respective regions 2 to n so that P2 ′ to Pn ′ measured by the load sensor 7 are equal to Pave. In addition,
The polishing pressures P1 ′ to Pn ′ measured by the load sensor 7 for the respective regions 1 to n and the pressure P1 of the fluid supplied to the respective regions 1 to n on the back surface of the workpiece (substrate such as wafer) 1 described above. Since there is a proportional relationship between the load sensor 7 and each of the regions 1 to n.
The supply pressures Ps1 to Psn of the fluid supplied to the respective regions 1 to n controlled by the pressure control valve 14 can be calculated from the polishing pressures P1 ′ to Pn ′ measured with respect to it can.

[0025]

EXAMPLES Next, a plasma TEOS film (1.
The case of application to an interlayer insulating film formed of 5 μm deposition) will be described. The main chemical / mechanical polishing conditions are: polishing pressure: 30-40 kPa, polishing liquid 6: colloidal silica made of an alkaline solution (particle size: about 30 nm), polishing pad 5: hard polyurethane foam (hardness: about 60 degrees). A suede type elastic body having a thickness of 0.95 mm and a thickness of about 0.5 mm formed on the surface of the chuck is used as the support 19 of the semiconductor substrate. The diameter of the hole 26 formed in the elastic body 19 was 2 mm, and the diameter of the fluid supply port and the fluid exhaust port was 0.8 mm. The following (Table 1) relates to the comparative example and the present invention in the case where the polishing pressure is not controlled (the semiconductor substrate is fixed to the support of the chuck) in the chemical / mechanical polishing process for the interlayer insulating film. FIG. 6 is a comparison between an example of controlling a polishing pressure distribution and an insulating film thickness after polishing and a variation in polishing amount.

[0026]

[Table 1]

In Table 1, Comparative Examples 1 to 3 show experimental results as comparative examples when the polishing pressure is not controlled (the semiconductor substrate is fixed to the support of the chuck). Comparison 1
In Nos. 3 and 3, when the plasma TEOS film (1.5 μm deposited) was chemically and mechanically polished to a residual film thickness of 0.5 μm, the variation in polishing amount was ± 8%, ± 7%. It was shown that. In Comparative Example 2, when the plasma TEOS film (1.5 μm deposited) was chemically and mechanically polished to a residual film thickness of 0.45 μm, the variation in polishing amount was ± 12%. Indicates. (Table 1),
Examples 1 to 3 show experimental results as examples when controlling the polishing pressure distribution according to the present invention. In Example 1, the control of the polishing pressure distribution was poor, and the plasma TEOS film (1.5
When chemical / mechanical polishing is applied to the residual film thickness of 0.45 μm, the variation in polishing amount is ± 6%. In Examples 2 and 3, the polishing pressure distribution was well controlled, and the plasma TEOS film (1.5 μm deposition) was chemically and mechanically polished to a residual film thickness of 0.5 μm. Variation of ± 5%
It is shown that the following values were ± 2% and ± 3%. The chemical / mechanical polishing characteristics were evaluated by the variation in the polishing amount of the insulating film after polishing. For the evaluation, the thickness of the insulating film was measured at 49 points in the plane of the semiconductor substrate (wafer) using a light interference type thin film thickness meter. Then, the maximum value of the thickness of the insulating film is set to Tma
x, the minimum value is Tmin, and the average value is Tave,
The film thickness variation V was calculated from the following (Equation 5).

V = ± 100 (Tmax-Tmin) / 2Tave (Equation 5) As can be seen from Table 1 showing the results of each of these experiments,
It was confirmed that the effect of reducing the variation in film thickness of the interlayer insulating film was obtained by controlling the polishing pressure distribution as in the present invention as compared with the comparative example. Further, by controlling the polishing pressure distribution as in the present invention, the step difference of 1 μm existing on the surface of the insulating film before polishing could be reduced to 0.1 μm or less after polishing. This value is a value that enables formation of a wiring having a wiring width of 0.25 μm or less on this interlayer insulating film. Next, a semiconductor device having a two-layer aluminum wiring structure on a 6-inch silicon substrate was manufactured by applying a chemical / mechanical polishing method of controlling the polishing pressure distribution according to the present invention. An example will be described with reference to FIG.

That is, reference numeral 61 is a step of forming a first layer of aluminum wiring after forming a semiconductor element on a semiconductor substrate (6 inch silicon substrate). Step 62 is a step of depositing (depositing) a plasma TEOS film (interlayer insulating film) on the first-layer aluminum wiring formed in step 61 by CVD to a thickness of about 1.5 μm. 63 indicates the surface of the plasma TEOS film having a thickness of, for example, 1.5 μm formed in the step 62,
As described in the embodiment of the present invention, it is a step of controlling the polishing pressure distribution and performing chemical / mechanical polishing to planarize the surface. As a result of polishing processing by 1 μm in this step 63, the thickness distribution of the plasma TEOS film was measured using an optical interference type thin film thickness measuring device, and the thickness was 0.5.
It was confirmed that it was μm ± 0.02 μm (the variation of the film thickness was ± 4%). At this time, 1 μm existing on the surface of the plasma TEOS film after depositing the plasma TEOS film
The step difference is measured by a stylus type step measuring device and the cross section of the wafer is observed by SEM.
It was confirmed that the thickness was reduced to μm or less. In addition, the surface roughness of the polished plasma TEOS film was measured using a contact type surface roughness measuring device and an atomic force microscope, and plasma TEOS was measured.
It was confirmed that the surface roughness of the OS film was 0.2 to 0.3 nm Rmax.

Reference numeral 64 denotes a SiO ₂ film having a thickness of 0.1 μm deposited on the surface of the polished plasma TEOS film by CVD (deposition).
This is the step of performing The surface of 65 is flattened in step 64,
This is a step of forming a contact hole for electrical connection with the lower aluminum wiring on the plasma TEOS film polished to a desired thickness by etching. Step 66 is a step of forming a contact via of a conductor made of tungsten or the like in the contact hole formed in the step 65. 67 is a step of forming aluminum upper layer wiring having a width of 0.25 μm on the surface of the SiO ₂ film formed in step 64.
Through the steps 61 to 67 described above, a semiconductor device having a two-layer aluminum wiring structure on a 6-inch silicon substrate can be manufactured. The semiconductor device is manufactured in this way,
As a result of measuring the contact via resistance and the wiring resistance, it was found that there were no contact resistance defects and wiring defects, and a highly reliable semiconductor device could be manufactured.

Next, an example of manufacturing a semiconductor device having a two-layer wiring structure on a semiconductor substrate by applying the chemical / mechanical polishing method of controlling the polishing pressure distribution according to the present invention , FIG. 7 will be described. That is, 71 is a step of forming a lower layer wiring on the semiconductor substrate. 72 is, for example, plasma TEO on the lower layer wiring formed in step 71.
In this step, the S film is deposited (formed) by CVD to a thickness of about 1.5 μm. Reference numeral 73 denotes a plasma TEOS film (interlayer insulating film) having a thickness of, for example, 1.5 μm formed in step 72
The surface of, as described in the embodiment of the present invention,
This is a step of controlling the polishing pressure distribution and performing chemical / mechanical polishing to planarize the surface. 1μ in this step 73
As a result of the polishing process, the thickness is 0.5 μm ± 0.02 μm (the variation in the film thickness is ± 4, as in the embodiment shown in FIG. 6).
%), The unevenness of the film thickness can be controlled to ± 5% or less, and the level difference (fine irregularities) can be reduced to 0.1 μm or less for planarization. The surface roughness of the plasma TEOS film can be 0.2 to 0.3 nm Rmax.

Step 74 is a step in which a contact hole for electrically connecting to the lower layer wiring is formed by etching in the plasma TEOS film whose surface is flattened in step 73 and which is polished to a desired thickness. Step 75 is a step of forming a contact stud made of a conductor such as tungsten by selective CVD with respect to the contact hole formed in step 74. Similarly to step 63, step 76 is a step of controlling the polishing pressure distribution and performing chemical / mechanical polishing to remove the metal film such as tungsten grown on the surface. Reference numeral 77 is a step of forming an upper wiring on the surface of the plasma TEOS film (interlayer insulating film). Step 71 described above
Through 77, it is possible to manufacture a semiconductor device having a multilayer wiring structure on a semiconductor substrate. As a result of manufacturing the semiconductor device and measuring the contact stud resistance and the wiring resistance as described above, it is found that there is no contact resistance defect or wiring defect, and a highly reliable semiconductor device can be manufactured.

The present invention can also be applied to manufacture a thin film multilayer wiring board.

[0034]

According to the present invention, in the chemical / mechanical polishing process, the distribution of the polishing pressure in the surface of the substrate is controlled during polishing to make the thickness of the insulating film, the metal film, etc. uniform. Moreover, since it can be processed flatly (for example, the variation of the film thickness is ± 5% or less and the fine unevenness is 0.2 μm or less), the semiconductor device can be highly reliable and highly integrated.

[Brief description of the drawings]

FIG. 1 is a conceptual diagram showing an embodiment of a chemical / mechanical polishing apparatus according to the present invention.

FIG. 2 is an explanatory view of a chuck portion supporting the workpiece shown in FIG. 1, (a) is a structural view showing a cross section of the chuck,
(B) is a plan view for explaining a region for controlling the polishing pressure by the chuck.

FIG. 3 is an enlarged cross-sectional view of a chuck portion that supports the workpiece shown in FIG.

FIG. 4 is a cross-sectional view showing a load sensor installed on a polishing platen for detecting a polishing pressure according to the present invention.

FIG. 5 is a diagram for explaining a method of measuring a polishing pressure distribution with a load sensor according to the present invention.

FIG. 6 is a diagram showing a process flow which is one embodiment for manufacturing a semiconductor device according to the present invention.

FIG. 7 is a diagram showing a process flow of another embodiment for manufacturing a semiconductor device according to the present invention.

[Explanation of symbols]

1 ... Workpiece (substrate such as wafer), 2 ... Chuck, 3 ...
Motor, 4 ... Polishing surface plate 5 ... Polishing pad, 6 ... Polishing liquid, 7 ... Load sensor, 9 ... Slip ring 11 ... Control device, 13 ... Fluid, 14 ... Pressure control valve, 15
... Fluid supply pipe 16 ... Rotary joint, 18 ... Wafer holder, 19
... Support (elastic body) 20 ... Fluid supply port, 21 ... Fluid exhaust port, 22 ... Region 1,
23 ... Region 2 24 ... Region n, 25 ... Annular recess, 27 ... Annular groove, 2
9 ... Contactor 30 ... Load sensor locus, 31 ... Polishing pressure distribution, 40
Input means 41 Display means 42 Storage device

Claims (14)

[Claims] 1. A chemical / mechanical polishing method in which a polishing pressure in each of a plurality of two-dimensional regions in a substrate surface is controlled to perform a chemical / mechanical polishing process on the substrate surface. Polishing method. 2. A polishing pressure distribution in each of a plurality of two-dimensional regions on a substrate surface is measured by in-process, and each of the two-dimensional regions is measured according to the measured distribution of polishing pressure in each of the two-dimensional regions. The chemical / mechanical polishing method is characterized in that the polishing pressure is controlled to perform the chemical / mechanical polishing processing of the substrate surface. 3. A chemical / mechanical device characterized in that the polishing pressure in each of a plurality of two-dimensional regions within a substrate surface is controlled to perform chemical / mechanical polishing of the surface of an insulating film on the substrate. Polishing method. 4. A polishing pressure distribution in each of a plurality of two-dimensional regions on a surface of a substrate is measured by in-process, and each of the two-dimensional regions is measured according to the measured distribution of polishing pressure in each of the two-dimensional regions. The chemical / mechanical polishing method is characterized in that the polishing pressure is controlled to perform the chemical / mechanical polishing of the surface of the insulating film on the substrate. 5. A chemical / mechanical device, characterized in that a polishing pressure in each of a plurality of two-dimensional regions in a substrate surface is controlled to perform a chemical / mechanical polishing process on a surface of a metal film on the substrate. Polishing method. 6. A polishing pressure distribution in each of a plurality of two-dimensional regions on a substrate surface is measured by in-process, and each of the two-dimensional regions is measured according to the measured polishing pressure distribution in each of the two-dimensional regions. The chemical / mechanical polishing method is characterized in that the polishing pressure is controlled to perform chemical / mechanical polishing of the surface of the metal film on the substrate. 7. A polishing pressure in each of a plurality of two-dimensional regions within a substrate surface is controlled so that variation in polishing amount on the surface of the insulating film on the substrate is ± 5% or less, and unevenness on the surface of the insulating film is reduced to 0. Two
A chemical / mechanical polishing method characterized by performing a chemical / mechanical polishing process with a size of μm or less. 8. A polishing pressure distribution in each of a plurality of two-dimensional regions in a substrate surface is measured by in-process, and each of the two-dimensional regions is measured according to the measured polishing pressure distribution in each of the two-dimensional regions. The polishing pressure is controlled to control the polishing amount variation of the insulating film surface on the substrate to be ± 5% or less, and the unevenness of the insulating film surface to be 0.2 μm or less for chemical / mechanical polishing. Chemical and mechanical polishing processing method. 9. The chemical / mechanical structure according to claim 1, wherein the two-dimensional region is a substantially concentric region. Polishing method. 10. An interlayer insulating film forming step of forming an interlayer insulating film on a lower wiring on a substrate, and a polishing pressure in each of a plurality of two-dimensional regions on the interlayer insulating film formed in the interlayer insulating film forming step. Controlling the surface of the interlayer insulating film to perform a chemical / mechanical polishing process to planarize the surface, and a chemical / mechanical polishing process for planarizing the surface. And a step of forming a desired upper layer wiring on the interlayer insulating film, the method of manufacturing a semiconductor substrate. 11. An interlayer insulating film forming step of forming an interlayer insulating film on a lower wiring on a substrate, and a polishing pressure in each of a plurality of two-dimensional regions on the interlayer insulating film formed in the interlayer insulating film forming step. Of the above-mentioned interlayer insulating film by performing a chemical / mechanical polishing process on the surface of the interlayer insulating film to planarize it, and a planarizing process on the chemical / mechanical polishing process. A contact hole forming step of forming a contact hole in the formed interlayer insulating film, a contact stud forming step of forming a contact stud by burying a conductive material in the contact hole formed in the contact hole forming step, and the contact stud After the forming step, an upper layer wiring forming step of forming a desired upper layer wiring on the interlayer insulating film is provided. 12. An interlayer insulating film forming step of forming an interlayer insulating film on a lower wiring on a substrate, and a polishing pressure in each of a plurality of two-dimensional regions on the interlayer insulating film formed in the interlayer insulating film forming step. A chemical / mechanical polishing process for controlling the surface of the interlayer insulating film by chemical / mechanical polishing, and the interlayer insulating film flattened by the chemical / mechanical polishing process. SiO ₂ film is formed by CVD on SiO ₂
A film forming step, the manufacturing method of a semiconductor substrate and having an upper layer wiring forming step of forming an upper layer wiring on the SiO ₂ film forming step SiO ₂ film formed by. 13. A control means for controlling a fluid pressure applied from the back surface of the substrate to control a polishing pressure in each of a plurality of two-dimensional regions in the surface of the substrate, the surface of the substrate being chemically and flattened. A chemical / mechanical polishing device characterized by being configured to perform mechanical polishing. 14. A measuring means for measuring in-process the distribution of polishing pressure in each of a plurality of two-dimensional areas on a substrate surface, and a polishing pressure distribution in each of the two-dimensional areas measured by the measuring means. And a control means for controlling the fluid pressure applied from the back surface of the substrate to control the polishing pressure in each of the two-dimensional regions, and to chemically and mechanically polish the surface of the substrate. A chemical / mechanical polishing machine characterized by the above.