JPH09147587A - Level shift circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent delay of switching rate of the word line when the power source voltage is low and control noise when the power source voltage is high by controlling a transistor of the level shift with an output of the drive control circuit. SOLUTION: A voltage of the output node 24 of a drive controller 104 having the P channel transistor 29 and N channel transistor 30 is input to the gate of the P channel transistor 26 which perfectly turns off the P channel transistor 27 to charge the node N23 connected to the word line. As explained, voltage of the word line is changed quickly to improve frequency characteristic by controlling the transistor 26 using an output of the drive controller 104 having a light load. Moreover, since it is no longer required to set large the size of transistor, noise generated when the transistor turns on and off can be controlled.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a level shift circuit, and more particularly to an EPROM (electrically programmable ROM).
), It is suitable for use as a circuit for shifting the voltage output from the address decoder to the voltage to be applied to the word line.

[0002]

2. Description of the Related Art In recent years, semiconductor devices such as EPROM have been required to have lower voltage, lower power consumption, and higher speed. In particular, recently, it is possible to guarantee operation at a low power supply voltage of 2 V or less. Is needed.

FIG. 3 shows a conventional level shift circuit and its peripheral circuit configuration. The address decoder 101 receives and decodes the address signals a, b, c and d,
The potential of the output node N21 is changed according to the result. More specifically, the address signals b, c, and d are input to the 3-input NAND circuit 31, and the NAND circuit 31
The source / drain of the N-channel transistor 32 and the source / drain of the P-channel transistor 33 are connected in parallel between the output terminal and the node N21.
The address signal a is input to the gate of the N-channel transistor 32, and the inverted address signal / a is input to the gate of the P-channel transistor 33. The source / drain of the P-channel transistor 34 is connected between the power supply voltage Vcc terminal and the node N21, and the address signal a is input to the gate thereof. Address signal a,
When the word line connected to the node N23 is selected by b, c, and d, the node N21 receives the power supply voltage V
It becomes the ss level and becomes the ground voltage Vcc level when not selected.

Between the node N21 and the node N22,
N-channel transistor 3 as switching unit 102
The source and drain of No. 5 are connected. At the gate,
The power supply voltage Vcc is supplied. When the word line is selected and node N21 is at the ground voltage Vss level, N-channel transistor 35 is on. On the contrary, when the word line is not selected, the node N21 is at the power supply voltage Vcc level and the transistor 35 is turned off.

Nodes N21 and N22 and node N23
A level shift unit 203 is connected between the power supply voltage VSW and the level shift unit 203, and the power supply voltage VSW is supplied to this level shift unit. The power supply voltage VSW is a voltage obtained by boosting the power supply voltage Vcc by a booster circuit (not shown). In recent years, the power supply voltage Vcc
Although a voltage of 2 V or less is also used as the output voltage, the boosted voltage VSW is usually set to about Vcc + 1 (V).

In the level shift unit 203, a P-channel transistor 37 and an N-channel transistor 38 are connected in series between the power supply voltage VSW terminal and the ground voltage Vss terminal, and the drains of the transistors 37 and 38 are commonly connected to the node. It is connected to N23. The voltage of the node N22 having an amplitude of 0 to VSW is supplied to the gate of the P-channel transistor 37, and the N-channel transistor 38
Is supplied with the voltage of the node N21 having an amplitude of 0 to Vcc. The source / drain of the P-channel transistor 36 is connected between the power supply voltage VSW terminal and the node N22, and the potential of the node N23 is applied to the gate.

As described above, when the node N23 is selected, the nodes N21 and N22 are set to the ground voltage Vss level, the P-channel transistor 37 is turned on, the N-channel transistor 38 is turned off, and the node N23 is supplied with the voltage Vs.
Switch to SW level. If the word line is not selected,
The node N21 has the power supply voltage Vcc level, and the node N22 has the power supply voltage VSW boosted by the P-channel transistor 36. The P-channel transistor 37 having this voltage VSW applied to its gate is completely turned off, the N-channel transistor 38 is turned on, and the node N23 is grounded to the ground voltage Vcc.
Become a level.

[0008]

However, the conventional level shift circuit has the following problems. FIG. 4 shows changes in the potentials of the nodes N21 to N23. At time 0, the word line is in the non-selected state and the address signals a to d
Is at the ground voltage Vss level, the node N21 is at the Vcc level, and the node N23 is at the ground voltage Vss level.

After the passage of 35 nsec, the address signals a to d for selecting the word line concerned have the power supply voltage Vcc (1.5
V) level, and both the nodes N21 and N22 become the ground voltage Vss level. The potential of node N23 gradually rises and reaches the boosted voltage VSW level.

Next, when 500 nsec has elapsed, the address signals a to d change to the ground voltage Vss level in order to switch from the word line selected state to the non-selected state. The transistor 34 switches from the off state to the on state, and the node N21 starts rising. Furthermore, in the initial stage when the transistor 35 is turned on, the node N22 also changes to the node N21.
At the same time, it starts rising. However, the transistor 36
From the time when the potential of the node N22 rises to near the circuit threshold determined by the ratio of the conductance Gm of the transistor 37 and the transistor 38, the rise sharply slows. Therefore, the period in which the transistors 37 and 38 are simultaneously turned on becomes long, the through current flowing between the boosted power supply voltage VSW terminal and the ground voltage Vss terminal increases, and the decrease in the potential of the node N23 slows down.

As a result, the switching speed of the word line is delayed, the frequency characteristic is deteriorated, and the boosted voltage VSW level itself is lowered due to the increase of the through current, resulting in a malfunction. Such a phenomenon occurs more notably when the power supply voltage Vcc is a low voltage of 2 V or less, and when the thresholds of the transistors 36 and 37 are low and the threshold of the transistor 38 is high.

The cause of such a phenomenon is that the DC component is the ratio of the conductance Gm of the transistor 36 and the transistor 38, and the transistor 37 is the transistor 3.
The ratio of the conductance Gm to 8 and the AC component include the load capacitance of the node N23. In order to solve the above problem, a method of increasing the conductance Gm of the transistor 38 may be considered, but the transistor 38 is provided for driving the word line directly connected to the node N23, and its original role is fulfilled. Considering conductance G
It is not necessary to make m too high. Furthermore, the node N23
In order to speed up the fall of the transistor 38, the size W of the transistor 38 must be set to a large value, but in this case, a large amount of noise will be generated when the transistor is turned on and off, and the operating margin of Cause decline. This phenomenon is likely to occur particularly when the power supply voltage Vcc is relatively high and the thresholds of the transistors 36 and 37 are high and the thresholds of the transistors 35 and 38 are low. Further, if the size of the transistor is increased, the area will be increased.

Further, the node N at a low power supply voltage
In order to solve the conflicting problems of speeding up the voltage drop of No. 23 and noise suppression at high power supply voltage, optimization is required every time the process is changed, and the development period is greatly reduced. Bring an extension.

The present invention has been made in view of the above circumstances, and it is possible to prevent the switching speed delay of a word line at a low power supply voltage and suppress noise at a high power supply voltage to prevent an increase in chip size. An object is to provide a possible level shift circuit.

[0015]

A level shift circuit according to the present invention is a switching circuit which has one end connected to an output terminal of an address decoder supplied with a first power supply voltage and which is opened / closed in accordance with selection or non-selection of a word line. Section and a second power supply voltage higher than the first power supply voltage, the input side is connected to one end and the other end of the switching unit, and the level changes according to selection or non-selection of the word line. A level shift unit that outputs a signal, the level shift unit including a charging unit that charges the other end of the switching unit, and the second power supply voltage supplied to the one end and the other end of the switching unit. And a drive control unit that is connected to the input side and controls the drive of the charging unit according to selection or non-selection of the word line.

Here, the charging means is connected between a terminal for outputting the second power supply voltage and the other end of the switching section, and is connected to the other of the switching section according to the control operation of the drive control section. It may include a transistor for charging the end.

In addition, another level shift circuit according to the present invention includes a switching section having one end connected to an output terminal of an address decoder supplied with a first power supply voltage, and the first shift circuit.
A first P-channel transistor and a first N-channel transistor connected in series between a second power supply voltage terminal higher than the power supply voltage and a ground voltage terminal, the second power supply voltage terminal and the switching A second P-channel transistor connected to the other end of the element, the gate of the first P-channel transistor being connected to the other end of the switching element, A third P connected in series between the level shift section whose gate is connected to one end of the switching element and the second power supply voltage terminal and the ground voltage terminal.
A channel transistor and a second N-channel transistor, wherein the gate of the third P-channel transistor is connected to the other end of the switching,
And a drive control unit in which the gate of the channel transistor is connected to one end of the switching element.

Here, the switching element has a third end connected between the output terminal of the address decoder and the gate of the first P-channel transistor, and the gate to which the first power supply voltage is applied. N-channel transistor may be included.

The third P-channel transistor and the second N-channel transistor may be set smaller in size than other transistors.

[0020]

DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 shows the configuration of the level shift circuit according to this embodiment. In the circuit shown in FIG. 3, the node N
By inputting the boosted power supply voltage VSW level to the gate of the transistor 37 that charges 23,
The potential of the node N23 was directly input to the gate of the transistor 36 for completely turning off the transistor. On the other hand, in the present embodiment, the drive control unit 104 including the P-channel transistor 29 and the N-channel transistor 30.
Is used to control the driving of the transistor 26.

The address decoder 101 and the switching circuit 102 are the same as those shown in FIG. 3, and their explanations are omitted.

The level shift unit 103 operates to boost the power source voltage V.
A P-channel transistor 27 and an N-channel transistor 28 are connected in series between the SW terminal and the ground voltage Vss terminal. The gate of the transistor 27 is connected to the node N22, and the gate of the transistor 28 is connected to the node N21. Both ends of the P-channel transistor 26 are connected between the node N22 to which the gate of the transistor 27 is connected and the boosted power supply voltage VSW terminal. The output node N24 of the drive control unit 104 is connected to the gate of the transistor 26. In the drive control unit 104, the P-channel transistor 29 and the N-channel transistor 30 are connected in series between the boosted power supply voltage VSW terminal and the ground voltage Vss terminal, and the drain of the transistor 29 and the drain of the N-channel transistor 30 are output. Commonly connected to the node N24. The gate of the transistor 29 is connected to the node N22 having an amplitude width of 0 to VSW, and the gate of the transistor 30 is connected to the node N21 having an amplitude width of 0 to Vcc.

The present embodiment having such a configuration operates as follows. The potentials of the nodes N21 to N24 change as shown in FIG. The relation between the selected / non-selected state of the word line and the potentials of the nodes N21, N22, N23 is the same as that of the level shift circuit shown in FIG. In FIG. 2, the time is about 500
When nsec elapses and the word line is switched from the selected state to the non-selected state, the nodes N21 and N22 rise at almost the same time. In the circuit shown in FIG. 3, as described above, the potential of the node N22 reaches the vicinity of the circuit threshold determined by the ratio of the threshold voltage of the transistor 36 to the total threshold voltage of the transistor 36 and the threshold voltage of the transistor 37. Then, the rising speed slows down. This is because the word line is directly connected to the gate of the transistor 36 and the potential of the node N23, which has a heavy load, is directly input.

On the other hand, in the present embodiment, since the potential of the node N24 having a light load is input to the gate of the transistor 26, the rise of the node N22 is almost the same as that of the node N21 without slowing down. . This allows
The period in which the transistor N27 and the transistor N28 are simultaneously turned on is very short, and the shoot-through current flowing between the boosted power supply voltage VSW terminal and the ground voltage Vss terminal is greatly reduced. As a result, the node N23 connected to the word line
Causes a rapid fall, and thus the frequency characteristic is improved.

Here, the transistors 29 and 30 of the drive controller 104 can be formed in a smaller size than other transistors. For example, the transistor 32
~ 35, transistor 26-28 size W / L 20
Assuming / 6 to 40/6, a size W / L of the transistors 29 and 30 of about 6/6 to 14/6 is sufficient. Therefore, even if the drive control unit 104 is added, it is possible to suppress the chip area so much that the through current in the drive circuit 104 does not affect the characteristics. Further, since it is not necessary to increase the size W of the transistor 28, it is possible to suppress the generation of noise during on / off even when the power supply voltage Vcc is high.

The above-described embodiment is an example and does not limit the present invention. For example, although the drive control unit is composed of the P-channel transistor P29 and the N-channel transistor N30 in the present embodiment, the drive control unit does not necessarily have to have the same structure, and is a transistor that charges the node connected to the word line. It is sufficient that the transistor for completely turning off the transistor can be controlled according to the selection / non-selection of the word line.

[0028]

As described above, according to the level shift circuit of the present invention, the transistor for turning off the transistor for charging the node connected to the word line is connected to the voltage of the node having a heavy load connected to the word line. Since it is controlled by using the output of the drive control circuit with a light load, rather than by using it, the potential change of the word line is quickened, the frequency characteristic is improved, and the need to set the transistor size large is eliminated. By doing so, noise generated when the transistor is turned on and off can be suppressed.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a configuration of a level shift circuit according to an embodiment of the present invention.

FIG. 2 is an explanatory diagram showing changes in the potential of each node in the same level shift circuit.

FIG. 3 is a circuit diagram showing a configuration of a conventional level shift circuit.

FIG. 4 is an explanatory diagram showing changes in the potential of each node in the same level shift circuit.

[Explanation of symbols]

31 NAND circuit 28, 30, 32, 35 N-channel transistor 26, 27, 29, 33, 34 P-channel transistor N21 to N24 node 101 Address decoder 102 Switching unit 103 Level shift unit 104 Drive control unit

Claims (5)

[Claims] 1. A switching unit, one end of which is connected to an output terminal of an address decoder supplied with a first power supply voltage and which opens and closes in response to selection or non-selection of a word line, and a switching unit which is higher than the first power supply voltage. A level shift section which is supplied with a power supply voltage of 2 and has an input side connected to one end and the other end of the switching section and which outputs a signal whose level changes according to selection or non-selection of a word line, The level shift unit including a charging unit that charges the other end of the switching unit, the second power supply voltage is supplied, the input side is connected to one end and the other end of the switching unit, and the selection or non-selection of the word line is performed. A level shift circuit comprising: a drive control unit that controls the drive of the charging unit according to selection. 2. The charging means is connected between a terminal for outputting the second power supply voltage and the other end of the switching section, and the other end of the switching section is controlled in accordance with a control operation of the drive control section. The level shift circuit according to claim 1, further comprising a transistor for charging the circuit. 3. A switching unit having one end connected to an output terminal of an address decoder supplied with a first power supply voltage, a second power supply voltage terminal higher than the first power supply voltage, and a ground voltage terminal. A first P-channel transistor and a first N-channel transistor connected in series between them, and a second P-channel transistor connected between the second power supply voltage terminal and the other end of the switching element. And a level shift unit in which the gate of the first P-channel transistor is connected to the other end of the switching element, and the gate of the first N-channel transistor is connected to one end of the switching element, A third P-channel transistor and a second N-channel transistor connected in series between the second power supply voltage terminal and the ground voltage terminal.
A channel control transistor, a gate of the third P-channel transistor is connected to the other end of the switching, and a gate of the second N-channel transistor is connected to one end of the switching element; A level shift circuit comprising: 4. The switching element has a third end connected between an output terminal of the address decoder and a gate of the first P-channel transistor, and a third power supply voltage applied to the gate. 4. The level shift circuit according to claim 3, including an N-channel transistor. 5. The size of each of the third P-channel transistor and the second N-channel transistor is smaller than that of the other transistors.
The described level shift circuit.