JPH09147090A - Image processor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an image processor with which images photographed by a monitoring camera, etc., can be digitized and efficiently preserved. SOLUTION: Based on the photographed image of a monitoring camera 1, a video capture circuit 2 extracts a synchronizing signal and digitized dot information. Under the control of a control circuit 3, this dot information is successively written into the 1st area of a memory 4. Besides, under the control of the control circuit 3, the image stored in the 2nd area of the memory 4 and an image in a memory 5 are read out and compared by a comparator circuit 8. This comparing processing is performed concerning all the dot information on the image and the presence/absence of complete coincidence between images is set to an FF 14. When the images are completely coincident, the control circuit 3 increases a count value on the memory 5 just for '1', but when the images are not coincident, on the other hand, the contents in the memory 5 are transferred to an HD 15 and afterwards, the image recorded in the 2nd area of the memory 4 is written in the memory 5.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image processing apparatus for compressing and storing / reproducing an image taken by a surveillance camera or the like.

[0002]

2. Description of the Related Art Conventionally, surveillance cameras have been widely used for the purpose of building management and crime prevention of ATMs (Automatic Teller Machines) installed in banks / post offices. In view of its purpose, a surveillance camera generally takes an image of a desired place day and night. Also, the image taken by the surveillance camera is recorded on a magnetic recording medium such as a video tape. However, if the image is recorded up to the end of the video tape, it is the actual situation that a person replaces the video tape each time. Is.

[0003]

By the way, as described above, if images are continuously recorded all day long, the number of video tapes required for this is a considerable amount even if one surveillance camera is considered. Becomes Moreover, due to the nature of the surveillance camera, it is rare to see the captured image immediately,
Only at a later date will it be necessary to regenerate. Therefore, the recorded videotape is for a predetermined period, for example, 10
It is necessary to keep it in a warehouse at least for a day. Therefore, it can be easily understood that a huge number of video tapes are required to store images for all the installed surveillance cameras for a predetermined period.

Further, as described above, there is a problem that replacement of video tapes requires a great deal of labor because it involves manpower, and the labor cost required for this is not negligible. However, if one tries to automate the exchange of videotapes, it is easily inferred that the machine for achieving this will be very expensive. As described above, in the method of recording an image on a video tape as it is (in an analog manner), there arise problems such as securing a place for storing the recorded video tape and replacing the video tape.

Therefore, in order to solve these problems,
It is possible to automate the recording of the captured image by digitizing the captured image. According to this,
Images of 30 or 60 frames per second are sequentially converted into digital data and recorded in a large-capacity storage medium such as a hard disk. This seems to solve the above problem. However, the amount of data required to store images is on the order of "gigabytes", which is underestimated even when considering only one day for one surveillance camera. Therefore, a hard disk having a capacity exceeding "terabyte" is required to store the image information for all the installed surveillance cameras for the predetermined period. Realizing such a device is extremely impractical.

The present invention has been made in view of the above points, and an object thereof is to provide an image processing apparatus capable of digitizing an image taken by a surveillance camera or the like and efficiently storing it. It is in.

[0007]

In order to solve the above-mentioned problems, the present invention according to claim 1 provides a extracting means for digitizing and extracting an image from a video signal output by a video camera, and a predetermined image. First storage means for storing only the image, storage means for sequentially writing the output images of the extraction means to the first storage means, and reading means for reading the images from the first storage means in the order of writing the images. Of the images of the same continuous content, a second storage means for storing the first image thereof, a number storage means for storing number information indicating the number of consecutive images of the same content, and an image output by the reading means. And a comparison means for determining whether the images stored in the second storage means match / mismatch, an image storage means for storing the leading image together with the number-of-images information, and a determination result of the comparison means. Indicates that the images do not match, the first image of the second storage means and the number information of the number storage means are transferred to the image storage means, and then the image output by the reading means is transferred to the second image storage means. And a control means for initializing the number information of the number storage means and updating the number information of the number storage means when the comparison result of the comparison means indicates the coincidence of images. Is.

According to a second aspect of the invention, in the first aspect of the invention, the first storage means comprises a first area and a second area for storing the image,
When the storing means writes an image in the first area, the reading means reads an image from the second area, and the storing means writes an image in the second area. In this case, the reading unit reads the image from the first area.

According to a third aspect of the present invention, in the first aspect of the invention, the number storage means is provided in a memory device constituting the second storage means, and the number information of the number storage means is provided. However, it is characterized in that it is arranged adjacent to the area where the first image of the second storage means is stored. According to a fourth aspect of the invention, in the invention according to any one of the first to third aspects, an image captured by the video camera is displayed on a display based on the information stored in the image storage means. The display control means retrieves the top image and the number-of-images information from the image storage means, and calculates the shooting time required to capture the number of images corresponding to the number-of-images information. The first image is displayed on the display only during the shooting time.

According to a fifth aspect of the present invention, in the invention according to any one of the first to third aspects, an image taken by the video camera based on the information stored in the image storage means. Is displayed on the display, and the display control means takes out the leading image and the number-of-images information from the image storage means and takes a photographing time required to take an image of the number-of-images information. Is calculated, the photographing time is converted into image data, and the image data is superimposed on the leading image and displayed on the display.

[0011]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing the arrangement of an image processing apparatus according to the same embodiment. In this figure, the surveillance camera 1 is a museum, a jewelry store, a vault, A
Surveillance cameras (video cameras) deployed in places where crime prevention is required such as TM machines.
An image signal conforming to the ision System Committee) standard is output at a rate of 30 frames (or 60 frames) per second. The video capture circuit 2 detects the vertical synchronizing signal VSYNC and the horizontal synchronizing signal HSYNC from the video signal output from the surveillance camera 1, and also takes out the RGB signals, converts them into digital signals, and outputs them as image information in dot units. At that time, a clock signal CL synchronized with each dot is generated.

The control circuit 3 is based on a vertical synchronizing signal VSYNC, a horizontal synchronizing signal HSYNC, a clock signal CL, and other signals (output signals of FF11 and FF14 described later).
Address ADR for access control of the memory 4 described below
a and the write control signal RWa, and the address ADRb and the write control signal RWb for access control of the memory 5 which will be described later are also created. Then, by sending these signals to each memory, reading and writing of data in the memory is controlled. At this time, the terminal DOa and the terminal DIa are used for reading and writing the contents of the memory 4, and the terminal DOb is used for reading and writing the contents of the memory 5, respectively.
And the terminal DIb are used.

Here, the write control signals RWa and RWb
Normally, both are set to the read side (high level), and a pulse is generated only when it is necessary to write, and the pulse is set to the write side (low level). Further, the control circuit 3 is connected to the bus BUS as shown in FIG. 1 and can access the HD 15 and the like described later. The detailed functions of the circuit, including the selection signal SEL output from the circuit, will be described later in the description of the memory 4 and the memory 5 and the operation described later.

The memory 4 is a RAM (Random Access Memo).
ry) is a general memory device composed of the like. Here, an access address for this memory is given to the terminal AD. The terminals DI / DO are data terminals for inputting / outputting the contents of the access address designated by the terminal AD. These data terminals have a bit width necessary for expressing one dot of image information (hereinafter referred to as dot information) output from the video capture circuit 2. For example, RGB
Assuming 16 bits for each color of the signal,
The bit width of the data terminal is 48 bits. Furthermore, whether the terminal RW performs a read operation with respect to the memory 4,
Alternatively, it is a control terminal for designating whether to perform a write operation.

By the way, the memory 4 is configured to hold the image information taken in from the surveillance camera 1 for two images. Therefore, in the following description, an area that physically holds an image assigned to the low-order address (address 0) side of the memory 4 is called a low-order image, and a high-order address (maximum address) of the memory 4 is physically held. The area holding the image assigned to the side will be referred to as a high-order image. Here, the head address of each physical image corresponds to the upper left corner of the image, and thereafter, as the address increases, the address moves from left to right of the image and from the upper scanning line to the dot of the lower scanning line. Yuki, the last address corresponds to the lower right corner of the image. Note that the start address of the low-order image is the address "0", and the start address of the high-order image is the default value "HT".

The memory 4 is logically composed of two images, a writing logical image and an image comparing logical image. The dot information sent from the video capture circuit 2 is sequentially written in the former area. on the other hand,
The latter area is used for image comparison processing described later. Focusing on the processing of a certain dot, the processing of writing the image information captured by the surveillance camera 1 into the writing logical image and the image comparison processing using the logical image for image comparison are performed in a time division manner. These processes are performed based on the above clock signal CL synchronized with the dot information,
If the clock signal CL is low level, the dot information writing process is performed, and if the clock signal CL is high level, the image comparison process is performed.

By the way, the correspondence between the physical image and the logical image is as follows. Now, at some point in time, it is assumed that dot information has been written on the “lower image” side and image comparison processing has been performed using the “higher image” side. Then, when the processing for the image ends and the next image is processed, the dot information is written on the “higher-order image” side, and the “lower-order image” side is used for the image comparison processing. That is, by switching the correspondence between the physical image and the logical image in image units, both processes are performed in parallel.

On the other hand, the memory 5 is a memory element for storing the first appearing image when the same image is continuous, and its configuration is almost the same as that of the memory 4, but in the following points. Be different. First, the memory 4 has a two-image structure, but the memory 5 has a capacity of one image. Second, a part of the memory 5 is provided with a count area for storing the number of consecutive images. This count area indicates how many consecutive images the same as the image stored in the memory 5 are captured. Then, this area is initialized to "1" each time a new image is stored in the memory 5. Therefore, if the same image is not continuous, the value of the count area remains the initial value "1", while if 10 images are continuous, the value becomes "10".

Note that, theoretically, there is no problem in arranging the count area anywhere on the memory 5, but in the present embodiment, only one row (one scanning line) of the image is provided at the end of the memory 5. Allocating space. On the other hand, the switching circuit 6 selects either the dot information output by the video capture circuit 2 or the content of the terminal DOa of the control circuit 3 based on the selection signal SEL generated by the control circuit 3, and the terminal of the memory 4 is selected. Supply to DI. Here, if the selection signal SEL is low level, the video capture circuit 2 side is selected, and if it is high level, the control circuit 3 side is selected.

The comparison circuit 8 compares the dot information read from the terminals DO of the memory 4 and the memory 5, respectively, and outputs a high level when these dot information do not match, and outputs a low level when they match. Output level. As an example, the comparison circuit 8 performs EOR (Exclusive OR) gates (of the number corresponding to the bit width of the terminal DO) for performing an exclusive OR operation for each memory output on a bit-by-bit basis, and the logic of these operation results. It can be composed of one OR gate for summation.

The counter 9 divides the horizontal synchronizing signal HSYNC during the period of the image area, so that the image display up to the last scanning line in each image is finished,
Output a pulse to the output terminal. For example, one image is 525
In the case of being composed of scanning lines, when the horizontal synchronizing signal HSYNC is output 525 times, the pulse is output when the 525th scanning line is displayed and the 526th horizontal synchronizing signal HSYNC is output. Will be output. Therefore, in this case, the counter 9 is composed of a 526-ary counter. Further, the counter 9 outputs the vertical synchronizing signal VSYNC, so that the reset terminal R becomes high level,
The count value is cleared. Further, reference numeral 10 is an OR gate.

The FF 11 is a set-reset type flip-flop, where S is a set terminal, R is a reset terminal, and Q is an output terminal. FF11 is a vertical synchronization signal V
Set when SYNC goes high. Further, the reset terminal R is reset when the pulse is output to the output terminal of the counter 9 (in other words, immediately before the display of the image is finished and the count area is accessed), and the reset terminal R is reset. It is also reset when the reset signal RST output when the power is turned on becomes valid. Then, at the output terminal Q of the FF 11, a signal for determining the timing for comparing the dot information is obtained. The AND gate 12 controls the output signal of the comparison circuit 8 with the timing signal and the clock signal CL output from the FF 11.

The FF 13 is a set-reset type flip-flop, which is set when the output signal of the AND gate 12 becomes high level, and is reset when the vertical synchronizing signal VSYNC or the reset signal RST is transmitted.
Therefore, at the output terminal Q of the FF 13, a signal indicating whether or not the contents of the memory 4 and the memory 5 are completely matched,
It will be obtained in image units. In other words, for one image, if the contents of the memory 4 and the memory 5 do not match even one dot, a high level is output from the output terminal Q,
Low level is output only when all dots match. As will be described later, this output signal is used by the control circuit 3 to determine whether the images match.

The FF 14 is a D type flip-flop connected to the clock terminal T by using the vertical synchronizing signal VSYNC as a clock, and the FF 13 fetched from the input terminal D.
The output signal Q is delayed by one image and output from the output terminal Q. As will be described later, this output signal is used by the control circuit 3 to perform processing when the images do not match. The HD (hard disk) 15 is an external storage device for storing the image information sent from the control circuit 3, and the image taken in from the surveillance camera 1 is compressed and stored as described later. An HDC (hard disk controller) 16 is a well-known control circuit for controlling the HD 15, and has a disk cache built therein for speeding up.

On the other hand, on the bus BUS to which the control circuit 3 is connected, in addition to the HDC 16, a CPU (central processing unit) 17, a ROM (Read Only Memory) 18, a RAM
A (Random Access Memory) 19, a display control circuit 20, and an operation panel 22 are connected. CPU17 is HD1
The ROM 18 stores a control program executed by the CPU 17, which is a processing device for reproducing the compressed image information stored in FIG. RAM 19 is a CPU
A working memory 17 is used. Furthermore, the display control circuit 20 has a built-in video RAM (not shown),
An image is displayed on the display 21 based on the display data sent from the CPU 17. Furthermore, the operation panel 2
Reference numeral 2 denotes a circuit for the administrator of the apparatus to control the start / stop of shooting and to give an instruction to reproduce the image stored in the HD 15.

Next, the operation of the image processing apparatus having the above configuration will be described. First, when the power of this device is turned on, the reset signal RST becomes high level, and the FF11 and FF
13 is reset. At this point of time, the contents of the memories 4 and 5 are indefinite, so the control circuit 3 performs the initialization processing of these memories as follows.

First, in order to initialize the memory 4, the address ADRa is set to "0" and the terminal DOa is set to a predetermined initialization pattern (for example, all bits are zero). Next, the selection signal SEL is set to high level to switch the switching circuit 6 to the control circuit 3 side. Then, the write control signal R
A write pulse is sent to Wa to write the initialization pattern to the address "0" of the memory 4. After that, the control circuit 3 increments the address ADRa by 1 and writes the initialization pattern up to the final address of the memory 4.

Next, in order to initialize the memory 5, the address ADRb is set to "0" and the write control signal RW is set.
A write pulse is sent to b to initialize the address "0" of the memory 5. After that, the address ADRb is set to 1
The initialization process is performed up to the final address of the memory 5 while incrementing each. After this processing, the address AD
If Rb is incremented by 1, the address ADRb
Indicates the count area. Therefore, the control circuit 3
Writes "1" which is the initial value of the number of continuous images in the count area. When the initialization process is completed in this way, the control circuit 3 sets the selection signal SEL to the low level and switches the switching circuit 6 to the video capture circuit 2 side.

As described above, the contents of the memories 4 and 5 are all initialized to the same pattern, which is shown in FIG. 2 (a). The figure shows that the image “B” is stored in the high-order image of the memory 4, the image “A” is stored in the memory 5, and the value of the count area of the memory 5 is “1”. The contents of the image "A" and the image "B" are actually the same, but different symbols are attached for convenience of explanation. In addition, the low-order image in the memory 4 is immediately rewritten with the dot information of the surveillance camera 1,
It is left blank in the figure. Further, for such a reason, the initialization may be started from the head address "HT" of the high-order image without actually performing the initialization on the low-order image side.

Next, when photographing is started, the surveillance camera 1 outputs the photographed image as an NTSC signal. This video signal output is captured by the video capture circuit 2, and the vertical synchronizing signal VSYNC, the horizontal synchronizing signal HSYNC, and the clock signal CL.
Are extracted, and dot information starts to be output in synchronization with the clock signal CL. After that, when the vertical synchronization signal VSYNC is output at time t1 shown in the time chart of FIG.
F11 is set and its output terminal Q becomes high level. As a result, the output of the comparison circuit 8 becomes the AND gate 12
Then, the image comparison processing becomes possible. On the other hand, since the FF13 is still in the reset state, the FF1 is activated at the rising edge of the vertical synchronization signal VSYNC.
The output terminal Q of 4 becomes low level. At this point, the counter 9 is reset and the count value is cleared.

Next, when the horizontal synchronizing signal HSYNC is output at time t2, the counter 9 counts up by one. After this, the video capture circuit 2 outputs the clock signal C
The output starts from the dot information of the first image in synchronization with L. Next, when the clock signal CL becomes high level at time t3, the control circuit 3 sets the address ADRa to the address "HT" which is the head of the high-order image and the address ADRb to the address "0". As a result, “H” in the memory 4
The dot information stored in the address “T” and the dot information stored in the address “0” of the memory 5 are read out. When the comparison circuit 8 compares these dot information, any dot information remains the initialization pattern, so the comparison circuit 8 outputs a low level. Therefore, the state of the FF 13 remains unchanged.

After that, when the clock signal CL becomes low level at time t4, the control circuit 3 sets the address ADRa to "0" and sends a write pulse to the write control signal RWa to store the first dot information in the memory. "0" of 4
Write to address. Thus, at this point, the low-order image is used for writing dot information, and the image comparison process is performed using the high-order image.

Next, when the clock signal CL becomes high level again at the time t5, the control circuit 3 increments the values of the address ADRa and the address ADRb by 1 from the values at the time t3, respectively, to "HT + 1" and "HT + 1". 1 "
And the second dot information in the memory 4 is compared with the second dot information in the memory 5. In this case as well, since the dot information of both is the same, the state of the FF 13 does not change. Further, when the clock signal CL becomes low level again at time t6, the control circuit 3 changes the value of the address ADRa to
The value at time t4 is incremented by 1 and the second dot information output by the video capture circuit 2 is written to the address "1" of the memory 4.

As described above, while the clock signal CL is at the high level, the high-order image in the memory 4 and the image in the memory 5 are compared dot by dot in the ascending order of the addresses. In this case, the contents of both of these images match, so
The FF 13 remains reset even after the final dot information is compared. On the other hand, while the clock signal CL is at the low level, the dot information of the video capture circuit 2 is sequentially written in the lower image area of the memory 4.
On the other hand, the counter 9 is incremented by "1" each time the horizontal synchronizing signal HSYNC is output.

In this way, as shown in FIG. 2B, the lower image in the memory 4 becomes the image "C". here,
The right arrow in the figure indicates that the image is newly written. Then, at the time t7, when the "number of scanning lines in the image area + 1" horizontal synchronizing signal HSYNC is output, the counter 9 generates a pulse to the output terminal, and FF
11 is reset. As a result, the AND gate 12
The output of is always low level to prevent the FF 13 from being set by mistake. Next, the control circuit 3 outputs FF1.
The level of the output terminal Q of No. 3 is judged, but here it is a low level indicating that both images match. Therefore, the control circuit 3 performs a process of incrementing the count area on the memory 5 by 1 as follows.

Now, the address ADRb points to the end of the dot information area secured on the memory 5. Therefore, if the control circuit 3 increments the address ADRb by 1, the address ADRb points to the count area, and the content at the beginning of the count area is read from the memory 5. Therefore, the control circuit 3 increments the value of the read count area by 1, outputs the result "2" to the terminal DOa, and writes it back to the count area. In this way, the contents of the memory are shown in FIG.
It becomes as shown in. Note that the AND gate 12 is gated by the output of the FF 11 during the update processing of the count area, and the FF 1
3 is set so that it is not set by mistake.

Next, when the vertical synchronizing signal VSYNC for the second image "D" is output at time t8, the vertical synchronizing signal VSYNC is generated.
At the rising edge of, the output of FF13 is taken in by FF14 and the output terminal Q thereof is maintained at a low level. At this time, FF11 is set and FF13 is reset. As a result, the output of the AND gate 12 is maintained at the low level. In addition, when FF13 is reset and F
Data acquisition by F14 is performed at the same time.
Since the effect of the reset of F13 appears at the output terminal Q after the delay of the propagation time of the circuit, FF14
Can correctly capture the output of the FF 13.

When the vertical synchronizing signal VSYNC is issued, the control circuit 3 switches the correspondence between the physical image and the logical image. That is, the low-order image side where the dot information has been written until now is used for the image comparison processing, and the high-order image side used for the image comparison processing is used for writing the dot information. Here, in the following description, the image “C” written on the low-order image side of the memory 4 as described above and the image “B” on the high-order image side are the dot information of the first to 100th dots. Are all in agreement, and inconsistency occurs from the 101st dot information.

Next, when the horizontal synchronizing signal HSYNC is output at time t9, the counter 9 is again incremented from "0". After that, at time t10, the control circuit 3 sets both the address ADRa and the address ADRb to “0”, reads the head dot information of the low-order image of the memory 4 and the head dot information of the memory 5, and the comparison circuit 8 Compare. As described above, since these dot information pieces match each other, the FF 13 remains reset. Next, at time t11, the control circuit 3 sets the address ADRa to "HT" which is the head of the high-order image in the memory 4 and writes the first dot information to the address "HT".

In this way, contrary to the first image processing, the memory 4 is operated while the clock signal CL is at the high level.
The low-order image and the memory 5 are compared, and dot information is sequentially written to the high-order image side of the memory 4 while the clock signal CL is at the low level. Then, as described above, since the first to 100th dot information match, the time t1 when the processing of 100 pieces of dot information ends.
Up to 2, the FF 13 is in a reset state. However, at time t12, when the contents of the address 100 of the memory 4 and the contents of the address 100 of the memory 5 are compared, they do not match. As a result, the output of the AND gate 12 becomes high level, and the FF 13 is set.

Even after this, the memory 4 and the memory 5
The dot information of is compared one by one until the last dot information is processed. However, in the comparison process for a certain image, once the FF 13 is set, the subsequent comparison result does not affect the state of the FF 13, and the FF 13 remains set. The state of the memory at the time when the above processing is completed is shown in FIG. As shown in the figure, the new image “D” is stored in the high-level image of the memory 4.

Next, at time t13, when the "number of scanning lines in the image area + 1" horizontal synchronization signal HSYNC in the second image processing is output, the control circuit 3 determines the level of the output terminal Q of the FF13. . In this case, the output of the FF 13 is at a high level, which means that a mismatch is detected in both images. Therefore, the control circuit 3 does not perform the increment processing of the count area on the memory 5. Next, at time t14, the vertical synchronization signal V for the third image
When SYNC comes out, FF14 takes in the state of FF13,
The output terminal Q becomes high level. The control circuit 3 catches this rising, and thereafter, in addition to performing the process of writing the third image “E” into the lower image of the memory 4, performs the following process. That is, the contents of the memory 5 are first transferred to the HD 15, and subsequently, the image of the memory 4 is transferred to the memory 5.

Therefore, the operation of the present apparatus will be described below focusing on these processes. First, at time t15, the address “HT” of the memory 4 and the memory 5
The address "0" of is read, but at that time, the control circuit 3
Captures both of these dot information inside the circuit. Next, the first dot information read out from the memory 5 side is sent to the HDC 16 and an instruction to write the dot information to the HD 15 is issued. HDC16 which received this instruction
Buffers the dot information sequentially sent from the control circuit 3 thereafter by a predetermined amount in the disk cache, and then collectively writes them to the HD 15.

Next, at the time t16, when writing the dot information from the video capture circuit 2 to the low-order image side of the memory 4, the control circuit 3 sets "0" to the address ADRb and fetches it inside. The dot information of the address "HT" in the memory 4 is put on the terminal DOa and is written in the address "0" of the memory 5. After that, the addresses ADRa and ADRb are sequentially counted up, and the process of writing the contents of the memory 5 to the HD 15 and the subsequent process of transferring from the memory 4 to the memory 5 are executed in dot units. Go on.

When the above processing is completed for all dot information, the control circuit 3 (not shown in the time chart of FIG. 3) counts the memory 5 within the period when the clock signal CL is at the low level. The contents of the area are read and written in the HD 15. As a result, all the contents of the memory 5 are recorded in the HD 15.
After that, the control circuit 3 writes the initial value “1” in the count area of the memory 5, and initializes the number of continuous images of the images newly transferred from the memory 4 to “1”. By this processing, the transfer processing from the memory 4 to the memory 5 is also completed.

The state of the memory at this time is shown in FIG. As shown in the figure, the contents of the HD 15 are updated, and the image “A” is recorded therein. Also, a new image "E" is written on the lower side of the memory 4, and the memory 5 is replaced by the image "D". In addition, memory 5
The count area of is initialized to "1". After that, the above-described processing is repeated. That is, it is inspected whether the image captured from the surveillance camera 1 into the memory 4 completely matches the image in the memory 5. Then, if the two images completely match each other, the value of the count area provided on the memory 5 is incremented by 1 as a part of the process for the image. On the other hand, if there is a disagreement between the two images even with one dot, the contents of the memory 5 are transferred to the HD 15 and then the contents of the memory 4 are transferred to the memory 5 in the process for the next image of the images. .

Therefore, assuming that the image "D" in FIG. 2 (e) does not match the image "E", in the processing of the next image, after the image "D" is transferred to the HD 15,
The image “E” is moved to the memory 5, and the image “F” is newly written on the high-order image side of the memory 4, and the memory and the HD 1
5 is as shown in FIG. 2 (f). Further, if the next image is processed on the assumption that the image “E” does not match the image “F”, the state becomes as shown in FIG. As shown in the figure, images “A”, “D”, “E” are displayed on the HD 15.
Are sequentially recorded, a new image “G” is written on the lower image side of the memory 4, and the content of the memory 5 is replaced with the image “F”. In this way, the above-described processing is performed until the administrator of this apparatus gives an instruction to end the capture from the surveillance camera 1 from the operation panel 22 and the instruction is transmitted to the control circuit 3 via the CPU 17. It is done continuously.

In the above manner, most images will be sequentially recorded in the HD 15 in a place where people come and go frequently, such as during the daytime. However, if there is almost no people coming in and going out at night, or if an originally unattended room is to be monitored, the captured image is not written to the HD 15 except for the first image, and the counter of the memory 5 is not used. Only the value in the area will count up. Then, occasionally, the recording on the HD 15 is performed only for a short time when the guards and the like make a patrol.

Therefore, for example, if there is no abnormality during 10 hours at night and there is no change in the image, then 30 [image / sec] × {3600 × 10} [sec] = 108.
What used to require a memory area of only ten thousand [images] is now only one image and a counter area. In addition, a surveillance camera is often installed in a place where no one usually enters, and in such a case, it is sufficiently possible that one image is enough for one week or more. .

Next, the operation of reproducing the compressed image information stored in the HD 15 will be described. First, the case of performing real-time display will be described.
In this case, the CPU 17 gives an instruction to the HDC 16 to read the dot information regarding the first image from the HD 15. As a result, the dot information is transferred from the HD 15 to the RAM 19. This transfer processing is performed by the CPU 17
Will communicate with the HDC 16 while performing a dedicated DM.
An A (Direct Memory Access) controller or the like may be provided for processing. When the transfer of one image is completed, the CP
U17 transfers this image information to the video RAM in the display control circuit 20. As a result, the display control circuit 20 displays the first image on the display 21 according to the contents of the video RAM.

On the other hand, the CPU 17 takes out the counter area provided at the end of the read image information and checks how many pieces of this image information are continuous. Then, the value of the counter area is multiplied by the image capturing time interval (1/30 seconds in this embodiment) to determine the image display time. For example, if the value of the counter area is 15 sheets, (1
/30)×15=0.5 seconds This image is continuously displayed. That is, during 0.5 seconds, the CPU 17 does nothing regarding the image reproduction processing. And 0.
When 5 seconds have elapsed, the CPU 17 continuously takes out the next image from the HD 15 and repeats the same processing as above. In this way, the captured image can be reproduced from the compressed image information recorded on the HD 15.

As a method other than the real time display, it is possible to display the elapsed time together. According to this method, the CPU 17 first transfers the image information from the HD 15 to 1
Only the number of sheets is taken out on the RAM 19. Since the taken-out image is the first one, the elapsed time from the start of shooting is 0 seconds for this image. So, in this image information,
The display of "0 seconds" which is the elapsed time of the image is superimposed and sent to the display control circuit 20 to be displayed on the display 21.

Next, the CPU 17 determines the HD1 based on the value of the counter area included in the image information just fetched.
The elapsed time is calculated for the second image to be retrieved next from 5. That is, if the value of the counter area of the first image just taken out is 15, for example, 2
It can be seen that the first image is an image 0.5 seconds after the start of shooting. Therefore, the CPU 17 changes the HD 15 to 2
After the image information of the first sheet is taken out, the elapsed time “0.5 seconds” is superimposed on this image information and displayed on the display 21. After that, the CPU 17 integrates the elapsed time from the start of shooting based on the value of the counter area recorded on the image information extracted from the HD 15, and displays it together with the image extracted from the HD 15.

In this way, when the same image is continuously displayed, only the first image can be displayed together with the elapsed time from the start of shooting, and the subsequent display of the same image can be omitted. . That is, by displaying only the moving image together with the elapsed time, the image can be reproduced in a very short time as compared with the fast-forwarding of the video tape.

As can be seen from FIG. 2 (f) and the like, according to the above-described embodiment, it is understood that the image “C” is not written in the HD 15. In general, according to this embodiment, the step of transitioning from a state in which the same images are continuous to a state in which the images are inconsistent (in the case of FIG. 2,
At the time of transition from (d) to (e)), the first image in which a change has occurred is lost. This is because the structure of the memory 4 is the minimum structure that holds only two images. However, even if only the first image is missing when a change occurs in the image, there is almost no problem because the captured image does not change rapidly. Rather, it can be said that the effect of cost reduction by simplifying the memory configuration and reducing the quantity is much greater.

By the way, in order to prevent the above-mentioned image loss, a second embodiment described below can be considered. As can be seen from the above description, in the image loss in the first embodiment, the image “C” in the memory 4 has not yet been written in the memory 5 when shifting from FIG. 2D to FIG. 2E. This is due to the fact that the correspondence between the logical image and the physical image in the memory 4 is switched.

However, in the above-described embodiment, the device operates based on the timing when one cycle of the clock signal CL is divided into two. That is, the timing is determined only by whether the level of the clock signal CL is the high level or the low level, and the memory 4 (or the memory 5)
In combination with the inability to process the read operation and the write operation in parallel, it is not possible to realize the above-described operation while solving the image loss.

Therefore, in the present embodiment, the clock signal C
It is assumed that one cycle of L is divided into three timings, and even if the correspondence relationship between the logical image and the physical image in the memory 4 is exchanged, the logical image before the exchange is accessed. Now, focusing on the case of shifting from FIG. 2D to FIG. 2E and considering the fitting to this, the operation of the apparatus in the present embodiment is as follows.

First, at the first timing, the dot information of the image "C" is fetched from the memory 4 into the control circuit 3. The dot information of the image "A" is read from the memory 5 and H is read.
The process of transferring to D15 is performed. Next, at the second timing, the process of writing the dot information of the image “C” captured at the first timing in the memory 5 is performed by converting the dot information of the image “E” output from the video capture circuit 2 into the image “C”. Is written in the area of the memory 4 in which was written.

Next, at the third timing, the process of reading the dot information of the image "D" from the memory 4, the process of reading the dot information of the image "C" from the memory 5, the image "D" and the image read in the above and The process of comparing the dot information of “C” is performed. Note that the processing related to updating the count area is the same as that in the first embodiment, and is omitted in the above description.

On the other hand, if there is no discrepancy in the images and the count area is updated, H at the first timing
This is different from the process in the case where there is a discrepancy between images in that the transfer process () to D15 and the write process () to the memory 5 at the second timing are not performed.
Note that the fetching process () of the memory 4 at the first timing does not need to be performed because it does not affect the operation. By doing so, the control of the control circuit 3 becomes somewhat complicated, the timing conditions required for the circuit become somewhat strict, and it is necessary to add a circuit for generating the above timing. Except for this, it is similar to the first embodiment.

In the above embodiment, for convenience of explanation, the memory 4 and the memory 5 are turned on at the time of power-on.
It was decided to initialize the contents of. However, in practice, except for the initialization processing of the count area of the memory 5, there is no problem even if such processing is not performed. If the initialization process is not performed, the contents of these memories are indefinite, and the image comparison process is performed with the indefinite contents and the HD
Written to 15. Therefore, when the power is turned on, the contents of the logical image for image comparison in the memory 4 and the memory 5 are compared.
Will be recorded in the HD 15 as a meaningless image, but it is clear that this has no problem. Further, in the above-described embodiment, the number of continuous images is provided on the memory 5, but it may be provided by a well-known counter circuit instead of being provided on the memory 5.

[0063]

As described above, according to the first aspect of the invention, the images from the video camera are written in the first storage means, and the images are read out in the order of writing to read the images in the second storage means. If the images do not match, the first image and the number information are transferred to the image storage means, the image in the first storage means is written in the second storage means, the number information is initialized, and the other image If the numbers match, only the number information is updated, so if the same image continues, only the first image is stored in the image storage means, and when monitoring an unmanned room / corridor, etc. Since it is not necessary to continuously capture meaningless images, there is an effect that the conventional problem that a recording medium such as a film or a hard disk is largely consumed can be solved.

According to the invention of claim 2, the first
Since the storage means is composed of two areas, and the storage means and the reading means use these two areas exclusively and alternately, the writing and reading of the image to and from the first storage means are performed in parallel. As a result, the processing can be performed, and the effect that the compression processing of the image captured by the video camera can be speeded up is obtained.

According to the third aspect of the invention, the number-of-images storage means is arranged in the same memory device as the second storage means, and the leading image and the number-of-images information are arranged continuously in the memory device. It is possible to handle the number-of-sheets information integrally with the leading image. Therefore, for example, when the images do not match, the circuit configuration for storing the leading image and the number-of-images information in the image compression means can be simplified.

According to the fourth aspect of the present invention, the leading image and the number-of-images information are taken out from the image storage means, the image-taking time required to image the number-of-images information is calculated, and the image-taking time is calculated. Since the top image is displayed only during the period, it is possible to obtain the effect that the image captured by the video camera can be reproduced in real time display based on the compressed image.

According to the fifth aspect of the invention, the leading image and the number-of-images information are taken out from the image storage means, the image-taking time required to image the number of images corresponding to the number-of-images information is calculated, and the obtained image is obtained. Since the time is converted to image data and is displayed so as to be superimposed on the first image, only the images that show changes in content will be displayed along with the elapsed time from the start of shooting. Since the display of the image is omitted, it is possible to obtain the effect that the image can be reproduced in a very short time as compared with the fast-forwarding of the video tape.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of an image processing apparatus according to an embodiment of the present invention.

FIG. 2 is a diagram showing a transition of recorded contents of a memory 4, a memory 5, and an HD 15 in an operation process of the device.

FIG. 3 is a time chart for explaining the operation of the device.

[Explanation of symbols]

1 ... Surveillance camera, 2 ... Video capture circuit, 3 ... Control circuit, 4, 5 ... Memory, 8 ... Comparison circuit, 9 ... Counter,
11, 13, 14 ... FF (flip-flop), 15 ...
HD (hard disk), 16 ... HDC (hard disk controller), 17 ... CPU, 18 ... ROM, 19
... RAM, 20 ... Display control circuit, 21 ... Display,
22 ... Operation panel

Claims (5)

[Claims] 1. An extracting means for digitizing and extracting an image from a video signal output from a video camera, a first storing means for storing a predetermined image of the image, and an output image of the extracting means for the first image. Storage means for sequentially writing to the first storage means, reading means for reading out the images from the first storage means in the order in which the images are written, second storage means for storing the first image of the continuous images having the same content And a number storage means for storing number information indicating the number of consecutive images having the same content, and a comparison means for determining whether the image output by the reading means matches the image stored in the second storage means. And an image storage unit that stores the top image together with the number-of-images information, and if the determination result of the comparison unit indicates that the images do not match,
The leading image of the second storage means and the number information of the number storage means are transferred to the image storage means, and then the image output by the reading means is written to the second storage means and the number storage is performed. An image processing apparatus comprising: control means for initializing the number information of the means, and updating the number information of the number storage means when the comparison result of the comparing means indicates image coincidence. 2. The first storage means comprises a first area and a second area for storing the image, and when the storage means writes an image in the first area, When the reading means reads an image from the second area and the storage means writes an image to the second area, the reading means reads an image from the first area. The image processing apparatus according to claim 1, which is performed. 3. The number storage means is provided in a memory device constituting the second storage means, and the number information of the number storage means is an area in which a leading image of the second storage means is stored. The image processing apparatus according to claim 1, wherein the image processing apparatus is disposed adjacent to the. 4. The display control means reproduces an image captured by the video camera on a display based on the information stored in the image storage means, the display control means comprising: It is characterized in that the leading image and the number-of-images information are taken out, a photographing time required to photograph an image of the number-of-images information is calculated, and the leading image is displayed on the display only during the photographing time. The image processing apparatus according to claim 1. 5. A display control means for reproducing an image captured by the video camera on a display based on the information stored in the image storage means, the display control means comprising: The leading image and the number-of-images information are taken out, the photographing time required to photograph the image corresponding to the number-of-images information is calculated, the photographing time is converted into image data, and the data is superimposed on the leading image and displayed on the display. 4. The display according to claim 1, wherein the display is made.
The image processing apparatus according to any one of 1.