JPH09147009A - Crosstalk delay deciding method and parallel wiring length limiting method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To perform the desivation of parallel wiring length limit value and the delay calculation with high accuracy by adding the adjacency length to the crosstalk delay elements in the delay calculation. SOLUTION: A erecti linear wiring (noticing path) S1 is prepared between a source gate 201 and a sink gate 202, and a wiring (adjacent path) S2 that is parallel to a part of the wiring S1 is prepared between a source gate 203 and a sink gate 204. The crosstalk delay value caused by an adjacent parallel wiring consisting of both paths S1 and S2 is calculated by simulation with the adjacency length Ls covering from the output point of the gate 201 of the path S1 through the start point of the adjacent parallel wiring and the parallel wiring length Lp of the adjacent parallel wiring as the parameter, and stored in a delay table while being made to correspond to the parameter. Then the object path S1 is selected, and the crosstalk delay value is found from the delay table using the adjacency length Ls of the path S1 and the parallel wiring length Lp.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an automatic wiring method for a semiconductor integrated circuit (hereinafter referred to as an LSI), and more particularly to a technique effective when applied to arithmetic processing of crosstalk delay.

[0002]

2. Description of the Related Art In a layout and wiring process of an LSI, a cell whose layout is designed in advance is used to arrange a cell on a semiconductor substrate and wire between cell terminals. The cell layout is generated manually or through an automatic program based on a circuit diagram designed in advance. In the gate array method, the transistor basic circuit is regularly arranged in the matrix direction,
In addition, this is a method in which fixedly arranged chips are commonly used in many types of random logic LSIs. A wafer whose substrate process is completed by using a mask common to each component is used, and a wiring mask different for each component is used. Can be used to provide LSIs with different functions. Not only can the sample formation period be shortened by standardizing the wafer process in the middle, but it is also easy to respond to types that require less even at the time of mass production and to adjust the mass productivity for types that have many required fluctuations. It is said that The chip layout structure simplified in the matrix direction facilitates automatic wiring to the logic element. In such an LSI design by the gate array method, as shown in FIG. 23, first, logic design is performed (2301), and then automatic wiring is performed by design automation (DA) or the like (2302). Next, parallel wiring length limitation is performed to limit adjacent parallel wiring as much as possible in order to reduce the influence of crosstalk delay on the wiring pattern obtained by automatic wiring (230
3) If the adjacent parallel wiring is longer than the limit value, automatic wiring or manual wiring processing is performed again. When the number of adjacent parallel wirings is equal to or smaller than the limit value, the process proceeds to the next process, and delay calculation is performed for each logic gate and wiring as a logic design and wiring verification (2304). In this delay calculation, the wiring is estimated as the load capacitance, and based on the obtained delay value, verification of whether the above logic design or the above automatic wiring is appropriate is performed. For example, it is verified (2305) whether the delay of the path satisfies the target cycle. In this verification, if the delay value for each logic gate and wiring is within the allowable range, it is judged that the above logic design and automatic wiring were properly performed, but if the obtained delay value is allowable. If the value deviates from the range, it is determined that the logical design and automatic wiring are not appropriate, and the logical design and automatic wiring are performed again. In this way, by performing verification based on the delay calculation result, the logic design and automatic wiring are optimized.

[0003]

With the miniaturization of LSIs, the wiring width becomes smaller and the wiring resistance also increases. For example, ECL (emitter coupled logic) LSI
In the above, the conventional resistance value has increased from about 10 to 15 Ω / mm to 50 Ω / mm or more. Therefore, the length of the wiring is also one of the delay elements. FIG. 3A shows an example in which adjacent parallel wirings are provided on the target path. Here, the distance from the source gate of interest to the adjacent parallel wiring in which the crosstalk delay occurs is the length Ls between adjacent wires.
And the length of the adjacent parallel wiring is represented by the parallel wiring length Lp. FIG. 3B shows a correlation diagram between the adjacent length Ls and the parallel wiring length Lp of the crosstalk delay variation Δtpd [ps]. According to (B) of the same figure, it can be seen that the influence of the impedance of the source gate of interest is weakened and the influence of crosstalk is increased as the position of the adjacent parallel wiring is separated from the source gate of interest.
Therefore, it is understood that the parallel wiring length limit value corresponding to the crosstalk generation amount cannot be set only by using the adjacent parallel wiring length Lp as a parameter in the calculation of the delay due to the crosstalk. Therefore, the present inventor has found the necessity of adding an element having the adjacent length Ls to the delay calculation due to crosstalk.

An object of the present invention is to add the inter-adjacent length Ls to the element of the crosstalk delay in the delay calculation, and to derive the parallel wiring length limit value and the delay calculation with high accuracy.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0006]

The following is a brief description of an outline of a typical invention among the inventions disclosed in the present application.

That is, the crosstalk delay value by the adjacent parallel wiring formed by the target path formed by one source gate and one sink gate and the adjacent path formed by one source gate and one sink gate is
Obtained by simulation using the inter-adjacent length, which is the length from the output point of the source gate of the path of interest to the start point of the adjacent parallel wiring, and the parallel wiring length, which is the length of the adjacent parallel wiring, as parameters. The step of forming a delay table for storing the crosstalk delay value in association with the above parameters, the step of selecting the target path formed with the adjacent parallel wiring from which the crosstalk delay value is to be extracted, The crosstalk delay determining method is configured to include the step of obtaining the crosstalk delay value from the delay table using the adjacent length of the target path and the parallel wiring length. The delay table can be formed for each combination of the driver path of the source gate forming the adjacent path and the source gate forming the adjacent path and the wiring shape. In the crosstalk delay determining method, attention is paid when the adjacent parallel wiring is formed by a focused path formed by one source gate and one sink gate and a plurality of adjacent paths formed by one source gate and one sink gate. The crosstalk delay value of the path is divided into a combination of the path of interest and one adjacent path, and can be determined by the crosstalk delay value determined from the delay table corresponding to each combination. In the crosstalk delay determination method, when a plurality of adjacent parallel wirings are formed by one adjacent path, the parallel wiring length may be a total value of the lengths of the plurality of adjacent parallel wirings.

Further, the permissible value of the crosstalk delay value by the adjacent parallel wiring formed by the target path formed by one source gate and one sink gate and the adjacent path formed by one source gate and one sink gate is obtained. , From the upper limit of the permissible value to the upper limit of the length of the adjacent parallel wiring which can be arranged by the driver gate of the source gate of the target path, from the output point of the source gate of the target path to the start point of the adjacent parallel wiring. A step of forming a function table that gives a function that specifies the length of adjacent paths as a parameter, a step of selecting a path of interest from which the upper limit value is to be extracted, and an adjacency length of the selected path of interest And the driver gate of the source gate of the path of interest are extracted. Selecting a function, by substituting the adjacent while length of the extracted to the selected function, constituting the parallel wiring length limiting method and a step of obtaining the upper limit value of the parallel wiring length. In the method for limiting the length of adjacent parallel wirings, in the case where the adjacent parallel wirings are formed by a target path composed of one source gate and one sink gate and a plurality of adjacent paths composed of one source gate and one sink gate. The upper limit value of the length of the adjacent parallel wiring of the target path is divided into the combination of the target path and one adjacent path, and can be determined by the function selected from the function table corresponding to each combination. In the adjacent parallel wiring length limiting method, when a plurality of the adjacent parallel wirings are formed by one adjacent path,
The upper limit value of the length of the parallel wiring can be a total value of the lengths of a plurality of adjacent parallel wirings.

According to the above-mentioned means, the crosstalk delay value by the adjacent parallel wiring formed by the target path and the adjacent path is determined by the crosstalk delay determining method using the inter-adjacent length and the parallel wiring length as parameters. Can be obtained from the delay table set for each combination of the target path and the adjacent path. The delay table is uniquely determined according to the hardware configuration of the target path composed of one source gate and one sink gate and the adjacent path composed of one source gate and one sink gate. Therefore, the delay table to be used is determined by designating the target path and the adjacent path that form the adjacent parallel wiring that is the target of the crosstalk delay determination. Examples of the above-mentioned hardware configuration include the wiring shape of the driver gate of the source gate forming the adjacent parallel wiring, the thickness of the wiring, the wiring pitch, and the like. When the number of adjacent paths is plural, the delay table set according to the combination of the target path and each of the adjacent paths is used, and the target path and the adjacent path are configured to have a one-to-one correspondence with each other. The value can be calculated. Further, when a plurality of the adjacent parallel wirings are formed by one adjacent path, the parallel wiring length can be a total value of the lengths of the plurality of adjacent parallel wirings, and the value can be used as a parameter of the delay table.

Further, according to the parallel wiring length limiting method, the upper limit of the length of the adjacent parallel wiring formed by the target path and the adjacent path is stored in the function table, and the function selected for each driver utility of the target path. Can be obtained by The selected function also takes into consideration the crosstalk delay value that is the allowable upper limit of the target path, and by substituting the adjacent length of the target path, the length of the adjacent parallel wiring that gives the allowable upper limit value to the target path. It is possible to obtain the upper limit of the height. In the parallel wiring length limiting method, when the adjacent path is composed of a plurality of adjacent paths, a function set according to the path of interest is used to configure the path of interest and the adjacent path to have a one-to-one correspondence with the length of the adjacent parallel wire. It is possible to obtain the upper limit of the height. Further, in the parallel wiring length limiting method, when a plurality of adjacent parallel wirings are formed by one adjacent path,
The upper limit value of the length of the adjacent parallel wiring can be the total value of the lengths of the plurality of adjacent parallel wirings.

[0011]

BEST MODE FOR CARRYING OUT THE INVENTION In designing an LSI, a workstation or the like first performs a logical design of the LSI in accordance with design specifications, and automatic wiring is performed based on the logical design, and individual logic gates and wirings connected to the logic gates. Is calculated. In the above-mentioned automatic wiring, the length of the parallel wiring, which is the cause of the crosstalk delay, is controlled to be within a predetermined allowable delay range. The influence of delay due to crosstalk occurs when signal wirings are arranged adjacent to each other in parallel (hereinafter, referred to as adjacent parallel wirings) and the timings at which the signals change overlap. For example, when the rising timing of the signal and the rising timing of the signal overlap, the speed of both signals increases (a negative delay occurs), and when the rising timing of the signal and the falling timing of the signal overlap. The speed of both signals decreases (plus delay occurs), and the speed of both signals increases (negative delay occurs) when the signal fall timing and the signal fall timing overlap. . The delay due to crosstalk is not caused by process variations, power supply voltage variations, or temperature variations, and is uniquely determined by the timing of signals flowing between paths in which adjacent parallel wirings are formed.

FIG. 2 shows an automatic example wiring configuration diagram having the above-mentioned adjacent parallel wiring. According to the figure, a linear wiring S1 is arranged between the gates of the source gate 201 and the sink gate 202, and between the source gate 203 and the sink gate 204, a part of the wiring S1 is adjacent and parallel. The wiring S2 is arranged in a line. Here, the name of each part of the wiring configuration shown in FIG. 2 is defined.
From the input of the source gate 201 to the sink gate 202
The signal path (micropath) up to the input of is the unit of interest for calculating the crosstalk delay value and is called the path of interest. In the path of interest, the source gate 201 is called the source gate of interest, and the sink gate 202 is called the sink gate of interest.
The path of interest can be composed of a plurality of micropaths. A micropath in which adjacent parallel wiring is connected to the wiring of the path of interest is called an adjacent path or an adjacent net. The source gate 203 and the sink gate 204, which form the adjacent path, are called adjacent source gates and the sink gate 204, respectively. The length of the adjacent parallel wiring that gives the crosstalk delay to the focused path by arranging the wiring S1 of the focused path and the wiring S2 of the adjacent path in parallel is called a parallel wiring length Lp. The length from the output to the adjacent parallel wiring start position is referred to as the inter-adjacent length Ls.

A large number of micropaths are formed in the LSI by automatic wiring, and the adjacent parallel wirings are formed in a predetermined micropath. It is difficult to trace the signal changes of all the micropaths provided with the adjacent parallel wirings and determine the presence or absence of the change of the crosstalk delay at every timing because of time constraints. In other words, it is effective for the crosstalk delay to give a range of plus delay and minus delay to the amount of crosstalk delay generated. Therefore, the crosstalk delay is
It can be treated as "variation" with a meaning including uncertainty. By thus setting the upper limit value and the lower limit value for the crosstalk delay generation amount, it is possible to include the crosstalk delay generation amount in all signal timing states. In the present invention, this "variation" of crosstalk delay is referred to as crosstalk delay variation. This crosstalk delay variation can be reflected in the normal delay calculation. INDUSTRIAL APPLICABILITY According to the present invention, for a micropath in which a predetermined crosstalk delay variation is determined, a crosstalk delay variation given to a target path by an adjacent parallel wiring formed by automatic wiring can be obtained with high accuracy, and wiring can be performed in the micropath. By deciding the parallel wiring length Lp, it contributes to highly accurate placement and routing processing.

First, the factors affecting the above variation in crosstalk delay will be considered below. FIG. 3A shows an example wiring configuration diagram of a signal line configured by automatic wiring processing. According to (A) of the figure, the signal line is arranged between the source gate 301 of interest and the sink gate 302 of interest, and the signal line arranged between the adjacent source gate 303 and the adjacent sink gate 304 is Adjacent parallel wirings having a parallel wiring length Lp with a length Ls between adjacent wirings are provided from the source gate 301. 3B, the correlation between the adjacent length Ls and the crosstalk delay variation Δtdp (ps: the unit is picosecond) in the configuration of FIG. 3A is shown for each parallel wiring length Lp. The represented correlation diagram is shown. Here, expressing the crosstalk delay variation Δtpd in picoseconds means that the crosstalk delay variation Δtpd is simply represented by the signal delay amount. From (B) of the figure, the crosstalk delay variation Δtp increases as the adjacent length Ls increases.
It can be seen that d [ps] becomes large. Further, as the parallel wiring length Lp becomes longer, the crosstalk delay variation Δt
It can be seen that pd [ps] becomes large. in this way,
It can be seen that the adjacent length Ls and the parallel wiring length Lp are parameters for determining the crosstalk delay variation Δtpd [ps].

Variation in crosstalk delay Δtp
Elements of d [ps] include a load capacitance delay due to the drivability of the source gates of the target path and the adjacent path and a wiring resistance delay of the target path and the adjacent path. Since the delay variation due to the load capacitance delay and the delay variation due to the wiring resistance delay differ in the timing of the maximum value or the minimum value of the delay, simply take the maximum value or the minimum value of the two and the crosstalk delay variation Δtpd [ ps] means that the desired crosstalk delay variation Δtpd
[Ps] will be overestimated. FIG. 4 shows a correlation diagram between the crosstalk delay variation Δtpd [ps] when the parallel wiring length Lp is 2 mm, the load delay variation due to crosstalk, and the adjacent length Ls. The crosstalk delay variation Δtpd [ps] is a combination of the load delay variation due to crosstalk and the wiring resistance variation due to crosstalk.
In the figure, crosstalk delay variation Δtpd
The difference obtained by subtracting the load delay variation due to crosstalk from [ps] is the wiring resistance delay variation due to crosstalk. According to the figure, when the length Ls between adjacent portions increases, the value of the load capacitance delay variation due to crosstalk converges to 0, and the crosstalk delay variation Δtp.
It can be seen that d [ps] is determined only by the wiring resistance delay. From this, it can be said that there is no useful factor obtained by separating the crosstalk delay variation Δtpd [ps] into constituent elements. Therefore, in the present embodiment, the crosstalk delay variation Δt
It is assumed that pd [ps] is handled without being separated into the above components.

FIG. 5A shows the same wiring configuration diagram as FIG. 3A. In FIG. 9A, the output of the source gate 301 of interest is changed to the sink gate 302 of interest.
The length of the wiring up to the input of is the source-sink distance Ls
k. In FIG. 5B, the source-sink distance Lsk and the crosstalk delay variation Δtpd [p
[s] is shown for each adjacent length Ls. From (B) of the figure, the distance L between the source and the sink
As sk becomes longer, crosstalk delay variation Δt
It can be seen that pd [ps] is saturated to a constant value for each adjacent length Ls. Therefore, the saturation value of the crosstalk delay variation Δtpd [ps] in each adjacent length Ls is set to the crosstalk delay variation Δtpd of the adjacent length Ls.
With [ps], it is possible to specify the crosstalk delay variation without considering the source-sink distance Lsk dependency. In the present embodiment, the saturation value is defined as the crosstalk delay variation Δtpd [ps].

FIG. 6 shows the source-sink distance Ls.
A correlation diagram is shown in which the correlation between k and the crosstalk delay variation Δtpd [%] is represented for each adjacent length Ls. Expressing the crosstalk delay variation Δtpd as a percentage means that the crosstalk delay variation Δtp with respect to the typical delay [ps] in the same path.
It is meant to indicate the ratio of d [ps]. Typical delay is logic gate delay, wiring resistance delay,
This is a delay that combines the wiring load delay and the source-
If the inter-sync distance Lsk becomes longer, the typical delay also increases. Therefore, as shown in the figure, the crosstalk delay variation Δtpd [%] decreases as the source-sink distance Lsk increases. Therefore, if the crosstalk delay variation is expressed in%, it becomes necessary to consider the dependency of the source-sink distance Lsk in addition to the adjacent length Ls. In this embodiment, the crosstalk delay variation is expressed in picoseconds [ps] in order not to increase unnecessary parameters, and the saturation value is used to facilitate the calculation of the crosstalk delay variation Δtpd [ps]. However, since the crosstalk delay variation Δtpd [ps] used here is the above-mentioned saturation value, when applied to the source-sink distance Lsk that is smaller than the saturation value, the crosstalk delay variation Δtpd [p].
Note that [s] will be larger than the measured value.

FIG. 7A shows an example wiring configuration diagram when the directions of the gates of the target path and the adjacent path are different. FIG. 1A shows a case 1 in which the signal traveling direction of the adjacent path is set to the same right direction as the path of interest and the adjacent parallel wiring having the parallel wiring length Lp with the inter-adjacent length Ls is provided. Further, in (A) of the same figure, the signal traveling direction of the adjacent path is opposite to that of the target path, and the adjacent parallel wiring having the same inter-adjacent length Ls as Case 1 and the same parallel wiring length Lp as Case 1 is provided. Case 2 is shown. FIG. 7B shows a correlation diagram between the crosstalk delay variation Δtpd [ps] in Case 1 and Case 2 and the adjacent length Ls. In FIG. 9B, the black circles represent the data of the crosstalk delay variation Δtpd [ps] in Case 1, and the black circles represent the crosstalk delay variation Δt of Case 2.
The data of pd [ps] is shown. According to (B) of the figure,
Crosstalk delay variation between Case 1 and Case 2 △
Since tpd [ps] match each other, it is understood that the signal traveling direction of the adjacent path with respect to the target path does not affect the crosstalk delay variation Δtpd [ps] if the adjacent length Ls is the same value. However, when the parallel wiring length Lp is long, the influence due to the difference in the signal traveling direction may be considered, but since the parallel wiring length Lp is limited in the automatic wiring process, the difference in the signal traveling direction is considered in the present embodiment. There is no need to do it.

As described above, it has been found that the crosstalk delay variation Δtpd [ps] in the present embodiment is determined by the adjacent length Ls and the parallel wiring length Lp. Next, a method of setting the adjacent length Ls and the parallel wiring length Lp will be described. First, consider a case where one adjacent net forms an adjacent parallel wiring in the path of interest.

In FIG. 8A, one adjacent path is the adjacent path length Ls (0 mm) and the parallel wiring length Lp (1 mm) is the path of interest.
An example wiring configuration diagram in the case of forming the adjacent parallel wirings a and b is shown. Here, the distance L between parallels between adjacent parallel wirings a and b is set. FIG. 2B shows a parallel distance L ′ in the wiring configuration shown in FIG.
And a crosstalk delay variation Δtpd [ps] is shown. According to FIG. 6B, it is understood that the crosstalk delay variation Δtpd [ps] maintains a substantially constant range regardless of the change in the parallel distance L ′. Crosstalk delay variation Δt at this time
pd [ps] has a parallel wiring length Lp of 2 mm and an adjacent length L
It is the same as when s is 0 mm. Therefore, the crosstalk delay variation Δtpd [ps] of the above wiring configuration
Can be obtained by setting the inter-parallel distance L ′ to 0 in the above wiring configuration.

In FIG. 9A, one adjacent path is a length Ls (0 mm) between adjacent ones and a parallel wiring length Lp (1 mm) is a path of interest.
Another wiring configuration diagram in the case of forming the adjacent parallel wirings a and b is shown. In (A) of the figure, adjacent parallel wirings each having a parallel wiring length Lp (1 mm) are formed in the respective wirings of one adjacent path branched to the target path.
The distance between the adjacent parallel wirings a and b in the target path at this time is defined as a parallel distance L ′. In (B) of the figure,
The parallel distance L ′ and the crosstalk delay variation Δtpd [p in the wiring configuration shown in FIG.
s] is shown. According to FIG. 6B, it can be seen that the crosstalk delay variation Δtpd [ps] maintains a substantially constant range regardless of the change in the parallel distance L ′. At this time, the crosstalk delay variation Δtpd [ps] in (A) of FIG.
Is 2 mm and the adjacent length Ls is 0. Therefore, the crosstalk delay variation Δt of the above wiring configuration
pd [ps] can be obtained by setting the inter-parallel distance L ′ to 0 in the above wiring configuration.

FIG. 10A shows another wiring configuration diagram when one adjacent net forms adjacent parallel wirings a and b having a parallel wiring length Lp (1 mm) with a length Ls between adjacent wirings in a path of interest. Be done. In (B) of the figure, the parallel distance L'and the adjacent length Ls in the wiring configuration shown in (A) of the figure.
And a crosstalk delay variation Δtpd [ps] is shown. In FIG. 10B, the black circles represent data of the crosstalk delay variation Δtpd [ps] that occurs in the target path of FIG.
Crosstalk delay variation Δt when p is 2 mm
The data of pd [ps] is shown. According to (B) of the figure,
It can be seen that the crosstalk delay variation Δtpd [ps] in (A) of the figure has almost the same value as the case where the parallel wiring length Lp is 2 mm and the parallel wiring length Lp is 2 mm, regardless of the change in the parallel distance L ′. . In this way, when one adjacent path forms two adjacent parallel wirings in the target path, crosstalk is performed using the adjacent length Ls of the adjacent parallel wirings close to the target source gate and the total value of the parallel wiring lengths Lp as parameters. It is understood that the delay variation Δtpd [ps] can be obtained.

FIG. 11A shows an example wiring configuration diagram in which one adjacent net forms adjacent parallel wirings a, b, c having a parallel wiring length Lp (1 mm) with an inter-adjacent length Ls in a path of interest. Shown. At this time, the adjacent length Ls is arbitrary, and the parallel distance L ′ is set to 1 mm. In (B) of the figure, the adjacent length Ls and the crosstalk delay variation Δtpd [ps] in the wiring configuration shown in (A) of the figure.
A correlation diagram with is shown. In FIG. 11B, a black circle indicates data of crosstalk delay variation Δtpd [ps] generated in the target path of FIG.
The data of the crosstalk delay variation Δtpd [ps] that occurs in the path of interest when one adjacent parallel wiring having the parallel wiring length Lp of 3 mm is formed in the adjacent net is shown. According to FIG. 9B, the crosstalk delay variation Δtpd [ps] of the above wiring configuration can be obtained by setting the inter-parallel distance L ′ to 0 in the above wiring configuration.

FIG. 12 (A) is another wiring configuration diagram in the case where one adjacent net forms adjacent parallel wirings a, b, c having a parallel wiring length Lp (1 mm) with an adjacent length Ls in the path of interest. Is shown. At this time, the adjacent length Ls is arbitrary, and the parallel distance L ′ is set to 2 mm. In (B) of the figure, the adjacent length Ls and the crosstalk delay variation Δtpd [ps] in the wiring configuration shown in (A) of the figure.
A correlation diagram with is shown. The black circles in FIG. 12B indicate data of the crosstalk delay variation Δtpd [ps] that occurs in the target path of FIG.
The data of the crosstalk delay variation Δtpd [ps] that occurs in the path of interest when one adjacent parallel wiring having the parallel wiring length Lp of 3 mm is formed in the adjacent net is shown. According to FIG. 9B, the crosstalk delay variation Δtpd [ps] of the above wiring configuration can be obtained by setting the inter-parallel distance L ′ to 0 in the above wiring configuration.

FIG. 13A shows an example wiring configuration diagram in which one adjacent net forms adjacent parallel wirings a, b, and c having a parallel wiring length Lp (1 mm) with an inter-adjacent length Ls in a path of interest. Shown. At this time, the adjacent length Ls and the parallel distance L ′ are arbitrary, and the source-gate distance Lsk is 12
mm. The relationship between the adjacent length Ls and the parallel distance L ′ is such that when the parallel distance L ′ is 0 mm, the adjacent length Ls is 4 mm, and the parallel distance L ′ is 4 mm.
In this case, the length Ls between adjacent portions is set to 0 mm, and the length from the source gate of interest to the start position of the second adjacent parallel wiring is fixed at 5 mm. FIG. 2B shows a parallel distance L ′ in the wiring configuration shown in FIG.
And the adjacent length Ls and the crosstalk delay variation Δt
A correlation diagram with pd [ps] is shown. In FIG. 13B, the black circles represent data of the crosstalk delay variation Δtpd [ps] that occurs in the target path of FIG. 13A, and x represents 1 in the target path and the adjacent net has a parallel wiring length Lp of 3 mm. The data of the crosstalk delay variation Δtpd [ps] that occurs in the target path when the adjacent parallel wirings are formed is shown. In this way, even when one adjacent path forms three adjacent parallel wirings in the target path, the crosstalk is performed using the inter-adjacent length Ls of the adjacent parallel wirings close to the target source gate and the total value of the parallel wiring lengths Lp as parameters. Delay variation Δtp
It can be seen that d [ps] can be obtained.

According to the above description of FIGS. 8 to 13, even if one adjacent net forms a plurality of adjacent parallel wirings in the target path, the crosstalk delay variation Δtpd occurring in the target path.
[Ps] can be obtained by summing the lengths of adjacent parallel wirings to be formed as the parallel wiring length Lp using the same length Ls between adjacent wirings. This is shown visually by FIG. In FIG. 14A, one adjacent net in the path of interest has an inter-adjacent length Ls and parallel wiring lengths Lp1 and Lp.
The crosstalk delay variation Δtpd [ps] that occurs in the path of interest when the p2 adjacent parallel wiring is formed is
One adjacent net in the path of interest has a length Ls between adjacent nets and a parallel wiring length L.
Crosstalk delay variation Δtpd [p that occurs in the path of interest when adjacent parallel wirings of p1 + Lp2 are formed
s]. Further, in FIG. 14B, one adjacent net branched to the path of interest has parallel wiring lengths Lp1 and Lp2 with an inter-adjacent length Ls for each branch wiring.
The crosstalk delay variation Δtpd [ps] that occurs in the path of interest when the adjacent parallel wires are formed is as follows.
Crosstalk delay variation Δtpd [ps] that occurs in the path of interest when + Lp2 adjacent parallel wiring is formed
Is shown to be the same. Further, in FIG. 14C, crosstalk that occurs in the target path when one adjacent net includes parallel lines Lp1, Lp2, and Lp3 with an inter-adjacent length Ls including branching in the target path. The delay variation Δtpd [ps] is such that one adjacent net in the target path has a length Ls between adjacent nets and a parallel wiring length Lp1 + L.
Crosstalk delay variation Δtpd [p] that occurs in the path of interest when adjacent parallel wirings of p2 + Lp3 are formed
s].

In FIG. 15A, the path of interest is a differential wire, and one adjacent net forms an adjacent parallel wire b of a parallel wire length Lp (1 mm) with a length Ls between adjacent wires in the path of interest. An example wiring configuration diagram is shown. The target path of the differential wiring is
In order to equalize the lengths of the positive side wiring and the negative side wiring, which are pair wirings during automatic wiring, the pair wirings are laid so as to be parallel wirings to adjacent channels as much as possible. Crosstalk delay variation due to pair wiring
Since the influence of tpd [ps] is included in the typical delay, the adjacent parallel wiring a by the pair wiring of the differential wiring is used.
Crosstalk delay variation Δt given to the target path by
pd [ps] need not be considered. Therefore, it is sufficient to consider only the crosstalk delay variation Δtpd [ps] that occurs in the path of interest in the wiring configuration shown in FIG. That is, the crosstalk delay variation Δtpd [ps] that occurs in the target path of (A) in the figure can be obtained from the adjacent length Ls and the parallel wiring length Lp. In FIG. 6B, the length from the source gate of the adjacent path to the start position of the adjacent parallel wiring is different, and the length Ls between the adjacent wirings and the parallel wiring length Lp are different.
An example of a wiring configuration in which the two are equal is shown. When obtaining the crosstalk delay variation Δtpd [ps], the length from the source gate of the net forming the adjacent parallel wiring adjacent to the target path to the adjacent parallel wiring is not considered in this embodiment. Therefore, the target path of the two-wiring configuration as shown in FIG. 7B has the same crosstalk variation Δtpd [ps].
Shall have. As the influence of the crosstalk delay variation, it is necessary to consider the distance dependency from the source gate of the adjacent net to the adjacent parallel wiring. However, in order to simplify the parameters, the consideration is omitted in this embodiment. , If necessary, can be considered. In this case, the length from the source gate of the adjacent net to the adjacent parallel wiring is added as a parameter.

In the above description, the case where one adjacent net forms an adjacent parallel wiring in the path of interest has been described. When a plurality of adjacent nets are formed on the target path, the target path and the adjacent nets may be replaced by a one-to-one correspondence, and the adjacent length Ls and the parallel wiring length Lp may be determined for each combination. When the target path is composed of a plurality of micropaths and one adjacent net forms an adjacent parallel wiring in the target path, the inter-adjacent length Ls and the parallel wiring length Lp may be determined for each target gate.

Furthermore, the obtained crosstalk variation Δ
In order to bring tpd [ps] close to the actual measured value, the length L
It is effective to perform the following processing on s and the parallel wiring length Lp. In FIG. 16A, an example wiring configuration diagram is shown in which an adjacent parallel wiring a having an adjacent path of, for example, about several μm is formed in the vicinity of the source gate of the target path, and an adjacent parallel wiring b is formed further away. Shown. Crosstalk delay variation Δtpd given to the path of interest by the adjacent parallel wirings a and b
In [ps], the influence of the adjacent parallel wiring b is dominant, and the influence of the adjacent parallel wiring a is small. Here, assuming that the inter-adjacent length Ls is the length to the start position of the adjacent parallel wiring a and the total length of the adjacent parallel wirings a and b is the parallel wiring length Lp, the crosstalk delay variation Δ compared to the actually measured value tp
d [ps] may be underestimated. This is because the crosstalk delay variation Δt decreases as the adjacent length Ls decreases.
This is because pd [ps] becomes small. In this case, the adjacent length Ls is the distance from the source gate of interest to the start point of the adjacent parallel wiring b, and the parallel wiring length Lp is the adjacent parallel wiring a,
It was found that the total length of b is a process according to the actual measurement value. Therefore, in order to obtain the correct crosstalk delay variation Δtpd [ps], it is effective to determine the adjacent length Ls as follows.

In FIG. 16B, one adjacent net has a plurality of adjacent parallel wirings a (parallel wiring length is Lp1) in the path of interest.
b (parallel wiring length is Lp2), c (parallel wiring length is Lp2)
3), d (parallel wiring length is Lp4), e (parallel wiring length is Lp4)
p5) is formed. At this time, the parallel wiring lengths Lp are sequentially added from the parallel wirings closer to the focused source gate, and the total value Lpn ′ (ΣLpn) of the parallel wirings is defined from the parallel wiring source distance defined length Lps The distance to the output of the source gate is defined as the adjacent length Ls. The parallel wiring source distance definition length Lps is the minimum parallel wiring length Lp for the parallel wiring length Lp to influence the adjacent length Ls. The parallel wiring source distance definition length Lps is defined in a predetermined library according to the combination of the target path and the adjacent path. In FIG. 16B, it is assumed that there is a relationship of Lp1 ′ = Lp1 <Lps Lp2 ′ = Lp1 + Lp2 <Lps Lp3 ′ = Lp1 + Lp2 + Lp3 <Lps Lp4 ′ = Lp1 + Lp2 + Lp3 + Lp4 ≧ Lps. Therefore, the adjacent length Ls, which is a factor of the crosstalk delay variation, can be set to the length from the source gate to the start position of the parallel wiring length Lp4. The parallel wiring length Lp at this time is Lp1 + Lp2 + L
It becomes p3 + Lp4 + Lp5. That is, the adjacent parallel wirings of the adjacent net are Lp1 + Lp2 from the position of the length Ls between the adjacent portions.
The crosstalk delay variation Δtpd [ps] can be obtained with the same wiring configuration as when there is a parallel wiring length Lp of + Lp3 + Lp4 + Lp5. At this time, the wiring length of the net may be longer than the path of interest, but there is no problem in calculating the crosstalk delay variation. When the wiring length of the path of interest is short and does not reach the parallel wiring source distance definition length Lps, or Lpn ′ is the parallel wiring source distance definition length Lp.
When it does not reach s, the adjacent length Ls is set to 0.

When the parallel wiring length Lp is, for example, several μm or less, it is assumed that the influence of the crosstalk variation on the target path by the parallel wiring length Lp is not measured. If these crosstalk variations due to the minute parallel wiring length Lp are taken into consideration, an increase in information of the parallel wiring length Lp and an increase in the derivation time of the crosstalk delay variation Δtpd [ps] will be caused. Therefore, the minimum parallel wiring length Lp for influencing the crosstalk delay variation is defined in a predetermined library according to the combination of the target path and the adjacent path. The minimum parallel wiring length Lp is the parallel wiring sensitivity length Lp (MIN), and when Lpn> Lp (MIN), it is treated as an adjacent parallel wiring, and Lpn ≦ Lp (MI
In the case of N), it is not treated as an adjacent parallel wiring. FIG.
The adjacent parallel wirings a to e shown in (B) are all processed as values larger than the parallel wiring sensitivity length Lp (MIN). If the adjacent parallel wirings a to c are parallel wiring sensitivity length Lp
When (MIN) or less, the parallel wiring length Lp is set to d + e in FIG.

The method of determining the inter-adjacent length Ls and the parallel wiring length Lp when the adjacent parallel wirings are formed has been described above. As described above, the adjacent length Ls and the parallel wiring length L
By obtaining p, the parallel wiring length limitation and the crosstalk delay variation Δtpd [ps] described below can be easily calculated.

The parallel wiring is restricted so that the parallel wiring length Lp of the adjacent parallel wiring formed by the automatic wiring has a crosstalk delay variation Δtpd [ps] which is given to the target path within the allowable range. Define the value. First, the layout information of the target path and the adjacent path, which are the parallel wiring length restriction targets, is selected. The layout information identifies the adjacent length Ls, the parallel wiring length Lp, and the driving capability of the source gate of interest. That is, if the allowable range of the predetermined crosstalk delay variation Δtpd [ps], the driving capability of the source gate of interest, and the adjacent length Ls are determined, the maximum value of the adjacent parallel wiring is limited. For example, as can be seen from FIG. 3B, the crosstalk delay variation Δtpd [ps] is increased by increasing the parallel wiring length Lp to 1, 2, 3 [mm].
The absolute value of Tctk also increases proportionally. When the length Ls between adjacent portions is 2 mm, the absolute value Tctk when the parallel wiring length Lp is 1 mm is 20 ps, the absolute value Tctk when the parallel wiring length Lp is 2 mm is 41 ps, and the parallel wiring length Lp is 3 mm.
In this case, the absolute value Tctk is 64 ps. Therefore, the absolute value Tctk and the parallel wiring length Lp have a direct proportional relationship of Tctk∝Lp. In FIG. 3B, the absolute value when the adjacent length Ls is 10 mm and the parallel wiring length Lp is 2 mm is Tctk.
Is 95 ps. Further, when the length Ls between adjacent portions is 8 mm and the parallel wiring length Lp is 2 mm, the absolute value Tctk is 72 ps. Therefore, when the length Ls between adjacent portions is 8 mm, the absolute value Tc
The reason why tk becomes 95 ps can be calculated from the above proportional relationship as the parallel wiring length Lp = (95 ps / 72 ps) * 2 mm = 2.64 mm. This parallel wiring length Lp (2.64
mm) is an upper limit value Lp ′ when the absolute value Tctk95ps is the maximum allowable value. That is, the upper limit value Lp ′ that is the absolute value Tctk that is the maximum allowable value in a certain adjoining length Ls is Lp ′ = (Tctk (r) / Tctk (Ls)) * Lp [mm] (where Tctk ( r) is the absolute value T of the maximum allowable value
ctk, where Tctk (Ls) is a predetermined length Ls between adjacent
The absolute value for the parallel wiring length Lp in FIG. Lp
Indicates the parallel wiring length designated for obtaining Tctk (Ls). ) Can be obtained from That is, from the absolute value Tctk, which is the maximum allowable value of the crosstalk delay variation Δtpd [ps], and the predetermined adjacent length Ls, the limit value Lp ′ indicating the longest value of the parallel wiring Lp at that time can be obtained. . The obtained limit value Lp ′ is the parameter L
When it is compared with p and Lp> Lp ′, automatic placement / placement / wiring is required again.

In FIG. 17A, the adjacent length Ls is 10 mm and the parallel wiring length Lp is 2 m in FIG. 3B.
From the absolute value of 95 ps when m, the absolute value Tc of the above formula
A correlation diagram between the limit value Lp ′ and the adjacent length Ls when tk (r) is 95 ps is shown. From (A) of the figure, the limit value Lp ′ is expressed by a linear function with the inter-adjacent length Ls as a parameter. However, since the above Lp ′ is expressed by a linear expression, depending on the value of the adjacent length Ls, the parallel wiring length L
In some cases, p'may be 0 mm or less. This means that adjacent parallel wiring is not permitted. In order to avoid this situation, a lower limit value is set for the parallel wiring length limit value Lp (max). The obtained Lp ′ is the limit value Lp (m
ax) and is compared with the parallel wiring length Lp obtained from the layout information in the first stage of the parallel wiring length limiting process. L
When p> Lp (max), automatic placement / placement / wiring is required again.

The parallel wiring length limit value Lp (max) is Lp (max) = ((Z-X) / Y) * Ls + X (where Lp (max) = Z when Ls≥Y, and L
When s = 0, Lp (max) = X. ) Can be expressed by a linear expression with the adjacent length Ls as a parameter. FIG. 17B shows a correlation diagram between the parallel wiring length limit value Lp (max) and the adjacent length Ls according to the above formula. The slope (Z-X) / Y indicates the dependency of the parallel wiring length Lp 'on the adjacent length Ls, and the coefficient Z indicates the lower limit value. The coefficient X indicates the maximum parallel wiring length Lp provided for each load driving capability value of the target source gate. The coefficient Y indicates the reduction ratio of the load driving capability. These coefficients X, Y,
Z is determined according to the driving capability of the source gate of the path of interest, and is set in advance in the function table.

Next, the crosstalk delay variation Δt
A method of calculating pd [ps] will be described. The crosstalk delay variation Δtpd [ps] is defined in the delay table by the combination of the target path and the adjacent path in units of micropaths. The above-mentioned crosstalk delay variation Δtpd [ps] is such that the minimum crosstalk delay value and the maximum crosstalk delay value are the adjacent length Ls.
And the parallel wiring length Lp can be expressed as an absolute value. Therefore, the adjacent length Ls and the parallel wiring length Lp
Using as a parameter, it is possible to easily create a delay table for obtaining an absolute value indicating the crosstalk delay variation Δtpd [ps]. FIG. 18A shows a configuration diagram of a target path and an adjacent net for which a delay table is created. The delay table has a form as shown in (B) of the figure, for each combination of load driving capabilities of the target source gate and the adjacent source gate, for each maximum and minimum crosstalk delay value, and for each target source gate. It is defined for each output polarity, for each combination of adjacent parallel wiring types, and the like. For example, the delay table obtained from the combination of the source gate of interest and the adjacent source gate in the configuration of FIG. 7A has the maximum value of the rising polarity, and the line width of the line of interest is the middle line (predetermined line width). It is possible to specify that the wiring width of the adjacent path is a thick line (predetermined wiring width). As described above, in the predetermined delay table, the crosstalk delay variation Δtpd [p] with the inter-adjacent length Ls and the parallel wiring length Lp as parameters is set.
The absolute value of [s] is defined. Therefore, if a desired delay table is used, the crosstalk delay variation Δtpd [ps] can be easily obtained as an absolute value from the adjacent length Ls and the parallel wiring length Lp of the wiring information of the predetermined target path and the adjacent net. it can. Crosstalk delay variation Δtpd [ps] described in the above delay table
The absolute value of is preferably a value at which the crosstalk generation amount is maximized in consideration of the timings of the output waveforms of both the source gate of the target path and the source gate of the adjacent path.

Hereinafter, crosstalk delay variation Δtpd due to combinations of various paths of interest and adjacent paths
A method of calculating [ps] will be described. In FIG. 19A,
An example wiring configuration diagram in which two adjacent nets form adjacent parallel wirings a and b in the path of interest is shown. Crosstalk delay variation Δtpd of the path of interest shown in FIG.
When obtaining [ps], it can be considered separately by the wiring configuration shown by the arrow → in the figure. Therefore, the absolute value of the crosstalk delay variation Δtpd [ps] for each adjacent net may be obtained from the predetermined delay table as described above. Crosstalk delay variation Δtpd [p of target path due to adjacent parallel wiring a of one adjacent net
Letting the absolute value of [s] be Tctk and the absolute value of the crosstalk delay variation Δtpd [ps] of the target path by the adjacent parallel wiring b of the other adjacent net be Tctk, the variation of the crosstalk delay Δtpd [p of the target path
The absolute value Tctk of [s] is represented by Tctk = √ (Tctk ² + Tctk ² ) [ps].

In FIG. 19B, an example wiring configuration diagram in which the same net is adjacent to a path of interest composed of two micropaths that are continuously arranged and adjacent microwiring is provided to each micropath Is shown. When obtaining the crosstalk delay variation Δtpd [ps] of the path of interest, the wiring configuration can be divided into the wiring configurations indicated by the arrow ↓. That is, the crosstalk delay variation Δtpd [ps] may be calculated for each micropath. At this time, it is assumed that the adjoining source gate of the subsequent micropass is the same as the adjoining source gate of the preceding micropass. Therefore, the absolute value of the crosstalk delay variation Δtpd [ps] of the micropath in the preceding stage of the target path is T
ctk, adjacent parallel wiring b of the micro-path after the target path b
Crosstalk delay variation due to Δtpd [ps]
Is the absolute value of the crosstalk delay variation Δtpd [ps] of the path of interest Tctk
Is represented by Tctk = √ (Tctk ² + Tctk ² ) [ps] as in the above.

In FIG. 20A, one source gate 18 is provided.
An example wiring configuration diagram in which adjacent parallel wirings a and b are provided by two adjacent nets to one wiring of the branch wiring composed of 01 and 2 sink gates 1802 and 1803 is shown. The parallel wirings a and b formed by the adjacent nets N1 and N2 are provided on the wiring of the sink gate 1802 from the branch point. In this case, the source gate 1801 and the sink gate 1803 of interest
The absolute value Tctk of the crosstalk delay variation Δtpd [ps] that occurs in the path between and can be obtained in the same manner as the wiring configuration of FIG. That is, the absolute value of the crosstalk delay variation Δtpd [ps] due to the adjacent parallel wiring a of the adjacent net N1 is Tctk,
The absolute value of the crosstalk delay variation Δtpd [ps] due to the adjacent parallel wiring b of the adjacent net N2 is Tctk.
Then, the crosstalk delay variation Tc of the path
Like the above, tk can be represented by Tctk = √ (Tctk ² + Tctk ² ) [ps]. Also, the source gate 1801 of interest
The crosstalk delay variation Δtpd [ps] generated in the path between the sync gate 1803 and the sync gate 1803 is set to the same value as Tctk for convenience here. In the actual path, the influence of the adjacent net can be ignored, but in the present embodiment, the crosstalk delay variation Δtpd [ps].
Crosstalk delay variation Δtpd with a path formed by the same target path in order to efficiently obtain
Set [ps] to the same value.

FIG. 20B shows an example wiring configuration diagram in which the target path itself branches to provide parallel wiring adjacent to its own wiring. In this case, only the negative variation of the crosstalk delay variation is calculated, and the positive variation is set to 0. This is because if one wire is considered as the path of interest and the other wire is considered as an adjacent net, the potential of the path of interest and the adjacent net are always equal, so the wire capacitance between adjacent parallel wires cannot be seen from the source gate of interest. by.

In FIG. 21A, an adjacent net B composed of a differential wiring and an adjacent net C composed of a single wiring are arranged for the path A of interest. In the path of interest, adjacent parallel wirings b are formed between adjacent nets formed of differential wirings, and adjacent parallel wirings c are formed between adjacent nets formed of a single wiring. Although the adjacent parallel wiring a is formed between the paired wirings of the gate of interest, it is not necessary to obtain the crosstalk delay variation Δtpd [ps] for the adjacent parallel wiring a for the above reason. The absolute value of the crosstalk variation Δtpd [ps] due to the adjacent parallel wiring b is Tctk.
(B) Assuming that the absolute value of the crosstalk variation Δtpd [ps] due to the adjacent parallel wiring c is Tctk (c), the absolute value Tctk (of the crosstalk variation Δtpd [ps] of the target path as the differential wiring. Differential) is represented by Tctk (differential) = √ (Tctk (b) ² + Tctk (c) ² ).

FIG. 21B shows an example configuration diagram in which the same adjacent net has a plurality of adjacent parallel wirings with respect to the path of interest. According to (A) of the same figure, one adjacent net is formed by one wiring and the adjacent parallel wiring a,
b, and another adjacent net provides adjacent parallel wirings c and d by branch wiring. In this case, the absolute value Tctk of the crosstalk delay variation Δtpd [ps] is
The wiring configuration is as shown by the arrow ↓, and the crosstalk delay variation Δtpd [ps] for each adjacent net.
Can be obtained by taking the root mean square of them.

FIG. 22 shows an example configuration diagram in which adjacent parallel wirings are provided by adjacent nets for each of a plurality of micropaths μPn forming a predetermined target path. In this case, the absolute value Tctk of the crosstalk delay variation Δtpd [ps] can be calculated by the following equation. Tctk = √ (ΣTctk (n) ² ) [ps] (In the formula, Tctk (n) indicates the absolute value of the crosstalk delay variation Δtpd [ps] of the micropath μPn.) The crosstalk delay of the obtained target path Variation Δt
The absolute value Tctk of pd [ps] is added to the typical delay value Tpd [ps] of the same target path to obtain the delay value variation Tdy of the entire target path. The above-mentioned typical delay value Tpd [ps] is a delay value of the target path itself. In other words, it is the delay value of the target path when the adjacent parallel wiring is not arranged. The above relationship is shown below. Tdy = Tpd ± Tctk [ps] Furthermore, when the process, power supply voltage, and temperature variations are taken into account, Tdy = Tpd (Typ) ± (process, power supply voltage, temperature variations) ± Tctk [ps]. Delay value variation T obtained in this way
If dy is within the allowable range in the system, the current wiring is maintained. Further, if it is out of the allowable range, it is necessary to change the logical arrangement and wiring configuration.

FIG. 1 is a flow chart showing a process for obtaining the above-described parallel wiring length limitation and crosstalk delay variation Δtpd [ps]. According to the figure, the adjacent parallel wiring formed by the automatic wiring is checked in micropath units. In step 101, the inter-adjacent length Ls of the adjacent parallel wiring formed in the micropath unit
And the parallel wiring length Lp is extracted. In step 101, the driving capability of the source gate of interest is identified. In step 102, a predetermined coefficient X, Y, Z is selected from a table in which the values of the coefficient X, Y, Z are set according to the driving capacity of the source of interest, and the parallel wiring length Lp (max) is obtained. To determine a linear equation for In step 103,
By inputting the adjacent length Ls to the obtained linear expression, the parallel wiring length Lp (max) that can be formed in the micropath can be obtained. In step 104, the obtained parallel wiring length Lp (m
ax) is compared with the parallel wiring length Lp to confirm whether the adjacent parallel wiring formed by the automatic wiring can be actually arranged. If the parallel wiring length Lp is equal to or less than the parallel wiring length Lp (max), the adjacent parallel wiring can be arranged. If the parallel wiring length Lp is larger than the parallel wiring length Lp (max), the adjacent parallel wiring cannot be arranged and relocation is required. The processing from step 101 to step 104 is parallel wiring length limitation. The adjacent parallel wirings in which the parallel wiring length Lp is within the parallel wiring length limit value move to the process of obtaining the crosstalk delay variation Δtpd [ps].
In step 105, a predetermined delay table is selected from the delay table library according to the combination of the target path and the adjacent path as described above. Step 10
6, the obtained delay table is used, and the crosstalk delay variation Δt given to the path of interest by the adjacent parallel wiring is set by using the adjacent length and the parallel wiring length Lp as parameters.
Calculate pd [ps]. In step 107, it is confirmed whether the obtained crosstalk delay variation Δtpd [ps] is within a predetermined range. Here, when the obtained crosstalk delay variation Δtpd [ps] is out of the predetermined range, rewiring is required.

According to the above embodiment, the following operational effects can be obtained. (1) The crosstalk delay variation Δtpd [ps] given to the target path by the adjacent parallel wiring formed by the target path and the adjacent path is obtained from a predetermined delay table using the inter-adjacent length Ls and the parallel wiring length Lp as parameters. be able to. Since the crosstalk delay variation Δtpd [ps] is obtained using the two parameters, the obtained crosstalk delay variation Δtpd [ps] is more accurate than the conventional one obtained only from the parallel wiring length Lp. To be taken. (2) The parallel wiring length Lp is the total length of the length of the plurality of adjacent parallel wirings when a plurality of adjacent parallel wirings are formed by one adjacent net. The crosstalk delay variation Δtpd [ps] in the case of such a wiring configuration does not need to be calculated for each adjacent parallel wiring, and one parallel wiring length Lp
Can be obtained by Therefore, the calculation of the crosstalk delay variation Δtpd [ps] becomes easy. (3) By setting the parallel wiring source distance definition length Lps, highly accurate crosstalk delay variation Δtp
It is possible to adjust the adjacent length Ls for obtaining d [ps]. (4) Crosstalk delay variation Δtpd [ps]
The upper limit of adjacent parallel wiring that does not cause
By setting (MIN) and assuming that there is no adjacent parallel wiring having a parallel wiring length Lp less than the parallel wiring sensitivity length Lp (MIN), the processing of the parallel wiring length Lp can be simplified. (5) If the upper limit value of the parallel wiring length Lp formed in the target path is used in accordance with the driving capability of the source gate of the target path by using a function that corresponds to the adjacent length, the upper limit value Lp of the parallel wire length Lp is (Max) is specified. Since the upper limit of the parallel wiring length can be confirmed before the delay calculation process, the crosstalk delay variation Δtp due to the adjacent parallel wiring can be confirmed.
The derivation of d [ps] can be speeded up, and the crosstalk delay variation Δtpd [ps] can be reduced.

Although the invention made by the present inventor has been specifically described based on the embodiments, the present invention is not limited thereto, and needless to say, various modifications can be made without departing from the scope of the invention. Yes.

For example, in the above embodiment, the drivability of the source gate of the adjacent parallel wiring may be assumed, but it is also possible to calculate the correct drivability and obtain the crosstalk delay variation.

In the above description, the case where the invention made by the present inventor is mainly applied to the automatic wiring method of the semiconductor integrated circuit which is the field of application which is the background of the invention has been described. It can be applied where it occurs.

[0049]

The effects obtained by typical ones of the inventions disclosed in the present application will be briefly described as follows.

That is, it is possible to obtain a highly accurate crosstalk delay value by using a predetermined delay table with the length between adjacent parallel wires and the parallel wire length as parameters. At that time, the length between adjacent portions and the parallel wiring length are simplified in order to obtain the crosstalk delay value with high accuracy and efficiency. Select a predetermined function from the properties of the source gate of the path of interest and the simplified adjacent length and parallel wiring length,
A highly accurate parallel wiring length limit value can be easily obtained. Further, the crosstalk delay value can be easily obtained from the delay table using the simplified parallel wiring length and the adjacent length as parameters.

[Brief description of the drawings]

FIG. 1 is a flowchart of a parallel wiring length limiting method and a delay determining method according to the present invention.

FIG. 2 is an example line configuration diagram in which adjacent parallel wirings are provided.

FIG. 3 is an example wiring configuration diagram in which adjacent parallel wirings are provided, an inter-adjacent length Ls and a crosstalk delay variation Δtpd.
It is a correlation diagram with [ps].

FIG. 4 is a correlation diagram of the adjacent length Ls, crosstalk delay variation Δtpd [ps], and load delay variation.

FIG. 5 is an example wiring configuration diagram in which adjacent parallel wirings are provided, and a correlation diagram between a source-gate distance Lsk and a crosstalk delay variation Δtpd [ps].

FIG. 6 is a correlation diagram between a source-gate distance Lsk and crosstalk delay variation Δtpd [%].

FIG. 7 is an example line configuration diagram in which adjacent parallel wirings are provided in which the gates of adjacent nets have opposite directions, and the adjacent length Ls and crosstalk delay variation Δtpd [p] at that time.
It is a correlation diagram with [s].

FIG. 8 is an example wiring configuration diagram in which two adjacent parallel wirings are formed by one adjacent net, and a length L ′ between parallel wirings at that time and a crosstalk delay variation Δtpd [p
It is a correlation diagram with [s].

FIG. 9 is another wiring configuration diagram in the case where two adjacent parallel wirings are provided by one adjacent net, the length L ′ between the parallel wirings and the crosstalk delay variation Δtpd [p
It is a correlation diagram with [s].

FIG. 10 is another wiring configuration diagram in the case where two adjacent parallel wirings are provided by one adjacent net, and the parallel wiring length L ′, the adjacent length Ls, and the crosstalk delay variation Δtpd [ps] at that time. It is a correlation diagram with.

FIG. 11 is an example wiring configuration diagram in which three adjacent parallel wirings are formed by one adjacent net, and the length Ls between adjacent portions and crosstalk delay variation Δtpd [ps] at that time.
It is a correlation diagram with.

FIG. 12 is another wiring configuration diagram in the case where adjacent parallel wiring is provided at three places by one adjacent net, and the adjacent length Ls and crosstalk delay variation Δtpd [ps] at that time.
It is a correlation diagram with.

FIG. 13 is another wiring configuration diagram when three adjacent parallel wirings are provided by one adjacent net, and the parallel wiring length L ′ and the adjacent wiring length Ls and the crosstalk delay variation Δtpd [ps]. It is a correlation diagram with.

FIG. 14 is an explanatory diagram schematically showing a delay calculation method of the present invention.

15A and 15B are an example wiring configuration diagram in the case where a target path is a differential wiring, and an explanatory diagram considering an influence of a length from a source gate of an adjacent path to a start position of an adjacent parallel wiring.

FIG. 16 is a crosstalk delay variation Δtpd [p when a defined length Lps between parallel wiring source distances is applied.
It is an explanatory view of how to obtain [s].

FIG. 17 is a correlation diagram between the parallel wiring limit length and the adjacent length Ls.

FIG. 18 is an explanatory diagram of a delay table in which the adjacent length Ls and the parallel wiring length Lp are parameters.

FIG. 19 is an example wiring configuration diagram in which adjacent parallel wiring is provided by two adjacent nets or a plurality of paths of interest by one adjacent net and crosstalk delay variation Δt at that time;
It is explanatory drawing of how to calculate | require pd [ps].

FIG. 20 is an example wiring configuration diagram in the case where the target path is a branch wiring or the adjacent parallel wiring is provided by the target path itself.

FIG. 21 is an example wiring configuration diagram in which a target path is a differential wiring and adjacent parallel wirings are formed by a plurality of adjacent nets; and an example wiring configuration in which a plurality of adjacent parallel wirings are formed for every two adjacent paths. It is a figure.

FIG. 22 is a diagram showing a path of interest composed of a plurality of micro paths,
It is an example wiring block diagram in which adjacent parallel wiring by an adjacent net is applied to each micropath.

FIG. 23 is a flowchart of a conventional automatic wiring method.

[Explanation of symbols]

 101 step 102 step 103 step 104 step 105 step 106 step 107 step

Claims (7)

[Claims] 1. A crosstalk delay value by an adjacent parallel wiring formed by a path of interest composed of one source gate and one sink gate and an adjacent path composed of one source gate and one sink gate Of the crosstalk delay obtained by simulation using the inter-adjacent length, which is the length from the source gate output point to the start point of the adjacent parallel wiring, and the parallel wiring length, which is the length of the adjacent parallel wiring, as parameters. Forming a delay table for storing values in correspondence with the above parameters; selecting a target path formed with adjacent parallel wirings from which crosstalk delay values are to be extracted; and selecting the selected target path Crosstalk delay from the above delay table using the adjacent length and parallel wiring length Wherein the determining a crosstalk delay determination method characterized by determining a crosstalk delay value target path adjacent parallel lines are formed. 2. The delay table is formed for each combination of a target gate path forming an adjacent parallel wiring and a driver gate of a source gate forming the adjacent path and a wiring shape. Crosstalk delay determination method described. 3. The adjacent parallel wiring has one source gate and one source gate.
The crosstalk delay value of the target path formed by the target path composed of the sync gate and the plurality of adjacent paths composed of one source gate and one sink gate is the crosstalk delay value of the target path and the one adjacent path. The crosstalk delay determining method according to claim 1 or 2, wherein the crosstalk delay value is determined by a crosstalk delay value that is divided into combinations and is determined from a delay table corresponding to each combination. 4. The parallel wiring length is a total value of lengths of a plurality of adjacent parallel wirings when the plurality of adjacent parallel wirings are formed by one adjacent path. 4. The crosstalk delay determination method according to any one of 3 above. 5. A permissible value of a crosstalk delay value by an adjacent parallel wiring formed by a target path formed by one source gate and one sink gate and an adjacent path formed by one source gate and one sink gate. , From the upper limit of the permissible value to the upper limit of the length of the adjacent parallel wiring which can be arranged by the driver gate of the source gate of the target path, from the output point of the source gate of the target path to the start point of the adjacent parallel wiring. A step of forming a function table that gives a function that specifies the adjacent length that is the length as a parameter, a step of selecting a target path from which the upper limit value is to be extracted, and an adjacent length of the selected target path And the driver gate driver power of the source gate of the path of interest are extracted. And a step of obtaining the upper limit of the parallel wiring length by substituting the extracted adjacent length to the selected function, and the upper limit of the adjacent parallel wiring satisfying the above allowable value. A parallel wiring length limiting method characterized by obtaining a value. 6. The adjacent parallel wiring has one source gate and one source gate.
The upper limit value of the length of the adjacent parallel wiring of the target path formed by the target path formed by the sync gate and the plurality of adjacent paths formed by one source gate and one sink gate is 6. The parallel wiring length limiting method according to claim 5, wherein the method is divided into combinations with adjacent paths, and is determined by a function selected from a function table corresponding to each combination. 7. When the plurality of adjacent parallel wirings are formed by one adjacent path, the upper limit of the length of the parallel wirings is the total value of the lengths of the plurality of adjacent parallel wirings. The parallel wiring length limiting method according to claim 5 or 6.