JPH09146999A - Logic simulation system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To enable a logic simulation system to perform logic simulation in consideration of variance of the temperature distribution in a logic circuit, and to verify logic with high precision. SOLUTION: A connection point information extracting means 6 finds how many times the logical potential level at a connection point between logic cells of the logic circuit changes in every unit simulation time while the logic simulation is performed, and a temperature predicting means 9 predicts the relative temperature of each logic cell in each unit simulation time on the basis of the frequency of the change in logical potential level and the position relation among the respective logic cells.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a logic simulation system, and more particularly to a logic circuit design support technique for supporting a logic circuit design of a semiconductor integrated circuit using a computer.

[0002]

2. Description of the Related Art In general, logic simulation in the design of a semiconductor integrated circuit refers to an input pattern which is an electrical signal for operating a circuit for circuit connection information equivalent to a logic circuit composed of logic cells. The logic is verified by confirming the operation result of the logic circuit based on the input pattern.

Further, a logic cell is a device for performing a specific electric operation such as an AND gate or an OR gate by connecting several semiconductor elements, that is, a certain electric signal is transmitted. When it is given as an input to the logic cell, an electric signal is output as an operation result corresponding to the input.

The delay time in the logic cell is the time from the input of an electric signal to the output thereof, which is an important factor in determining the movement of the entire logic circuit. Since the delay time is affected by the temperature when the operation is performed in the logic cell, it is important to confirm the operation of the logic circuit by performing the logic simulation in consideration of the temperature dependence.

Therefore, in order to perform the logic simulation in consideration of the temperature dependence of the delay time of each logic cell, conventionally, all the logic cells constituting the logic circuit are over the entire period in which the logic simulation is performed. However, the delay time is corrected by setting a constant temperature (see JP-A-5-135128).

[0006]

Generally, in a logic cell forming a logic circuit in a semiconductor integrated circuit, a load capacitance equivalently connected to its output terminal is charged / discharged in its operating state. The operation of the logic cell is accompanied by a rise in temperature due to heat generation due to the peak of the current flowing through the transistor forming the logic circuit at the time of charge / discharge and transition of the output state. It is also known that the delay time of a logic cell composed of CMOS transistors and the like increases as the temperature rises.

On the other hand, as for the semiconductor integrated circuit, the scale of the circuit and the speed of operation have been increased with the progress of the manufacturing technology. Along with this, local activation of connection points has come to occur in the logic circuit, which causes variations in temperature distribution in the logic circuit and maintains temperature uniformity in the entire logic circuit. It's gone.

Further, the variation of the temperature distribution due to this activation depends on the operation of each logic cell in the logic circuit.
It changes over time.

Therefore, in the conventional logic simulation under the temperature condition, the accurate delay time for each logic cell in the logic circuit cannot be obtained, and the simulation accuracy is deteriorated.

The present invention has been made in order to solve the above-mentioned problems, and it is possible to perform a logic simulation in consideration of variations in temperature distribution in a logic circuit, which enables highly accurate logic verification. The purpose is to obtain a possible logic simulation system.

[0011]

A logic simulation system according to the present invention (claim 1) is a logic simulation system for performing a logic simulation of a logic circuit including a plurality of logic cells in a semiconductor integrated circuit. The logic simulation system provides logic simulator means for applying an input signal, which is an electrical signal for operating the logic circuit, to circuit connection information equivalent to the logic circuit, and verifying an operation result of the logic circuit. Connection point information extracting means for determining, for each unit simulation time, the number of times the logic potential level of the connection point between the logic cells in the logic circuit changes while the logic simulation is being performed by the logic simulator means. Temperature prediction means for predicting the temperature of each logic cell at each unit simulation time based on the number of times the logic potential level has changed and the positional relationship of each logic cell. The delay time in each unit simulation time is determined from the temperature of the logic cell. Thereby, the above object is achieved.

According to a second aspect of the present invention, in the logic simulation system according to the first aspect, the connection point information extracting means is provided between the logic cells in the logic circuit based on the information from the logic simulator means. Information about the logic potential level at the connection point is stored together with time information based on the start time of the logic simulation,
Based on these pieces of information, the number of times the logic potential level at the connection point between the logic cells in the logic circuit has changed is calculated for each unit simulation time.

According to a third aspect of the present invention, in the logic simulation system according to the first aspect, the temperature predicting means is configured to calculate the logic potential level from the number of changes of the logic potential level at each connection point in each unit simulation time. Based on the temperature table for the number of changes in the potential level,
Based on the temperature determining means for determining the relative temperature of the logic cell driving each connection point and the positional relationship of each logic cell obtained from the design information of the layout of the logic circuit, the correction value of the relative temperature for each logic cell is calculated. And a correction value determining means for determining.

According to the present invention (claim 4), in the logic simulation system according to claim 1, the logic simulator means performs logic simulation for each logic cell based on information from the temperature predicting means. Recognizing the temperature of each logic cell that changes with the passage of time from the start as a parameter, and based on the table of delay time for the parameter of each logic cell stored in the logic library, each unit simulation The delay time of each logic cell in time is determined, and the logic simulation is executed based on the determined delay time.

The operation of the present invention will be described below.

In the present invention (claim 1), in the logic simulation, at each simulation time, the frequency of the state change (change of the logic potential level) at the connection point inside the logic circuit and the positional relationship of each logic cell are used. Since the temperature correction value of each logic cell is determined and reflected as the parameter for calculating the delay time in the logic simulation, the logic simulation in consideration of the variation in the temperature distribution in the logic circuit is realized,
Highly accurate logic circuit verification is possible.

Generally, in the design of a semiconductor integrated circuit, after the layout design of the logic cell, a more accurate logic simulation is performed with a more accurate delay time considering the load capacitance in the actual wiring. By applying it to such a logic simulation, a more accurate logic simulation can be performed.

In the present invention (claim 2), the connection point information extracting means is different from the activation simulation conventionally used in the design of a logic circuit, in that the state of the logic potential level of each connection point is changed to the logic state. Parameters that depend on each unit simulation time and connection point are stored because the number of changes in the state of the logic potential level at each connection point during the unit simulation time is stored together with the time when the simulation starts. To
It can be provided as a parameter when performing a logical simulation.

In the present invention (claim 3), the temperature predicting means calculates the number of changes in the state of the logic potential level at each connection point in each unit simulation time, based on the temperature table for the number of changes in this state. The relative temperature of each logic cell driving the connection point at each simulation time is determined, and the relative temperature of each logic cell is corrected based on the positional relationship of each logic cell obtained from the layout design information. Therefore, it is possible to perform the logic simulation in consideration of each unit simulation time and the position of each logic cell.

According to the present invention (claim 4), the logic simulator not only sets a certain amount of parameters for each connection point while the logic simulation is being performed, The parameters that change with the passage of time are set for each connection point, and the delay time of each logic cell at each unit simulation time is determined based on the parameters set in this way. It enables highly accurate logic simulation by delay time considering the time change of the elements that affect the electrical characteristics.

[0021]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS First, the basic principle of the present invention will be described.

In the present invention, a logic simulation is executed in advance, and a logic potential level (high level, low level, or 0 level, 1 level) at a connection point inside the logic circuit is obtained.
The relative temperature of each logic cell that drives each connection point in each unit simulation time is determined from the frequency of the change of the state. Further, the relative temperature of each logic cell determined as described above is corrected based on the positional relationship of each logic cell obtained from the layout design information of the logic circuit. And
The logic simulation is executed again using the corrected relative temperature of each logic cell as a parameter for calculating the delay time of each logic cell. As a result, a logic simulation that considers the variation in temperature distribution in the logic circuit is realized, and highly accurate verification of the logic circuit becomes possible.

The logic simulation system according to the embodiment of the present invention will be described below.

FIG. 1 is a block diagram for explaining the configuration of a logic simulation system according to an embodiment of the present invention, and FIG. 2 is a diagram showing a logic circuit which is a target of logic simulation by the logic simulation system of this embodiment. Is.

In FIG. 2, reference numeral 100 is an example of a logic circuit to be subjected to logic simulation, which is logic cells C1 to C.
It is composed of a plurality of logic cells including 3. here,
Each of the logic cells C1 to C3 has input terminals A and B and an output terminal Y. N1 to N6 are connection points that physically connect the terminals of a predetermined logic cell forming the logic circuit.

In FIG. 1, 4 is a logic simulation system of this embodiment, which is a circuit connection information file 1.
A logic simulator 5 for performing a logic simulation of the logic circuit 100 shown in FIG. 2 based on the information stored in the input pattern file 2, the information stored in the input pattern file 2, and the information stored in the logic cell library 3. Have The logic simulation 5 is performed by the logic circuit 1
For the circuit connection information equivalent to 00, the logic circuit 100
Gives an input signal that is an electrical signal for operating
The result of the operation of the logic circuit is verified.

Here, the circuit connection information file 1 is
The input pattern file 2 stores the circuit connection information of the logic circuit 100, the input pattern file 2 stores electrical signals for digitally operating the logic circuit 100, and the logic library 3 stores the logic circuit 100. It stores the electrical characteristics of each logic cell constituting the. The electrical characteristics of each logic cell include a table of delay time with respect to temperature of each logic cell.

FIG. 3 is a table showing a table of delay time with respect to temperature of each logic cell. The delay time in this table, that is, the time from the inversion of the input signal to the inversion of the output signal takes into consideration the load capacitance and the power supply voltage. In the table shown in this figure, the central column indicated by 0 → 1 indicates the delay time when the input signal is inverted from 0 level to 1 level, and the column on the right side of the paper indicated by 1 → 0 indicates The delay time when the input signal is inverted from 1 level to 0 level is shown.

Further, the logic simulation system 4 has a connection point state extracting means 6 which operates together with the operation of the logic simulator 5, and the connection point state extracting means 6 outputs the connection point state extracting means 6 from the operating logic simulator 5. The state of the logic potential level at each connection point in the logic circuit and the time when the state of the logic potential level changes are stored based on the output information, and based on this, at each connection point in each unit simulation time. The number of changes in the potential level of is output to the connection point information file 7.

FIG. 4 is a diagram showing an example of stored information of the connection point information file. In this example, the number of times the state of the logic potential level changes at the connection points N1 to N3 is shown with the unit simulation time of 200 ns in the logic simulation.

Further, the logic simulation system 4 uses the temperature correction value table (FIG. 6) for the number of state changes at each connection point in each unit simulation time to the number of state changes at each connection point in the unit simulation time. Temperature for performing the process of determining the relative temperature of the logic cell that drives the connection point and the process of determining the correction value of the relative temperature of the logic cell from the positional relationship of each logic cell obtained from the layout design information of the logic cell. It has a prediction means 9.

FIG. 5 shows the detailed construction of the temperature predicting means 9.

The temperature predicting means 9 receives information about the number of state changes of the logic potential level at the connection point in the unit simulation time from the connection point information file 7, and stores it in the temperature correction table 8 for the number of state changes. On the basis of the above, the temperature determining means M1 determines the relative temperature of each logic cell driving each connection point in each unit simulation time, and outputs the temperature as the temperature file 12.

FIG. 6 is a diagram showing an example of information stored in the temperature table 8. In this example, time 200
With ns as a unit simulation time, the number of changes in the state of the logic potential level at the connection point and the corrected temperature of the logic cell driving the connection point are stored in comparison. The correction temperature of the logic cell is represented by a relative temperature, which is 0 ° C. when the number of state changes of the logic potential level at the connection point is 0.

Further, FIG. 7 shows an example of stored information in the temperature file 12. In this example, the correction of the relative temperature of the logic cells C1 to C3 at each unit simulation time determined based on the storage information of the connection point information file 7 shown in FIG. 4 and the storage information of the temperature correction table 8 shown in FIG. Indicates the value.

The temperature predicting means 9 corrects the relative temperature of each logic cell from the position information of each logic cell obtained from the layout data file 11 and the temperature information of each logic cell in the temperature file 12. , Temperature correction value means 10 for outputting as the temperature correction value file 10. Here, the storage information of the layout data file 11 is obtained by the layout design information of the logic cell based on the storage information of the circuit connection information file 1.

FIG. 8 is a diagram showing the layout of the logic cells C1 to C3 in the layout design. FIG. 9 shows an example of the storage information of the temperature correction value file 10. The correction value of the relative temperature of the logic cell in each unit simulation time is calculated as an average value with the relative temperature of the logic cells adjacent to each other in FIG. In this example, the corrected relative temperature of the logic cells C1 to C3 is described with the unit simulation time being 200 ns in the simulation.

Next, the operation will be described.

In this logic simulation system 4, in the first logic simulation, the logic simulator 5 operates based on the circuit connection information file 1, the input pattern file 2 and the logic cell library 3. Further, the connection point information extraction means 6 operates the logic simulator 5 and, at the same time, sets the state of the logic potential level at each connection point in the logic circuit and the time when the state changes (the time when the simulation starts). The number of state changes of each connection point in each unit simulation time is stored and output to the connection point information file 7 based on the stored information. As shown in FIG. 4, this file 7 stores the number of state changes of the connection points N1 to N3, with a unit simulation time of 200 ns in the logic simulation. Then, the temperature predicting means 9 performs a process of predicting the temperature correction value of each logic cell.

First, in the first step, the temperature determining means M1 receives information on the number of state changes of the connection points in the unit simulation time from the connection point information file 7, and the temperature table 8 (FIG. 6) corresponding to the state changes. Based on the reference), the relative temperature of the logic cell driving each connection point at each unit simulation time is determined and output as the temperature file 12.

In the next step, the temperature correction means M2
The relative temperature of each logic cell is corrected based on the position information of each logic cell obtained from the layout data file 11 and the temperature information of each logic cell in the temperature file 12, and the temperature correction value file 10 (see FIG. 9) is output. Then, the first logic simulation ends.

In the second logic simulation, the logic simulator 5 uses the circuit connection information file 1,
Input pattern file 2 and logic cell library 3
A logic simulation of the logic circuit 100 is performed based on the storage information of the temperature correction value file 10 together with the storage information of.

At this time, the logic simulator 5 determines the temperature of the logic cell library 3 based on the sum of the ambient temperature and the correction value of the relative temperature of each logic cell at each unit simulation time stored in the temperature correction value file 10. The delay time of each logic cell at each simulation time is determined from the table of delay times for the simulation, and the simulation is executed.

[0044]

As described above, according to the logic simulation system of the present invention, with respect to the delay time of each logic cell forming the logic circuit in the semiconductor integrated circuit, the frequency of the state change of the logic potential level at each connection point. Since the delay time is corrected by taking into consideration the temperature change due to the positional relationship of each logic cell, the logic that considers the variation in the temperature distribution in the logic circuit is different from the logic simulation under the constant temperature condition so far. Simulation can be realized, and highly accurate logic verification is possible.

Further, by using the logic simulation system of the present invention to carry out a logic simulation in consideration of the load capacitance in the actual wiring, a more accurate logic simulation can be performed.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of a logic simulation system according to an exemplary embodiment of the present invention.

FIG. 2 is a diagram showing an example of a configuration of a logic circuit which is a target of a logic simulation by the logic simulation system of the present embodiment.

FIG. 3 is a diagram showing an example of a table of delay time with respect to temperature of each logic cell.

FIG. 4 is a diagram showing an example of information stored in a connection point information file 7 which constitutes the logic simulation system.

FIG. 5 is a diagram showing a detailed configuration of temperature predicting means 9 constituting the logic simulation system.

FIG. 6 is a diagram showing an example of information stored in a temperature correction table 8 constituting the logic simulation system.

FIG. 7 is a diagram showing an example of information stored in a temperature file 12 which constitutes the logic simulation system.

FIG. 8 is a diagram showing an arrangement of each logic cell in the logic circuit, which is obtained from layout design information.

FIG. 9 is a diagram showing an example of information stored in a temperature correction value file 10 which constitutes the logic simulation system.

[Explanation of symbols]

 1 Circuit Connection Information File 2 Input Pattern File 3 Logic Cell Library 4 Logic Simulation System 5 Logic Simulator 6 Connection Point Information Extraction Means 7 Connection Point Information File 8 Temperature Correction Table 9 Temperature Prediction Means 10 Temperature Correction Value File 11 Layout Data File 12 Temperature file 100 Logic circuit M1 Temperature determination means M2 Temperature correction means

Claims (4)

[Claims] 1. A logic simulation system for performing logic simulation of a logic circuit including a plurality of logic cells in a semiconductor integrated circuit, for operating the logic circuit with respect to circuit connection information equivalent to the logic circuit. The input signal which is the electrical signal of
Logic simulator means for verifying the operation result of the logic circuit, and the number of times the logic potential level at the connection point between the logic cells in the logic circuit changes during the logic simulation by the logic simulator means. Connection point information extraction means for each unit simulation time, and temperature prediction means for predicting the temperature of each logic cell at each unit simulation time based on the number of times the logic potential level has changed and the positional relationship of each logic cell. And a logic simulation system configured to determine the delay time in each logic cell in each unit simulation time from the predicted temperature of the logic cell. 2. The logic simulation system according to claim 1, wherein the connection point information extraction means relates to a logic potential level of a connection point between each logic cell in the logic circuit based on information from the logic simulator means. Information is stored together with time information based on the start time of the logic simulation, and based on these information, the number of times the logic potential level at the connection point between the logic cells in the logic circuit changes is calculated as the unit simulation. A logic simulation system that is obtained every hour. 3. The logic simulation system according to claim 1, wherein the temperature predicting means calculates the temperature from the number of changes in the logical potential level at each connection point in each unit simulation time to the number of changes in the logical potential level. Relative to each logic cell based on the table, the temperature determining means for determining the relative temperature of the logic cell driving each connection point, and the positional relationship of each logic cell obtained from the design information of the layout of the logic circuit. And a correction value determining means for determining a correction value of temperature. 4. The logic simulation system according to claim 1, wherein the logic simulator means, based on information from the temperature predicting means, elapses from the start of the logic simulation for each logic cell. The temperature of each logic cell that changes with is recognized as a parameter, and the delay time of each logic cell at each unit simulation time is based on the table of delay time for each parameter stored in the logic library. And a logic simulation system for executing a logic simulation based on the determined delay time.