JPH09146555A - Waveform memory sound source device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To enable accessing a waveform memory efficiently for every channel by required quantity when required by buffering an address and a waveform sample to an address storage means and a sample storage means. SOLUTION: A waveform read-out interpolation circuit 102 generates successively read-out addresses of a waveform memory 208. Read-out addresses are values that specified read-out pitches are successively totaled from the start of a specified read-out section. Especially, in this sound source section 207, a sample RAM being a sample buffer is provided in a decoder 104, only a required number of waveform samples (waveform data) are read out from the waveform memory 208 for every channel, and the number of times of accessing waveform memories in each channel are variable. Read-out timing of a waveform sample can be adjusted properly, and continuous access can be performed corresponding to the speed of a waveform memory.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a tone generator for generating and outputting digital tone waveform data.
The present invention relates to a waveform memory tone generator that allows a waveform memory to be accessed only when necessary in a tone generator that reads the waveform memory on multiple time-division channels.

[0002]

2. Description of the Related Art Conventionally, there has been known a waveform memory sound source which simultaneously generates musical tones for a plurality of channels by time division channel operation. In such a sound source, a tone generation operation of each channel is performed in a time slot of each channel obtained by equally dividing one sampling period. Similarly, access to the waveform memory is a time-division channel operation, and for each channel, access is performed a fixed number of times in a time slot corresponding to the channel.

Further, the sound source of the waveform memory reading system is provided with an interpolation circuit, and performs an interpolation calculation using several consecutive samples (waveform data) for each channel.
There is one that obtains musical tone waveform data for a point. In addition, the interpolation circuit has a sample buffer,
There is a waveform memory sound source that enables high-order interpolation calculation. This is because the waveform data read from the waveform memory is stored in the sample buffer, and when the waveform memory is being read, if there is little advance in the address, the waveform data stored in the sample buffer and the newly read The interpolation is performed by using the waveform data.

[0004]

As described above, in the waveform memory sound source which simultaneously generates musical tones for a plurality of channels in the time-division channel operation, the waveform memory access is fixed at a fixed number of times for each channel. Has been. In general, according to the waveform read speed (F number) of each channel, etc., and for each sampling cycle,
Although the required number of times of accessing the waveform memory is different, the conventional technique has not done so, and the limited operation speed (accessible number) of the waveform memory has not been effectively utilized.

In the method using the sample buffer, the data in the sample buffer can be effectively used for interpolation when the advance of the address is small, but when the advance of the address is large, all necessary waveform data must be read out. However, the interpolation order may be lowered (for example, 4-point interpolation is changed to 2-point interpolation).

According to the present invention, in a sound source of a waveform memory reading system which simultaneously generates musical tones for a plurality of channels by time division channel operation, the waveform memory can be efficiently accessed by each channel when needed. The purpose is to do so.

[0007]

The invention according to claim 1 of the present invention is a waveform memory sound source device for generating musical sounds of a plurality of channels by operating in a time-divisional manner in a plurality of channels at a predetermined sampling period. A waveform memory that stores a waveform sample of each channel, a waveform memory that can be accessed a predetermined number of times within the predetermined sampling period, an address storage unit that stores an address of each channel, and a waveform that stores a waveform sample of each channel. Based on the sample storage means, the address creation means for creating the address of each channel prior to the reading of the waveform memory, and storing the address in the address storage means, and the advance amount of the address of each channel, An access count calculating means for calculating the access count of the waveform memory; Based on the address of each channel stored in the storage means, the waveform memory is continuously accessed for each access count of each channel calculated by the access count calculation means, and the read waveform sample of each channel is the waveform sample. First stored in storage means
It is characterized by further comprising access means and tone generation means for generating a tone for each sampling period of each channel based on the waveform sample of each channel stored in the waveform sample storage means.

According to a second aspect of the present invention, there is provided a waveform memory sound source device for generating musical tones of a plurality of channels by operating in a time-divisional manner in a plurality of channels at a predetermined sampling cycle.
One that can be accessed a predetermined number of times within the predetermined sampling period, address storage means for storing the address of each channel, and n (n is 2) for each channel.
(The above integer) waveform sample storage means for storing waveform samples, address creating means for creating addresses for each channel prior to reading the waveform memory, and storing the addresses in the address storage means, and An access number calculating means for calculating a required number of times of access to the waveform memory for each channel based on the amount of advance of the address, and the access number calculating means for calculating the number of times of access to the waveform memory on the basis of the address of each channel stored in the address storage means. The waveform memory is continuously accessed by the number of times of access of each channel calculated in step 1, and n of each channel already stored in the waveform sample storage means is accessed.
The first access means for replacing the waveform samples with the smallest addresses in the plurality of waveform samples with the waveform samples of the respective channels read by the continuous access, and the n number of n-number of the respective channels stored in the waveform sample storage means. And a tone generation means for generating a tone for each channel sampling period by performing an interpolation process using the waveform sample.

The invention according to claim 3 is the invention according to claim 1 or 2.
In the waveform memory sound source device according to the above paragraph, the sampling cycle is divided into m (m is an integer of 2 or more) sections, and the first access means should process in each of the divided sections. The waveform memory is continuously accessed for a plurality of channels. It is desirable that the sampling period be equally divided into the first half and the second half.

[0010] The invention according to claim 4 is the invention according to claim 1 or 2.
In the waveform memory tone generator according to claim 1, the waveform data of the waveform memory is composed of an attack section and a loop section, and the address creating means includes a loop section from an attack section of the waveform data whose created address is to be read on the channel. When it enters, the advancing address is returned in the opposite direction to repeatedly create the same address in the loop portion for each cycle of the loop portion of the waveform data, and the access count calculation means executes the return of the address. If
With respect to the channel, a predetermined number of times of access is designated regardless of the amount of advance of the address.

[0011] The invention according to claim 5 is the invention according to claim 1 or 2.
The waveform memory tone generator according to claim 1, further comprising second access means for performing at least one of reading and writing of the waveform memory, the second access means comprising:
The remaining time after the waveform memory is accessed by the first access means is used to access the waveform memory. The second access means is, for example, for refreshing when the waveform memory has a DRAM structure or for accessing the waveform memory by the CPU.

According to a sixth aspect of the present invention, there is provided a waveform memory sound source device for generating musical tones of a plurality of channels by operating in a time-divisional manner on a plurality of channels at a predetermined sampling cycle.
A unit that can be accessed a predetermined number of times within the predetermined sampling period, an address storage unit that stores the address of each channel, a waveform sample storage unit that stores the waveform sample of each channel, and the waveform memory An access for creating an address of each channel prior to reading and storing the address in the address storage means, and an access for calculating the number of times the waveform memory is accessed for each channel based on the advance amount of the address of each channel. A number-of-times calculating means, an accumulating means for accumulating the number of times of access calculated by the number-of-accesses calculating means for a predetermined number of channels, and outputting the accumulated number of times, and within an access period corresponding to the predetermined number of channels, Determining means for determining whether or not access for the accumulated number of times is possible; Is determined to be possible, the waveform memory is continuously accessed and read for each access count of each channel calculated by the access count calculation unit based on the address of each channel stored in the address storage unit. First access means for storing the waveform sample of the channel in the waveform sample storage means, and tone generation means for generating a tone for each channel sampling period based on the waveform sample of each channel stored in the waveform sample storage means. It is characterized by having and.

According to a seventh aspect of the present invention, in the waveform memory sound source device according to the sixth aspect, the sampling period is divided into m (m is an integer of 2 or more) intervals, and the accumulating means is For each divided section, the access count is accumulated for a plurality of channels to be processed in the section, and the determination means makes the determination for each divided section as the access period. First
The access means is configured to continuously access the waveform memory for each of the divided sections with respect to a plurality of channels to be processed in the section. It is desirable that the sampling period be equally divided into the first half and the second half.

According to an eighth aspect of the present invention, in the waveform memory sound source device according to the sixth aspect, when the determination means determines that the determination is impossible, access is made to any one of the predetermined number of channels. This is to reduce the number of times.

According to a ninth aspect of the present invention, in the waveform memory tone generator according to the sixth aspect, the waveform memory tone generator further comprises second access means for performing at least one of reading and writing of the waveform memory, and the determining means determines that the waveform memory sound source is possible. If so, the second access means uses the portion of the total number of accesses within the access period that has not been used in the access by the first access means to access the waveform memory. It is a thing. The second access means is, for example, for refreshing when the waveform memory has a DRAM structure or for accessing the waveform memory by the CPU.

[0016]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings.

FIG. 2 shows the overall block configuration of an electronic musical instrument to which the sound source device according to the present invention is applied. 1 is shown in FIG.
2 shows a block configuration of a sound source section of the electronic musical instrument of FIG. 1 and 2, the same numbers indicate the same things.

First, the overall configuration of this electronic musical instrument will be described with reference to FIG. This electronic musical instrument includes a keyboard 201, a display unit 202, a switch group (SW) 203, a central processing unit (CPU) 204, and a read only memory (ROM) 20.
5, random access memory (RAM) 206, tone generator 207, waveform memory 208, digital-analog converter (DAC) 210, sound system (SS) 211,
An external storage device 212 and a bus 213 are provided.
Keyboard 201, display unit 202, switch group 203, CPU
204, ROM 205, RAM 206, sound source unit 207,
The external storage device 212 and the external storage device 212 are connected to each other by a bus 213.

The keyboard 201 is a keyboard provided with a plurality of keys for a user to perform a performance operation. The display unit 202 is provided on the panel of the electronic musical instrument and displays various kinds of information. The switch group 203 is provided on the panel,
By operating this, the user can give various instructions to the electronic musical instrument. The CPU 204 controls the operation of the entire electronic musical instrument. In particular, during a normal performance, the operation of the keyboard 201 is detected, and the sound source unit 207 is instructed to sound according to the operation. ROM 205 is a CPU
Stores programs executed by the sound generator (such as a sound source control program for controlling the sound source unit 207) and various constant data. The RAM 206 is used as a work register or the like. The external storage device 212 includes a DRAM, which will be described later.
Waveform data and the like to be loaded into the configured waveform memory 208 are stored.

In response to an instruction from the CPU 204, the sound source unit 207 reads out waveform data from the waveform memory 208, performs processing such as interpolation, envelope addition, channel accumulation, and effect addition, and outputs it as tone waveform data. The musical tone waveform data output from the sound source unit 207 is D
It is converted into an analog signal by the AC 210 and is emitted by the sound system 211.

The waveform memory 208 is composed of a DRAM (dynamic RAM). Waveform memory 208
Stores waveform sample data sampled at a predetermined rate. The waveform sample data is
Although it may be read from the external storage device 212 and stored in the waveform memory 208 prior to the generation of musical tones, it is not particularly used in the tone generator of this embodiment when performing the musical tone generating operation for a plurality of channels. Since the empty time slot can be used for other purposes,
The waveform data may be read from the external storage device 212 and stored in the waveform memory 208 by using the empty time slot during the operation of generating a tone.

Next, the sound source unit 207 will be described in detail. In FIG. 1, the sound source unit 207 is a control register 10
1, address generator 102, interpolator 103, decoder 1
04, volume change control unit 105, channel (ch) accumulator 106, effect circuit 107, refresh counter 10
8, a CPU access control unit 109, a selector 110, a selector 111, a system clock generation unit 112, and a channel (ch) counter 113.

The control register 101 includes designation information (sound source section 207) for a plurality of channels sent from the CPU 204.
Is a control register for storing an instruction and parameter information). The CPU 204 sets predetermined designation information in the control register 101 for each sounding channel and issues a sounding start instruction. The designation information to be set includes designation information such as a memory read pitch (frequency number), a memory read section, a waveform data compression method, an envelope, and an effect coefficient.

When the tone generation start instruction is received, the tone generator section 207 starts the operation of generating a tone waveform. First, the address generator 102 sequentially generates read addresses of the waveform memory 208. The read address is a value obtained by sequentially accumulating the designated read pitch from the beginning of the designated read section. In particular, this sound source unit 207 is the decoder 1
04, a sample RAM as a sample buffer is provided, and only the required number of waveform samples (waveform data) are read from the waveform memory 208 for each channel, so that the number of waveform memory accesses for each channel can be changed. It has become. Therefore, the address generator 102 is configured to sequentially output the addresses of the waveform memory according to the number of times of access of each channel at a timing different from the time division channel timing.

An empty time slot is obtained by outputting the address from the address generator 102 at a timing different from the time division channel timing. The refresh counter 108 and the CPU access control unit 109 refresh the waveform memory 208 in this empty time slot, or the CP
It is for accessing the waveform memory 208 from U204. The selectors 110 and 111 use the refresh counter 108 and the CP in empty time slots.
The U access control unit 109 is controlled to connect to the waveform memory 208.

The read address generated by the address generator 102 is passed through the selector 110 to the waveform memory 208.
Waveform data is read from the waveform memory 208. The decoder 104 receives the waveform data via the selector 111 at the timing when the address generator 102 sends out the address. In this embodiment, the compression method of waveform data is 16-bit uncompressed, 8
Either bit uncompressed or 8-bit compressed. Therefore, the decoder 104 decodes the uncompressed waveform as it is, and decodes the compressed waveform and stores it in the sample RAM.

The interpolator 103 reads the waveform data of each channel from the sample RAM in the decoder 104,
Interpolation processing (basically, 4-point interpolation is performed, and 2-point interpolation is performed only when waveform data for 4 points cannot be secured). The volume change control circuit 105 adds an envelope to the tone waveform data of each channel. Channel accumulator 106
Is for accumulating the tone waveform data of each channel. The effect circuit 107 adds various effects to the result of channel accumulation. The musical tone waveform data to which the effect is applied is input to the DAC 210 of FIG. 2 to be converted into an analog signal, which is then emitted by the sound system 211.

The sound source section 207 operates on 32 channels in time division. The system clock 112 is a sound source unit 207.
A control clock signal Φ serving as a reference signal for performing a time-division operation is supplied to each section therein. Channel counter 11
3 counts the channel count value CHC for performing the time-division channel operation (specifically, repeats 0 to 31) and supplies it to each block in the sound source unit 207.

Next, with reference to FIGS. 3 and 4, an outline of the timing of the main parts in the sound source unit 207 of this embodiment will be described. In FIG. 3, “Processing A” indicates a section of the process performed by the address generator 102, in which the process of creating the address of each channel is performed. “Processing B” indicates a section of the processing performed by the address generator 102, in which the processing for sending the address to the waveform memory 208 is performed. “Decode” indicates a processing section of the decoder 104, particularly a section in which processing for receiving the waveform data output from the waveform memory 208 is performed. “Interpolation” indicates a processing section of the interpolator 103. In each processing section, one sampling cycle is divided into the first half and the latter half, and the first half performs the processing of channels 0 to 15, and the latter half performs the processing of channels 16 to 31.

FIG. 4 shows the state of the channel during each processing of FIG. "Processing A first half ch" of FIG. 4 is the section 3 of FIG.
The state of the channel in 01 is shown. “Processing B” in FIG.
The “first half ch” indicates the state of channels in the section 302 of FIG. The “first half channel of decoding” in FIG. 4 shows the state of channels in the section 303 of FIG. The “first half channel of interpolation” in FIG. 4 shows the state of channels in the section 304 of FIG. In FIG. 4, the timings of the respective channels are vertically arranged and aligned, but the timings of the respective processes are actually shifted as shown in FIG.

In this embodiment, as can be seen from FIG.
The address generation process A by the address generator 102 and the interpolation process by the interpolator 103 operate in synchronization with the time-division channel timing in the sound source. on the other hand,
Process B of sending address from address generator 102
The processing of receiving the waveform data by the decoder 104 operates at a timing independent of the time division channel timing (specifically, by the control of the processing B control unit in FIG. 5 described later).

For example, in FIG. 3 and FIG.
In the first half section 301, the address generator 102
Addresses of the respective channels are created in order according to the time division channel timing for the 0th to 15th channels. In the section 302 in the first half of the process B, the address generator 102 causes one address of the 0th channel to be output at a timing different from the time division channel timing.
The addresses of the 0th to 15th channels are sent out in such a manner that three addresses of the second channel, one address of the fifth channel, and so on. The time width of the section for sending out one address is half the time width of the section for processing one channel at the time division channel timing. The number of addresses to be sent out in each channel is different because the past waveform data is held in the sample RAM in the decoder 104 and it is sufficient to read only the required number of waveform data for each channel, or This is because there is a channel that does not need to be pronounced and does not need to send out an address. In this case (FIG. 4), the 0th channel requires 1 access, the 2nd channel requires 3 accesses, the 5th channel requires 1 access, and the 7th channel requires 2 accesses. There is. The other channels are channels that are not sounding or that can generate musical tones only with the samples that have already been read and stored in the waveform buffer 307. Note that a channel not sounding is a channel whose volume level is lowered, such as EG, and the channel is controlled so that the access timing of the waveform memory in the process B is not used.

In the first half section 303 of the decoding, the waveform data read from the waveform memory 208 is received in accordance with the address sending timing of the first section 302 of the process B. The decoder 104 will be described in detail later.
When the received waveform data is a compressed waveform, it decodes it, and when it is an uncompressed waveform, it writes it to the internal sample RAM as it is. The interpolator 103 performs interpolation processing on the 0th to 15th channels using the data of the sample RAM in accordance with the time division channel timing in the first half section 304 of the interpolation. At the time of performing the interpolation for a certain channel, the waveform data of the channel required for performing the interpolation is prepared in the sample RAM.

As described above, musical tone waveform data of channels 0 to 15 are generated. The same applies to the 16th to 31st channels processed using the latter half section.

An empty time slot appears by performing the address sending process B in the address generator 102 and the waveform data receiving process in the decoder 104 at a timing different from the time division channel timing. In the sections 302 and 303 of FIG. 4, “-
“Ch” indicates an empty time slot that is not used for sample reading of any channel. This empty time slot section can be used arbitrarily. In the present embodiment, the refresh counter 108 of FIG. 1 refreshes the waveform memory 208 or the CPU access control unit 109 accesses the waveform memory 208 during the empty time slot.

Next, the address generator 102 will be described in detail. FIG. 5 shows a block configuration of the address generator 102. The address generator 102 has a selector 50.
1, 502, 503, adder 504, shifter 505, vibrato modulator 506, octave (OCT) shifter 5
07, read integer part latch 508, integer part latch (ILAT) 509, decimal part latch (FLAT) 51
0, an address RAM 511, an integer part combining unit 512, an interpolating decimal part latch 513, a control unit A 514, a processing B control unit 515, and a control RAM 517. Processing B
An accumulator (ACC) 51 is provided inside the control unit 515.
6 are provided.

In FIG. 5, selectors 501, 502,
Reference numerals 503 are selectors for selecting and outputting a predetermined input in each time division time slot. Adder 5
Reference numeral 04 denotes a 23-bit adder that inputs the selection output data of the selector 501 and the selection output data of the selector 502 and executes addition. In this adder 504, there is a delay of 2 clocks before the addition result is output, and therefore it is described as “2D”. The shifter 505 is an adder 50
The addition result of 4 or the decimal part data of the decimal part latch 510 is shifted and output. The shift amount of the shifter 505 is variable. The integer part latch (ILAT) 509 is a 23-bit latch, and the decimal part latch (FLAT) 510 is a 9-bit latch.

FIG. 6 shows a memory map of the address RAM 511 of FIG. The address RAM 511 is composed of areas for each of the 0th to 31st channels and stores the current address value of each channel in these areas. The area of each channel is composed of an address upper ADH and an address lower ADL. The size of each of the ADH and ADL areas is 16 bits. A 32-bit address value that is a combination of the upper address ADH and the lower address ADL is divided into an integer part and a decimal part. The address integer part corresponds to the address of the waveform memory 208. That is, corresponding to one value of the address integer part,
There is one sample (waveform data) in the waveform memory 208. The fractional address part indicates a unit smaller than that, and is information used in the interpolation process using waveform data of some points. The address integer part has 23 bits, and the address decimal part has 9 bits. Therefore, the address RAM 511
The ADH of each channel indicates the upper 16 bits of the 23-bit address integer part, and the ADL indicates 16 bits that are the lower 7 bits of the 23-bit address integer part and the 9 bits of the address fraction part. Become.

The symbol attached to the area indicates the area itself and also the data stored in the area. For example, the address lower ADL indicates the area itself for storing the lower 16 bits of the current address value and also indicates the lower data of the address value stored in the area. The same applies to the symbols attached to the respective areas.

In FIG. 5, the integer part synthesis unit 512 reads out the address value of an arbitrary channel of the address RAM 511 and outputs the decimal part or the integer part. Specifically, when the fractional part of the address is output, the address RA
The lower ADL of M511 is read and the lower 9 bits are output as the address fractional part. When outputting the address integer part, the upper 7 bits of ADL, that is, the lower 7 bits of the address integer part, are first fetched, then the upper 16 bits of the address integer part of ADH are fetched, and they are combined to form a complete 23-bit address. Generates and outputs the integer part.

The control unit A 514 inputs the clock Φ and the channel count value CHC, creates control signals for controlling all the operations of the processing A and the basic operations of the processing B (described later in FIG. 8), and each block Supply to. Process B control unit 5
Reference numeral 15 controls each block in order to perform the process B described in FIGS. In particular, the process B control unit 515
In the first half of the process B (302 in FIG. 3), the 0th to 15th 1
Accumulator 516 accumulates the access counts for 6 channels and accumulates the access counts for 16th to 31st channels in the latter half of the process B (306 in FIG. 3). It is for storing the accumulated value. The operation of the process B control unit 515 and the accumulator 516 will be described in detail later.

FIG. 8 shows a timing chart of the address generator 102 of FIG. Each section separated by a vertically drawn dotted line represents a time slot of 1 clock. FIG. 8 is a diagram in which 2 channel times of the operation of 1 DAC cycle of 384 clocks (12 clocks × time-division 32 channels) are taken out. Slot numbers (0 to 11) are sequentially assigned to each section of 12 clocks for one channel. In FIG. 8, a section in which a series of slot numbers 0 to 11 is surrounded by a square is a section for one channel.

The numbers 1 to 6 in the line labeled "Process A" correspond to the process numbers below, and the process of the process number is performed in the time slot in which the process number is described. For example, regarding process A, the position of slot number 0 is described as "1", and the position of slot number 2 is described as "2". It indicates that the process of No. 1 is performed and the process of the following process number 2 is performed in the slot of slot number 2. Regarding the process A, an address for one channel is created in 6 clocks. Hereinafter, referring to FIG. 8 and FIGS. 5 and 6, the address generator 1
Process number 1 of process A for creating address in 02
The process of 6 will be described.

1. In the process number 1, the selector 501 is P
ITCH is selectively output, and the selector 502 selectively outputs LTUNE. PITCH indicates the pitch within the octave, and is designated by the CPU 204 via the control register 101. LTUNE indicates loop tune. The waveform data stored in the waveform memory 208 is divided into an attack portion and a loop portion, and LTUNE is 0 while the attack portion is being read. When entering the loop section from the attack section, the pitch value may differ between the attack section and the loop section, so loop tune L as an offset
The pitch is adjusted by adding TUNE to the pitch PITCH. In LTUNE, the CPU 204 controls the control register 1
Specify via 01.

The adder 504 uses PITCH + LTUNE
Is calculated. The addition result VIBM is output after two clocks and input to the vibrato modulator 506. The vibrato modulator 506 performs a process of adding the fluctuation amount in order to add a slow temporal frequency fluctuation to the musical sound. The result of vibrato modulation is the octave shifter 5.
Input to 07 and shift by octave. The OCT input to the octave shifter 507 indicates a shift amount for an octave, and is designated by the CPU 204 via the control register 101.

The output of the octave shifter 507 is input to the selector 501 as the pitch PITX. The pitch PITX is the advance value (frequency number) of the address on the channel. Actually, the addition result VIBM calculated in the slot of the processing number 1 of the previous channel timing is processed by the vibrato modulator 506 and the octave shifter 507 and used as the pitch PITX of the processing number 2 of the channel timing.

2. In the process number 2, the selector 501 selects and outputs the pitch PITX output from the octave shifter 507, and the selector 502 outputs the address fractional part ARAM (ADF) of the channel from the address RAM 511.
Is selected and output. The integer part synthesis unit 512 prepares the ARAM (ADF). That is, the integer part combining unit 512
ADL related to the channel of the address RAM 511
Is read out, and only the fractional part of the address of the lower 9 bits is taken out and input to the selector 502 as the fractional part of the address ARAM (ADF). At the same time, the integer part combining unit 512
Is the address integer part ARAM (AD
The lower bit of I) is acquired in the internal register.

The adder 504 uses ARAM (ADF) + P
Calculate and output ITX. The addition result UD is output after 2 clocks and used in the next processing number 3 via the shifter 505. Furthermore, the result of this addition is the fractional part latch (FL
AT) 510, and the lower 9 bits are latched.
This is the new data for the fractional part of the address. The data of the address decimal part of the decimal part latch 510 is later written to the lower 9 bits of the ADL of the address of the address RAM 511 via the selector 503. Further, the integer part (overflow value) of the UD at this time is taken into the process B control unit 515 as the number of samples to be read according to the new address.

3. In the process number 3, data UD ↓ 9 (* bit downshifted data is represented as UD ↓ *) in which the addition result UD of the process number 2 is downshifted by 9 bits in the shifter 505 is input to the selector 501. Upon inputting, the selector 501 selects and outputs this data UD ↓ 9. The selector 502 selects and outputs the address integer part ARAM (ADI) of the channel of the address RAM 511. The ARAM (ADI) is an integer part synthesis unit 51.
2 prepared. That is, the integer part synthesizing unit 512 first reads the ADL of the channel of the address RAM 511 by processing number 2 and extracts the high-order 7 bits, then reads the ADH of the channel by processing number 3, and sets A
16 bits of DH and ADL upper 7 extracted earlier
Bit integer and ARAM (AD
Obtain I). The integer part combining unit 512 performs a process of combining the address integer parts in advance, and outputs ARAM (ADI) at the timing of this process number 3.

The adder 504 is ARAM (ADI) + U
Calculate D ↓ 9. UD ↓ 9 (integer part = overflow value described above) is processed number 2 and pitch PITX is added to the address decimal part.
In the addition result obtained by adding (advance value of address), this corresponds to the overflow above 9 bits of the address fractional part, so ARAM (ADI) + UD ↓ 9 adds the overflow to the address integer part. It is a calculation. This addition result UD
Is output after 2 clocks and is used in the next processing number 4 via the shifter 505. Further, the addition result is input to and latched in the integer part latch (ILAT) 509. This is the data of the new address integer part. The data of the address integer part of the integer part latch 509 will be stored in the selector 5 later.
It is written in ADH and ADL upper 7 bits of the address of the address RAM 511 via 03.

4. In the process number 4, the addition result UD of the process number 3 is directly input to the selector 502 (the shift amount of the shifter 505 is 0), and the selector 502 selectively outputs this data UD. Selector 501 is -LPLEN
Is selected and output. -LPLEN is a data length LPLEN of the loop portion of the waveform data to be read, which is negatively added. -LPLEN is CPU20
4 designates via the control register 101. Adder 20
8 calculates -LPLEN + UD and outputs the addition result after 2 clocks.

The waveform data in the waveform memory 208 is composed of an attack portion and a loop portion that follows it. When accessing the waveform data, the beginning position of the loop portion (that is, the final position of the attack portion) is set to the address 0. The standard of. Therefore, when -LPLEN + UD becomes positive (when a carry is not generated), the address value has exceeded the loop unit final position, and in this case, the address must be returned to the beginning of the loop unit. Therefore, when a carry occurs when the process number 4 is added, the following process numbers 5 and 6 are performed.
If the carry does not occur, the following processing numbers 5 and 6 are performed to return to the address near the beginning of the loop portion.

5. In process number 5, the addition result UD (new address integer part) of process number 4 and the address fraction part of the fraction part latch (FLAT) 510 are combined 32.
A bit address value UD (I & FLAT) is generated (this data is generated by the shifter 505), and the selector 50
2 selects and outputs this data UD (I & FLAT). Further, the selector 501 selects and outputs the loop fraction part data LPFR. The LPFR is designated by the CPU 204 via the control register 101. Adder 208
Calculates UD (I & FLAT) + LPFR and outputs the addition result after 2 clocks.

The loop fraction part data LPFR is offset data for correction when returning to the vicinity of the beginning of the loop part.
In processing number 4, -LPLEN was added to the address integer part to calculate the return address for the integer part. However, when returning to the vicinity of the beginning of the loop part, it is necessary to adjust the decimal part. Address value UD (I &
Loop fractional part data LPFR is added to (FLAT),
Subtle return address adjustments are made.

The addition result of the process number 5 is input to the fractional part latch (FLAT) 510, and the lower 9 bits are latched. This is the new data for the fractional part of the address. The data of the address decimal part of the decimal part latch 510 is written to the lower 9 bits of the ADL of the address of the address RAM 511 via the selector 503.

6. In the process number 6, the data UD ↓ 9 obtained by downshifting the addition result UD of the process number 5 by 9 bits by the shifter 505 is input to the selector 502, and the selector 502 selectively outputs the data UD ↓ 9. The selector 501 selectively outputs -AS. -AS indicates data that is the initial value of the address integer part at the time of note-on rising and is 0 at other times. -AS is the CPU 20
4 designates via the control register 101. Adder 50
4 calculates -AS + UD ↓ 9 and outputs the addition result after 2 clocks. The result of this addition is the integer part latch (IL
AT) 509 and latched. This is the data of the new address integer part. The data of the address integer part of the integer part latch 509 is transferred to the ADH and ADL of the address of the address RAM 511 via the selector 503.
It is written in the upper 7 bits.

In summary, in the process number 6, the address integer part obtained by downshifting the addition result UD (new address value) of the process number 5 by 9 bits is used in the integer part latch 509 and the address RAM 51 except when the note-on is started.
Write to 1. Then, when the process number 6 is executed at the rising of the note-on (UD is 0 at this time), the initial value of the address integer part is written to the address RAM 511 via the integer part latch 509. As described above, since the waveform data has the reference address 0 at the beginning of the loop portion, the beginning address of the attack portion is a negative number -AS. Therefore, it is necessary to write this initial value in the address RAM 511 when the note-on rises.

After that, the processing number 1 to the processing number 6 described above are executed in the sampling cycle, so that the RAM 5
The address written in 11 is gradually changed from the attack part start address to the loop part start address, and then repeatedly changed from the loop part start address to the loop part end address.

As described above, the process numbers 1 to 6 are executed at the timing shown in the process A of FIG. 8 to create the address value of each channel on the address RAM 511. An outline of the above-mentioned processing A is shown below for each processing number only by the formula.

1. PITCH + (LTUNE) → VIBM 2. ARAM (ADF) + PITX → UD, FLAT →
ARAM 3. ARAM (ADI) + UD ↓ 9 → UD, ILAT →
ARAM 4. -LPLEN + UD → UD (I & FLAT) 5. (UD (I & FLAT) + LPFR → UD, FLA
T → ARAM) 6. ((-AS) + UD ↓ 9 → ILAT → ARAM)

However, the LTUNE of the process number 1 is parenthesized to show that it is 0 except the loop part (attack part). Similarly, -AS of process number 6 is parenthesized to indicate that it is 0 except when the note-on is rising. Since the process numbers 5 and 6 are executed only when the carry number is not generated in the process number 4, parentheses are attached to the whole.

Next, the address sending operation of the process B will be described. Before actually performing the processing for sending out the address from the address generator 102 in FIG. 5 at the timing shown in processing B in FIG. 8, the processing B control unit 515 performs the preprocessing for sending out the address. FIG. 10 is a flowchart showing the operation of the preprocessing. Address generator 1
02 is performing the process A for the first half of channels 0 to 15 (section 301 in FIG. 3), the process B control unit 515 performs the process A shown in FIG. Perform the operation of. Further, when the address generator 102 is executing the process A regarding the 16th to 31st channels of the latter half (section 30 in FIG. 3).
5), the process B control unit 515 performs the operation of FIG. 10 as a preprocess for sending out the addresses of the 16th to 31st channels. Hereinafter, the processing related to the 0th to 15th channels will be referred to as the first half processing, and the processing related to the 16th to 31st channels will be referred to as the second half processing.

In FIG. 10, in step 1001,
The first half / second half accumulator (ACC) 516 inside the process B control unit 515 is initialized (cleared to zero). As the accumulator (ACC) 516, the 0th
A first half accumulator for accumulating the waveform memory access count for the 15th channel and a second half accumulator for accumulating the waveform memory access count for the 16th to 31st channels are independently provided.
If the process A which is being executed in parallel is the process of creating the addresses of the first half channels 0 to 15, the first half accumulator is initialized and the addresses of the latter half channels 16 to 31 are set. If the process of creating is done, the latter half accumulator is initialized. In the following description of FIG. 10, when simply referring to “accumulator ACC”, it is assumed that the first half processing refers to the first half accumulator, and the second half processing refers to the second half accumulator.

The step 1002 does not perform any processing, but the following steps 1003 to 1008 are performed.
This means focusing on the first channel as the target channel (hereinafter referred to as the target channel) for performing. The first channel is the 0th channel in the first half processing and the 16th channel in the second half processing.

Next, in step 1003, for the target channel, the channel number, compression method, number of samples, and address least significant bit are received. The channel number can be known from the count value CHC from the channel counter 113.

The compression method received in step 1003 is the compression method of the waveform data of the target channel to be read, and is either 16-bit uncompressed, 8-bit uncompressed, or 8-bit compressed. The compression method may be different for each channel. The compression method for each channel can be known by referring to the information set in the control register 101 by the CPU 204.

FIG. 9A shows 16 waveforms in the waveform memory 208.
The format of the bit uncompressed waveform data is shown. 90
Reference numerals 1 to 906 each represent one sample of 16-bit uncompressed waveform data. Since the addresses are assigned in sample units, assuming that the sample 901 is the reference position of the address 0, the addresses of the samples 902, 903, 904, ... Are 1, 2, 3 ,. In FIG. 9 (b),
8 shows a format of 8-bit uncompressed or 8-bit compressed waveform data in the waveform memory 208. 911-922
Indicate one sample of 8-bit uncompressed or compressed waveform data, respectively. Since the addresses are assigned in sample units, assuming that the sample 911 is the reference position of the address 0, the addresses of the samples 912, 913, 914, ... Are 1, 2, 3 ,. Waveform memory 208
The waveform data can be accessed regardless of the compression method.
It is performed in units of 16 bits. Therefore, in the 16-bit non-compression method, the number of samples to be read and the number of times of accessing the waveform memory match. In the 8-bit non-compression or compression method, the number of samples to be read out and the number of times of accessing the waveform memory do not always match.

The number of samples received in step 1003 is the number of samples to be read in the target channel. This sample number is the processing number 2 of the processing A described above.
It can be understood by fetching an overflow amount (overflow value) higher than 9 bits of the fractional address part of the addition result of (1) from the adder 504 into the processing B control unit 515. If a carry does not occur due to the addition of the process number 4 of the process A,
Returning to the address near the beginning of the loop part, in this case, the past sample in the sample RAM 1205 (FIG. 13) cannot be used. Therefore, the process B control unit 515 determines that the process A
When the carry non-occurrence in the processing number 4 is detected, the number of samples to be read is forcibly designated as 4 so that all 4 samples for interpolation are read.

The least significant bit of the address received in step 1003 is the least significant bit of the address integer part of the target channel. As the least significant bit of the address, the addition result (in particular, the least significant bit) of the processing number 3 or the processing number 6 of the above-described processing A is added from the adder 504 to the processing B control unit 5.
It can be understood by taking in 15.

Next, in step 1004, it is determined whether or not the number of samples is zero. If the number of samples is 0, there is no need to read a new sample from the waveform memory 208 in this target channel, so the flow proceeds to step 1009.
If the number of samples is not 0, the write pointer is incremented in step 1005, and the channel number and the number of samples regarding the target channel are written in the control RAM 517 in step 1006.

FIG. 7 shows the structure of the control RAM 517.
The control RAM 517 is configured by preparing a plurality of areas for storing the channel number and the number of samples to be read in that channel. The process B control unit 515 is provided with a write pointer and a read pointer. When writing the number of samples to be read in each channel to the control RAM 517, the write pointer is recommended (step 1005 described above), and the channel number and the sample are read from the control RAM 517. When reading the number and sending the read address for the channel, the read pointer is advanced (step 110 in FIG. 11 described later).
2). The control RAM 517 is designed to be used in a ring shape, and the write or read pointer is controlled by the control R.
When the one end of the AM 517 is reached, the position of the next pointer becomes the other end of the control RAM 517. Further, writing and reading are performed so that the position pointed by the read pointer follows the position pointed by the write pointer, but it is assumed that the size of the area is ensured so that the write pointer does not overtake the read pointer. Similar to the accumulator ACC, the write pointer and the read pointer are provided separately for the first half processing and the second half processing. When simply referred to as the write pointer and the read pointer, the first half processing indicates the one for the first half processing, and the second half processing indicates the one for the second half processing. In addition to the configuration shown in FIG. 7, one address may be associated with each channel and the required number of samples may be written therein.

Returning to FIG. 10 again, in step 1007, the number of times of waveform memory access required for the target channel is calculated and stored in the work register AT. The number of accesses is obtained from the compression method, the number of samples, and the address least significant bit obtained in step 1003. 16
In the bit uncompressed method, "access count = sample count"
It is. In the case of 8-bit uncompressed or compressed system, FIG.
When reading 8-bit samples from the 16-bit boundary position as shown in (c), “access count = number of samples / 2” is satisfied, and the 8-bit boundary position is not the 16-bit boundary as shown in FIG. 9D. To 8
When the reading of the bit sample is started, “access count = sample number / 2 + 1” is set (however, sample number / 2 is rounded down to the right of the decimal point). In addition, in FIGS. 9C and 9D, an example in which four samples are read in the order of 0, 1, 2, and 3 is described. In the case of FIG. 9C,
The case of FIG. 9D can be determined by the least significant bit of the address. When the least significant bit of the address is 0,
In the case of (c), the case of 1 is the case of FIG. 9 (d).

In FIG. 4 described above, the required number of waveform memory accesses is 1 for the 0th channel and 3 for the 2nd channel.
This is the case of 1 for the fifth channel and 2 for the seventh channel. The other channels are channels that are not sounding or have the overflow value of 0 (that is, it is not necessary to read the sample from the waveform memory).

In step 1008, the accumulator A
The access count AT is accumulated in CC. Step 1009
Then, it is determined whether or not the target channel is the last channel (the fifteenth channel is the last in the first half processing, and the thirty-first channel is the last in the second half processing). If it is not the last channel, the next target channel is selected in step 1010. Channel 10 (the number of channels is +1) Step 10
Return to 03.

When the final channel is reached in step 1009, in step 1011 the accumulator ACC
It is determined whether or not the accumulated access count value exceeds the maximum accessible number in the first half section or the second half section of the process B in which the access is actually executed, and the access count and the interpolation order for each channel are determined. In this embodiment, the maximum accessible number is 32. As described with reference to FIG. 4, the time width of the section in which one address is sent out in the process B is half the time width of the section in which the process for one channel is performed at the time division channel timing, and the first half section of the process B and the second half section of the process B This is because 32 access is possible for each. Therefore, if the accumulated access count value of the accumulator ACC does not exceed 32, the control RAM 51
Since the number of samples of each channel in the first half or the latter half written in 7 can be accessed, the access number of each channel and the interpolation order are determined according to the number of samples. In this case, 4-point interpolation is possible on all 16 channels in the first half or the second half. On the other hand, if the accumulated access count value of the accumulator ACC exceeds 32, it is not possible to access all the sample numbers of each channel written in the control RAM 517.
The access frequency of any channel is reduced and the interpolation order is reduced. As a method of deciding a channel that reduces the number of accesses, for example, there are the following methods.

The number of accesses is reduced from one end in the order of channels. The number of accesses is reduced from the channel reproducing the 16-bit waveform. The 16-bit waveform has a great reduction effect. At that time, the number of accesses is reduced from the channel having the lower volume level. In this way, the influence on the musical sound is small. The volume level of each channel is known from the envelope value.

Although four-point interpolation is basically performed for each channel in the present embodiment, the number of samples should be secured so that at least two-point interpolation can be performed when the number of accesses is reduced. Therefore, the number of accesses is not reduced so much that two-point interpolation cannot be performed. Also, in the case of a compressed waveform, it cannot be reproduced if the sample in the middle is skipped, so it is excluded from the target of the access count reduction.

FIG. 14 shows a specific example (including an example in which the number of times of access is not reduced) in this embodiment. FIG.
In (a) to (g), the advance amount is the advance amount of the waveform memory sample address (specifically, the sample address integer part indicating each sample recorded in the address RAM 511), and the number of samples obtained in step 1003. That is. A downward arrow ↓ indicates a convenient reference position (a position where reading has been completed in the previous process B of the same channel) for indicating the address advance amount. ×, ○, and ● are
One sample of waveform data is shown. ● is already a sample RA
A sample existing in M is shown, and a circle shows a sample to be read.

FIG. 14A shows the case where the advance amount of the address is 0. Since four samples required for four-point interpolation exist in the sample RAM, new reading is unnecessary and the access count is zero. Naturally, the number of accesses is not reduced.

FIG. 14B shows the case where the advance amount of the address is 1. Since three of the required four samples are already in the sample RAM, only one sample is read. Therefore, regardless of the compression format, one access is required. In this case, the number of accesses is not reduced.

FIG. 14C shows the case where the address advance amount is 2. Since two of the required four samples are already present in the sample RAM, only two samples are read out. The 16-bit uncompressed format requires two access times, and the 8-bit compressed or uncompressed format requires one or two access times. In this case, the number of accesses is not reduced.

FIG. 14D shows the case where the address advance amount is 3. Since one point out of the required four point samples already exists in the sample RAM, only three samples are read out. The 16-bit uncompressed format requires three access times, and the 8-bit compressed or uncompressed format requires two access times. In this case, when reducing the number of accesses (limited to the non-compressed format), FIG.
As described in the lower part of (d), the number of accesses is reduced by newly reading out two samples required for two-point interpolation.

FIG. 14E shows the case where the amount of advance of the address is 4. Sample RAM for required 4 points
All 4 samples are read because they do not exist. 1
In the 6-bit uncompressed format, the access count is 4 times, 8 times
In the case of the bit compression or non-compression format, the access frequency is required to be 2 or 3 times. In this case, when reducing the number of accesses (limited to the non-compressed format), FIG.
As described in the lower part of (e), the number of accesses is reduced by newly reading out two samples required for two-point interpolation.

FIG. 14 (f) shows a case where the waveform data is in an uncompressed format and the amount of advance of the address is 5 (the same applies when the amount of advance is 5 or more). Sample RAM for required 4 points
All 4 samples are read because they do not exist. 1
In the 6-bit uncompressed format, the access count is 4 times, 8 times
The number of accesses is 2 or 3 in the bit uncompressed format
Need to be repeated. In this case, when the access count is reduced, the access count is reduced by newly reading out two samples required for two-point interpolation, as described in the lower part of FIG.

FIG. 14G shows the case where the waveform data is in the 8-bit compression format and the address advance amount is 5. The required 4 samples are not in the sample RAM, so all 4 required for 4 point interpolation are read out.
Since this is a compressed format, it is not possible to skip intermediate samples, so a total of 5 samples are read. The number of accesses is 3 times. In the case of a compressed waveform, the advance amount may be limited so that the case shown in FIG. 14 (g) does not occur.

Next, referring to FIG. 8, the address generator 1
The operation of the process B by 02 will be described. As can be seen from FIG. 8, in process B, one address is sent out by performing the processes of process numbers 1, 2, and 3 below in slot numbers 1, 3, and 5. As a result, the waveform memory 20
8 is accessed once. The same processing is performed for slot numbers 7, 9 and 11 so that 1 access is performed, so processing for 1 access can be performed in 3 clocks, and 2 accesses can be performed within the time per channel of time division channel timing. Is. The waveform memory access process of the process B has no relation to the process according to the time division channel timing of the process A, and is sequentially performed for each channel that needs to be read. The channels and the number of samples that need to be read have been determined by the above-described preprocessing in FIG. Further, as described with reference to FIG. 3, when the process B is performed for a certain channel, the process A for the channel has already been performed, and therefore the process numbers 1 to 3 below are performed.
When executing, the address value of the channel is already set in the address RAM 511. Hereinafter, FIG.
The processes of process numbers 1 to 3 of process B will be described with reference to FIGS.

1. In the processing number 1, the selector 501 is O
The FS is selectively output and the selector 502 outputs the ARAM (AD
I) is selectively output. The ARAM (ADI) is an address integer part of the channel to be processed in the address RAM 511 (the order of the channels for sending out the address is determined based on the control of the process B controller 515, which will be described in detail later with reference to FIG. 12). Yes, process number 3 of process A above
The integer part synthesizing unit 512 prepares in the same manner as described above.
OFS is an offset generated and output by the processing B control unit 515, and is an added value for sequentially accessing samples of the required number of samples (16-bit data including the required samples in the case of the 8-bit sample format). is there. FIG.
The offset OFS of each access timing in
For example, 0 for channel 0, -2 for the first time on channel 2 (-4 for 8-bit samples ←← 1/2 later)
The second time is -1 (the same as -2), the third time is 0, and the fifth time.
The first time of the channel is -1 (same as -2), the second time is 0, etc. As a result, the samples corresponding to the circles in FIG. 14 described above are controlled to be sequentially read. Since the processing B control unit 515 has already acquired the compression method, the number of samples to be read, and the address least significant bit for each channel in step 1003, the OFS can be sequentially generated and output. The adder 504 is an ARAM (AD
I) + OFS is calculated and output. The addition result UD is output after 2 clocks and is used in the next processing number 2 via the shifter 505.

2. In the processing number 2, the data UD ↓ 1 obtained by shifting the addition result UD of the processing number 1 by 1 bit by the shifter 505 is input to the selector 501, and the selector 501 selectively outputs the data UD ↓ 1. The selector 502 selects and outputs the same UD ↓ 1 as the selector 501 when the waveform data is in the 16-bit sample format, and outputs 0 when it is in the 8-bit sample format. Adder 50
4 adds these data and outputs the addition result after 2 clocks.

In short, when the waveform data is in the 16-bit sample format, it is the same as passing through the addition result of the processing number 1 without performing the addition, and the waveform data is 8
In the case of the bit sample format, the addition result of the process number 1 is halved and output. Since the address of the sample is attached in sample units, in the case of the 8-bit sample format, if the address is halved, the position of the 16-bit boundary waveform data including the sample is calculated. In the case of the 16-bit sample format, it seems that the least significant bit of the addition result of the processing number 1 is discarded.
UD ↓ 1 input to 1, 502 is data including one bit below the decimal point, and the adder 504 performs addition including one bit below the decimal point, so the least significant bit is not discarded. This processing number 2 means that the waveform data address to be accessed can be calculated.

3. In the process number 3, the selector 501 selects and outputs the address reference value WAD, and the selector 502 selects and outputs the addition result UD of the process number 2. Adder 504
Adds these data and outputs the addition result MALAT after two clocks. The address obtained by the process number 2 is an address with the head position of the loop part as the reference of the address 0. On the other hand, in reality, the waveform data is stored in the waveform memory 20.
8 is stored at a predetermined address. Therefore, the address reference value WAD of the waveform data (the address on the waveform memory 208 at the loop portion head position of the waveform data) is added to convert the read address into the address on the waveform memory 208.

The addition result MALAT is supplied to the address terminal of the waveform memory 208 via the read integer latch 508, whereby the waveform data of the address is read.

The operation of the process B described above is performed by the process B control unit 51.
It is performed under the control of 5. Hereinafter, the process B control unit 51
The operation of No. 5 will be described. FIG. 11 shows the address generator 102.
6 is a flowchart showing the operation of the process B control unit 515 when performing the address sending operation of process B described above. The operation of FIG. 11 is executed in parallel with the operation of the preprocessing of FIG. For example, when the address generator 102 is executing the process A for the first half of the 0th to 15th channels, the process B control unit 515 performs the operation of FIG. 10 as a preprocess for sending out the addresses of the 0th to 15th channels. In parallel with this, the process B control unit 515 performs the address sending-out process of FIG. 11 for the 16th to 31st channels for which the preprocessing has already been completed.

In FIG. 11, in step 1101,
It is determined whether the value of the read pointer that points to the control RAM 517 shown in FIG. 7 and the value of the write pointer match. The value of the write pointer means the value of the write pointer updated by the process of FIG. 10 executed immediately before. If the value of the read pointer and the value of the write pointer are different in step 1101, step 11
In 02, the read pointer is incremented, and in step 1103, the channel number and sample number pointed to by the read pointer are read from the control RAM 517.

Next, in step 1104, the compression method and the least significant bit of the address for the channel of the read channel number are received. These may be acquired in the same manner as step 1003 in FIG. 10, but the values obtained in FIG. 10 may be held in a work register in the process B control unit 515 and used. Step 110
Although 5 does not particularly perform any processing, it indicates that the address sending processing performed in the next step 1106 is the first access. Step 1106
Then, each block of the address generator 102 is instructed to create a read address for the first access. As a result, the operations of the processing numbers 1 to 3 of the processing B described above are executed, and the address transmission of the first access is performed.

Further, in step 1107, it is determined whether or not the access count of the channel is completed. If the access count has not been completed, the process goes through step 1108 (step 1108 does not perform any particular processing, but indicates that the next access is performed in step 1106), and the next address is sent out in step 1106. Do. When the access count of the channel is completed in step 1107, the process returns to step 1101.

If the value of the read pointer and the value of the write pointer match in step 1101, it means that there is no more address to be sent to the waveform memory 208, so the flow advances to step 1109. Step 1
At 109, it is determined whether or not there is access time left.
If there is an access surplus time, the free time slot is used to execute the refresh of the waveform memory 208 or the access processing of the waveform memory 208 from the CPU 204 in step 1110, and the process returns to step 1109. When there is no more time to access, the process ends.

Next, the decoder 104 of FIG. 1 will be described in detail. FIG. 12 shows the decoder 104 and the interpolator 1.
03 shows a block configuration of No. 03. The decoder 104 includes a selector 1201, an adder 1202, a delay circuit 1203, a selector 1204, a sample RAM 1205, an expansion coefficient generator 1206, multipliers 1207 and 1208, and a controller D1209.

FIG. 13 shows the structure of the sample RAM 1205. The sample RAM 1205 is composed of four sample storage areas for each channel. The four sample storage areas are used in a ring shape. That is, a pointer is provided for each channel, and when writing a sample, the sample is written at the position indicated by the pointer and the pointer is advanced by one. For example, the pointer is the i-th channel in FIG.
Sample 1 → 2 → 3 → 4 → 1 → 2 → ... In the sample RAM 1205 of FIG. 12, the terminals labeled “1D” and “2D” are the terminals for reading the sample one sample before and the sample two samples before from the current pointer position, respectively.

The operation of the decoder 104 will be described in detail with reference to FIGS. 12 and 13. The waveform data read from the waveform memory 208 by the address sent by the above process B is input to the selector 1201 and the delay circuit 1203. The size of this waveform data is 16 bits, and its format is 16 bits uncompressed, 8 bits.
Either bit uncompressed or 8-bit compressed. If the data is 8-bit compressed or uncompressed,
Since only one of the upper 8 bits or the lower 8 bits of the input 16 bits is the desired sample, the selector 1
In 201, a desired sample of upper 8 bits or lower 8 bits is selected.

The control control signal of the selector 1201 is output by the control unit D1209. The control unit D1209 performs the process B.
Decoder control data output by the control unit 515 in synchronization with the address sending (channel number related to the channel sending the address, compression format, whether the desired sample is upper 8 bits or lower 8 bits in the case of 8 bit sample It is determined whether the upper 8 bits or the lower 8 bits of the input waveform data should be selected according to the information shown).

The uncompressed or compressed 8-bit sample output from the selector 1201 is input to the adder 1202. Further, the adder 1202 has a sample RA
Samples one and two before the current pointer position are read from M1205, and the multiplication results obtained by multiplying the samples by the expansion coefficient generator 1206 by the multipliers 1207 and 1208 are input. The adder 1202 is the selector 1
The current sample from 201 and the multipliers 1207, 12
08 adds the multiplication results and adds the addition results to the selector 12
Enter in 04. When the waveform data currently being processed is an 8-bit compressed waveform, a predetermined expansion coefficient is output from the expansion coefficient generating unit 1206, one sample is reproduced from the compressed sample, and output from the adder 1202. If the waveform data currently being processed is an 8-bit uncompressed waveform,
The expansion coefficient generator 1206 outputs 0 as the expansion coefficient, and the uncompressed sample is output through the adder 1202.

On the other hand, when the sample read from the waveform memory 208 is 16-bit uncompressed data, the sample is input to the selector 1204 after being delayed by the delay circuit 1203 for a predetermined time. The reason why the delay circuit 1203 delays is that the 8-bit sample is input to the selector 1204 via the adder 1202, so that it matches the timing.

The selector 1204 selects and outputs the sample from the delay circuit 1203 in the case of 16-bit sample based on the selection control signal from the control unit D1209,
When it is a bit sample, the sample from the adder 1202 is selected and output. The sample output from the selector 1204 is written in the position pointed to by the pointer of the channel of the sample RAM 1209, and the pointer is advanced by one.

The above operation is performed for each sample of each channel in synchronization with the timing at which the address generator 102 sends out the address in the process B. In the section 303 of the first half channel of FIG. 3, the above operation is performed for the 0th to 15th channels.
Samples are set in the sample storage areas of the 0th to 15th channels of the AM 1205. The same applies to the 16th to 31st channels in the latter half. Since it is basically 4-point interpolation, 4 samples (including already held samples) for each channel are prepared in the sample RAM 1205. However, the number of channels for which the interpolation order is reduced from 4 points to 2 points by the reduction of the number of times the waveform memory is accessed becomes 2 samples.

Next, the interpolator 103 of FIG. 1 will be described in detail. In FIG. 12, the interpolator 103 is a multiplier 1
210, interpolation coefficient generator 1211, interpolation accumulator 121
2 and a control unit I1213.

When the interpolator 103 starts the first half processing, that is, the interpolation of each channel for the 0th to 15th channels, all four samples of each channel used for the interpolation are set in the sample RAM 1209. The same applies to the 16th to 31st channels in the latter half. The interpolator 103 sequentially performs interpolation processing on the 0th to 15th channels in the first half and on the 16th to 31st channels in the latter half according to the time division channel timing. The control unit I1213 inputs the control clock Φ, the channel count value CHC, and the interpolation order (which the process B control unit 515 outputs corresponding to each channel), and performs each process according to the time division channel timing. Control the block. The interpolation process for one channel is as follows.

First, under the control of the control unit I1213,
Four samples of the channel are sequentially read from the sample RAM 1205. The read samples are sequentially input to the multiplier 1210. In synchronism with the input of four samples, the interpolation coefficient generator 1211 sequentially inputs the interpolation coefficients to be multiplied by each sample to the multiplier 1210. The interpolation coefficient generator 1211 generates and outputs an interpolation coefficient corresponding to each sample based on the address fractional part of the channel output from the address generator 102. This fractional part of the address is the address R of the address generator 102 of FIG.
It is output from the AM 511 via the interpolating decimal part latch 513. The multiplier 1210 multiplies each of the above samples by the corresponding interpolation coefficient, and the interpolation accumulator 1212 accumulates the multiplication result. As a result, the interpolated tone waveform data is generated and output. For the channel whose interpolation order is reduced from 4 points to 2 points by reducing the number of times the waveform memory is accessed, 2-point interpolation is performed using 2 samples instead of 4 samples to obtain interpolated tone waveform data.

In the above embodiment, it is determined in step 1011 of FIG. 10 whether the accumulated access count value of the accumulator ACC exceeds 32, which is the maximum accessible number, and the read sample of each channel is read. Number, number of accesses, and interpolation order are determined,
The maximum accessible number may be determined by giving priority to the amount of other processing. For example, when it is known in advance that the waveform memory is refreshed or accessed by the CPU, the number of times of access for those processes is secured in advance, and the remaining number is set as the maximum accessible number, and the determination in step 1011 is made. May be performed.

In particular, when a DRAM is used as the waveform memory, refreshing is always necessary, so the access count for refreshing should be secured with priority. Also, reading / writing of the waveform memory from the CPU is as follows.
It is advisable to respond according to the degree of urgency. For example, when the urgency of the waveform memory access from the CPU is low, the access is performed using an empty time slot not used in the sound source channel. When the degree of urgency is high, a portion for waveform memory access from the CPU is secured first, and the rest is used for the sound source channel.

In the above-described embodiment, the waveform memory is continuously accessed in the front slots in the first half and the second half of the process B and the decoding as shown in FIG. 4, but not in the front side. May be. For example, with respect to the above-mentioned preferentially secured refresh or access from the CPU, those processes are performed in the front slot in the section, and continuous waveform memory access for each channel is performed in the rear slot. You may However, in that case, it is necessary to start the interpolation processing of the first half section 304 after the processing of the first half section 303 of FIG. 3 is completed and all the samples necessary for interpolation are prepared in the sample RAM (second half). Processing is the same). Therefore, it is necessary to shift the interval in which the interpolation is performed (it is sufficient to start the first half of the interpolation process after the first half of the decoding process and start the second half process of the interpolation after the second half process of the decoding).

Further, in the above embodiment, one sampling period is divided into ½ (first half and second half) and the first half processing and the second half processing are alternately performed. Not limited to For example, one sampling cycle may be divided into 1/3, 1/4, ... And the processing may be performed in units of these sections. Further, irregular division may be performed instead of equal division (for example, 0th to 1st divisions).
4 channels and divided into 15th to 31st channels).
Further, one sampling period may be used as a unit without dividing the section. However, note that the address RAM is not rewritten by the process A before the address is sent out by the process B to access the waveform memory.
Need to guarantee. For that purpose, for example, when the sections are not divided, two sets of address RAMs are prepared, and the process A
It is necessary to adopt a method of alternately using two sets of address RAMs for the address rewriting by the process B and the address sending by the process B. If one sampling cycle is divided into the first half and the latter half, the process A and the process B can be alternately performed in one set of address RAMs, and the circuit configuration can be simplified and rational. .

[0112]

According to the first or second aspect of the present invention,
Prior to reading the waveform memory, the address of each channel is created and temporarily stored in the address storage means.
Further, the number of times of access is calculated based on the amount of advance of the address of each channel, and the waveform memory is continuously accessed by the number of times of access. Further, the waveform sample read from the waveform memory is temporarily stored in the waveform sample storage means, and the musical sound generation means produces the musical sound for each sampling period of each channel based on the waveform sample of each channel stored in the waveform sample storage means. To generate. Since the address and the waveform sample are buffered in the address storage means and the sample storage means, the timing of reading the waveform sample can be adjusted appropriately, and continuous access matching the speed of the waveform memory becomes possible. Therefore, when it is not necessary to read a waveform sample on a certain channel, or when only a small number of waveform samples need to be read because a waveform sample buffered on a certain channel can be used, the remainder The time slot can be devoted to other processing. Further, since the surplus time slots can be used for access to other channels, the number of cases in which the interpolation order needs to be reduced due to the relationship between channels decreases.

According to the invention of claim 6, an accumulating means and a judging means are further added to the structure of claim 1, the access frequency is accumulated for a predetermined number of channels, and the access corresponding to the predetermined number of channels is performed. Since it is determined whether access for the accumulated number of times is possible during the period,
In addition to the effects of the invention described above, before starting the waveform memory access, it is possible to know whether or not the required access to the predetermined number of channels is possible, and it is possible to deal with it. Particularly, in the invention according to claim 8,
If the determination means determines that it is impossible, the number of accesses for any one of the predetermined number of channels is decreased (the interpolation order is decreased). The case of reduction can be minimized.

According to the invention of claim 3 or 7, since the sampling cycle is divided into a plurality of sections and the processing is carried out for each section, the circuit configuration such as the address storage means can be simplified. Especially, the sampling period is 1/2
If the first half processing and the second half processing are performed, the address storage means may be one set.

According to the invention of claim 4, proper waveform samples can be reproduced even when returning to the vicinity of the beginning of the loop portion. According to the invention of claim 5 or 9,
The remaining time of the access by the access means can be used to perform other processing by the second access means (for example, refresh processing of the waveform memory of the DRAM configuration or access of the waveform memory by the CPU).

As described above, according to the present invention, in the sound source of the waveform memory reading system which simultaneously generates musical tones for a plurality of channels in the time-division channel operation, the waveform can be efficiently generated by each channel when necessary. You will be able to access the memory.

[Brief description of the drawings]

FIG. 1 is a block configuration diagram of a sound source section to which a sound source device according to the present invention is applied.

FIG. 2 is an overall block configuration diagram of an electronic musical instrument to which the sound source device of the embodiment is applied.

FIG. 3 is a diagram showing a timing of a main part in the sound source unit of the embodiment.

FIG. 4 is a diagram showing a state of a channel during each processing of FIG.

FIG. 5 is a block diagram of an address generator.

FIG. 6 is a diagram showing a memory map of the address RAM shown in FIG.

FIG. 7 is a block diagram of a control RAM

FIG. 8 is a timing chart of the address generator.

FIG. 9 is a diagram showing a compression method of waveform data.

FIG. 10 is a flowchart showing the operation of the processing B control unit during processing A.

FIG. 11 is a flowchart showing the operation of the processing B control unit during processing B.

FIG. 12 is a block diagram of a decoder

FIG. 13 is a block diagram of a sample RAM

FIG. 14 is a diagram showing a specific example of reducing the number of accesses in the present embodiment.

[Explanation of symbols]

101 ... Control register, 102 ... Address generator, 10
3 ... Interpolator, 104 ... Decoder, 105 ... Volume change control unit, 106 ... Channel (ch) accumulator, 107 ... Effect circuit, 108 ... Refresh counter, 109 ... CPU
Access control unit, 110, 111 ... Selector, 112 ...
System clock generator, 113 ... Channel (ch)
Counter, 204 ... Central processing unit (CPU), 207 ...
Sound source section, 208 ... Waveform memory, 210 ... Digital-to-analog converter (DAC), 211 ... Sound system (S
S), 212 ... External storage device, 213 ... Bus, 501,
502, 503 ... Selector, 504 ... Adder, 505 ...
Shifter, 506 ... Vibrato modulator, 507 ... Octave (OCT) shifter, 508 ... Read integer latch, 509 ... Integer latch (ILAT), 510 ... Fractional latch (FLAT), 511 ... Address RAM, 51
2 ... Integer part combining part, 513 ... Interpolation decimal part latch, 51
4 ... Control unit A, 515 ... Process B control unit, 517 ... Control R
AM, 516 ... Accumulator (ACC).

Claims (9)

[Claims] 1. A waveform memory sound source device for generating musical tones of a plurality of channels by operating in time division on a plurality of channels at a predetermined sampling period, the waveform memory storing waveform samples, wherein A device that can be accessed a predetermined number of times, an address storage unit that stores the address of each channel, a waveform sample storage unit that stores the waveform sample of each channel, and Address creating means for creating a channel address and storing it in the address storing means; access count calculating means for calculating an access count of the waveform memory for each channel based on an advance amount of the address of each channel; Address of each channel stored in the address storage means A first access unit for continuously accessing the waveform memory for each access count of each channel calculated by the access count calculation unit and storing the read waveform sample of each channel in the waveform sample storage unit. A waveform memory sound source device, comprising: a tone generation unit that generates a tone for each sampling period of each channel based on the waveform sample of each channel stored in the waveform sample storage unit. 2. A waveform memory sound source device for generating musical sounds of a plurality of channels by operating in time division on a plurality of channels at a predetermined sampling period, wherein the waveform memory stores waveform samples, A unit that can be accessed a predetermined number of times, an address storage unit that stores the address of each channel, and a waveform sample storage unit that stores n (n is an integer of 2 or more) waveform samples for each channel. An address creating means for creating an address of each channel and storing it in the address storing means prior to reading the waveform memory, and to the waveform memory for each channel based on the advance amount of the address of each channel. Access number calculation means for calculating the required number of accesses of Based on the address of each channel stored in the means, the waveform memory is continuously accessed by the number of access times of each channel calculated by the access number calculating means, and each of the waveform samples is already stored in the waveform sample storage means. A first access unit for replacing the waveform samples of the smallest number of the n waveform samples of the channel with the waveform samples of the respective channels read by the continuous access, and for each channel stored in the waveform sample storage unit. A waveform memory tone generator device comprising: a tone generation unit that generates a tone for each channel sampling period by performing an interpolation process using n waveform samples. 3. The sampling cycle is divided into m (m is an integer of 2 or more) intervals, and the first access unit is configured to perform, for each of the divided intervals, the plurality of channels to be processed in the interval. The waveform memory sound source device according to claim 1, wherein the waveform memory is continuously accessed. 4. The waveform data of the waveform memory is composed of an attack section and a loop section, and the address creating means is provided when the created address enters the loop section from the attack section of the waveform data to be read on the channel. For each cycle of the loop portion of the waveform data, the advancing address is returned in the reverse direction to repeatedly create the same address in the loop portion, and the access count calculation means, when the return of the address is executed, The waveform memory tone generator according to claim 1 or 2, wherein a predetermined number of times of access is designated for a channel regardless of the amount of advance of the address. 5. A second access means for performing at least one of reading and writing of the waveform memory is further provided, wherein the second access means uses a surplus time after the waveform memory is accessed by the first access means. hand,
The waveform memory sound source device according to claim 1, wherein the waveform memory is accessed. 6. A waveform memory sound source device for generating musical sounds of a plurality of channels by operating in a time-divisional manner in a plurality of channels at a predetermined sampling period, wherein the waveform memory stores waveform samples within the predetermined sampling period. A device that can be accessed a predetermined number of times, an address storage unit for storing the address of each channel, a waveform sample storage unit for storing the waveform sample of each channel, and each of them before reading the waveform memory. An address creating means for creating a channel address and storing it in the address storing means; an access count calculating means for calculating an access count of the waveform memory for each channel based on an advance amount of the address of each channel; Number of channels, the access count calculation means Accumulating the calculated number of accesses, and accumulating means for outputting the accumulated number of times, within the access period corresponding to said predetermined number of channels,
When the determination means determines that the accumulated number of times of access is possible, and when the determination means determines that the access is possible, the access number calculation means calculates based on the address of each channel stored in the address storage means. The number of times each channel is accessed, the waveform memory is continuously accessed,
First access means for storing the read-out waveform sample of each channel in the waveform sample storage means, and based on the waveform sample of each channel stored in the waveform sample storage means, tones are generated for each sampling period of each channel. A waveform memory sound source device comprising a musical sound generating means. 7. The sampling cycle is divided into m (m is an integer of 2 or more) sections, and the accumulating means makes access counts for a plurality of channels to be processed in each of the divided sections. The determination unit makes the determination for each of the divided sections using the section as the access period, and the first access unit performs processing for each of the divided sections in the section. 7. The waveform memory tone generator according to claim 6, wherein the waveform memory is continuously accessed for a plurality of channels to be processed. 8. The waveform memory tone generator apparatus according to claim 6, wherein said judging means reduces the number of accesses to any one of said predetermined number of channels when it is judged impossible in said judgment. 9. A second access means for performing at least one of reading and writing of the waveform memory, further comprising: a second access means if the determination means determines that the second access is possible.
7. The waveform memory sound source device according to claim 6, wherein the access means utilizes the portion of the total number of accesses within the access period that has not been used in the access by the first access means to access the waveform memory. .