JP2882464B2 - Waveform memory sound generator - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a tone generator for generating and outputting digital tone waveform data.
The present invention relates to a waveform memory sound source device in which a waveform memory is read out by a time-division plural channel so that the waveform memory can be accessed when necessary.

[0002]

2. Description of the Related Art Conventionally, there has been known a waveform memory sound source which simultaneously generates musical tones for a plurality of channels by time division channel operation. In such a sound source, a tone generation operation of each channel is performed in a time slot of each channel obtained by equally dividing one sampling period. Similarly, the access to the waveform memory is a time-division channel operation, and for each channel, access is performed a predetermined number of times in a time slot corresponding to the channel.

Further, the sound source of the waveform memory reading system is provided with an interpolation circuit, and performs an interpolation calculation using several consecutive samples (waveform data) for each channel.
There is one that obtains musical tone waveform data for points. In addition, the interpolation circuit has a sample buffer,
There is a waveform memory sound source that enables high-order interpolation calculation. This is because the waveform data read from the waveform memory is stored in the sample buffer, and when the address of the address is small when reading the waveform memory, the waveform data stored in the sample buffer is newly read. The interpolation is performed using the obtained waveform data.

[0004]

As described above, in a waveform memory tone generator that simultaneously generates musical tones for a plurality of channels in a time-division channel operation, the access to the waveform memory is determined at a fixed number of times for each channel. Have been. Generally, according to the waveform reading speed (F number) of each channel, and at each sampling cycle,
Although the required number of times of access to the waveform memory is different, the related art has not performed any corresponding operation, and the limited operation speed (accessible number) of the waveform memory has not been effectively used.

In the method using a sample buffer, interpolation is possible by effectively using the data in the sample buffer when the address advance is small, but when the address advance is large, all necessary waveform data must be read out. In some cases, the interpolation order may be reduced (for example, four-point interpolation may be replaced with two-point interpolation).

According to the present invention, in a sound source of a waveform memory reading system for simultaneously generating musical tones for a plurality of channels by time-division channel operation, it is possible to efficiently access the waveform memory for each channel when necessary. The purpose is to be.

[0007]

According to a first aspect of the present invention, there is provided a waveform memory tone generator for generating a musical tone of a plurality of channels by operating in a predetermined sampling cycle in a time-division manner on a plurality of channels. A memory that can be accessed a predetermined number of times within the predetermined sampling period, address storage means for storing an address of each channel, and a waveform for storing a waveform sample of each channel. Sample storage means, address reading means for creating an address of each channel prior to reading out the waveform memory, and storing the address in the address storage means; and Access number calculating means for calculating the number of accesses to the waveform memory; Based on the address of each channel stored in the storage means, the waveform memory is continuously accessed by the number of accesses of each channel calculated by the number-of-accesses calculation means, and the read waveform sample of each channel is converted into the waveform sample. The first stored in the storage means
An access unit, and a tone generation unit that generates a tone for each sampling period of each channel based on the waveform sample of each channel stored in the waveform sample storage unit.

According to a second aspect of the present invention, there is provided a waveform memory tone generator for generating a musical tone of a plurality of channels by operating in a time-division manner on a plurality of channels at a predetermined sampling period.
A device which can be accessed a predetermined number of times within the predetermined sampling period, an address storage means for storing the address of each channel, and n (n is 2)
Waveform sample storage means for storing a waveform sample of the above (integer), an address creation means for creating an address of each channel prior to reading out the waveform memory, and storing the address in the address storage means; Access number calculating means for calculating the required number of accesses to the waveform memory for each channel based on the advance amount of the address; and the access number calculating means based on the address of each channel stored in the address storage means The waveform memory is continuously accessed by the number of access times of each channel calculated in the above, and n of each channel already stored in the waveform sample storage means is accessed.
First access means for sequentially replacing the waveform samples having the smaller addresses with the waveform samples of the respective channels read out by the continuous access, and n number of the respective channels stored in the waveform sample storage means. Music tone generating means for generating a tone for each sampling period of each channel by performing interpolation processing using waveform samples.

The invention according to claim 3 is the invention according to claim 1 or 2
Wherein the sampling period is divided into m (m is an integer of 2 or more) sections, and the first access means should perform processing in each of the divided sections in the section The waveform memory is successively accessed for a plurality of channels. It is desirable to divide the sampling period equally into the first half and the second half.

The invention according to claim 4 is the invention according to claim 1 or 2.
In the waveform memory sound source device described in the above, the waveform data of the waveform memory is constituted by an attack part and a loop part, and the address creating means is configured to change the created address from the attack part of the waveform data to be read in the channel to the loop part. When entering, for each cycle of the loop portion of the waveform data, the advancing address is returned in the reverse direction to repeatedly create the same address in the loop portion, and the access count calculating means executes the return of the address. If
Regarding the channel, a predetermined number of accesses is specified regardless of the address advance amount.

[0011] The invention according to claim 5 is the invention according to claim 1 or 2.
The waveform memory sound source device according to the above, further comprising a second access means for performing at least one of reading and writing of the waveform memory, the second access means,
The waveform memory is accessed using a surplus time after the first access unit accesses the waveform memory. The second access means performs, for example, refresh when the waveform memory has a DRAM configuration, or accesses the waveform memory by the CPU.

According to a sixth aspect of the present invention, there is provided a waveform memory tone generator for generating musical tones of a plurality of channels by operating in a time-division manner on a plurality of channels at a predetermined sampling period, wherein the waveform memory stores waveform samples.
A memory which can be accessed a predetermined number of times within the predetermined sampling period; an address storage means for storing an address of each channel; a waveform sample storage means for storing a waveform sample of each channel; Prior to reading, an address generating means for generating an address of each channel and storing the address in the address storage means, and an access for calculating the number of accesses of the waveform memory for each channel based on the advance amount of the address of each channel. Number-of-times calculating means, for a predetermined number of channels, accumulating the number of times of access calculated by the number-of-accesses calculating means, and accumulating means for outputting the number of times of accumulating, within an access period corresponding to the predetermined number of channels, Determining means for determining whether access for the number of accumulations is possible; Is determined to be possible, the waveform memory is successively accessed and read out by the number of access times of each channel calculated by the access number calculation means based on the address of each channel stored in the address storage means. First access means for storing a waveform sample of a channel in the waveform sample storage means, and tone generation means for generating a tone for each channel sampling period based on the waveform sample of each channel stored in the waveform sample storage means And characterized in that:

According to a seventh aspect of the present invention, in the waveform memory sound source device of the sixth aspect, the sampling period is divided into m (m is an integer of 2 or more) sections, and the accumulating means includes: For each of the divided sections, accumulate the number of accesses for a plurality of channels to be processed in the section, and for each of the divided sections, perform the determination using the section as the access period, First
The access means performs continuous access to the waveform memory for a plurality of channels to be processed in each of the divided sections. It is desirable to divide the sampling period equally into the first half and the second half.

According to an eighth aspect of the present invention, in the waveform memory tone generator according to the sixth aspect, when the determination means determines that the determination is impossible, the access means accesses any one of the predetermined number of channels. This is to reduce the number of times.

According to a ninth aspect of the present invention, in the waveform memory tone generator of the sixth aspect, the apparatus further comprises a second access unit for performing at least one of reading and writing of the waveform memory, and the determination unit determines that it is possible. In this case, the second access unit accesses the waveform memory by using a portion of the total number of accesses within the access period that has not been used in the access by the first access unit. Things. The second access means performs, for example, refresh when the waveform memory has a DRAM configuration, or accesses the waveform memory by the CPU.

[0016]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 2 shows the overall block configuration of an electronic musical instrument to which the tone generator according to the present invention is applied. FIG. 1 shows FIG.
2 shows a block configuration of a sound source section of the electronic musical instrument of FIG. 1 and 2, the same numbers indicate the same ones.

First, an overall configuration of the electronic musical instrument will be described with reference to FIG. The electronic musical instrument includes a keyboard 201, a display unit 202, a switch group (SW) 203, a central processing unit (CPU) 204, a read only memory (ROM) 20
5, random access memory (RAM) 206, tone generator 207, waveform memory 208, digital-to-analog converter (DAC) 210, sound system (SS) 211,
An external storage device 212 and a bus 213 are provided.
Keyboard 201, display unit 202, switch group 203, CPU
204, ROM 205, RAM 206, sound source 207,
The external storage device 212 is mutually connected by a bus 213.

The keyboard 201 is a keyboard provided with a plurality of keys for a user to perform a performance operation. The display unit 202 is provided on a panel of the electronic musical instrument and displays various information. The switch group 203 is provided on a panel,
By operating this, the user can give various instructions to the electronic musical instrument. The CPU 204 controls the operation of the entire electronic musical instrument. In particular, during a normal performance, an operation of the keyboard 201 is detected, and a sound generation instruction is issued to the sound source unit 207 in accordance with the operation. ROM 205 is a CPU
(A sound source control program for controlling the sound source unit 207) and various constant data are stored. The RAM 206 is used for a work register or the like. The external storage device 212 includes a DRAM (to be described later).
Waveform data to be loaded is stored in the configured waveform memory 208.

The tone generator 207 reads out waveform data from the waveform memory 208 in accordance with an instruction from the CPU 204, performs processing such as interpolation, envelope addition, channel accumulation, and effect addition, and outputs it as musical sound waveform data. The musical tone waveform data output from the sound source unit 207 is D
The signal is converted into an analog signal by the AC 210 and is emitted by the sound system 211.

The waveform memory 208 is constituted by a DRAM (Dynamic RAM). Waveform memory 208
Stores waveform sample data sampled at a predetermined rate. The waveform sample data is
The tone may be read from the external storage device 212 and stored in the waveform memory 208 prior to the generation of the musical tone. However, the tone generator of this embodiment is not used when performing the tone generating operation for a plurality of channels. Since the empty time slots can be used for other purposes,
The waveform data may be read from the external storage device 212 and stored in the waveform memory 208 using the vacant time slot during the tone generation operation.

Next, the sound source section 207 will be described in detail. In FIG. 1, the sound source unit 207 includes a control register 10
1, address generator 102, interpolator 103, decoder 1
04, volume change control unit 105, channel (ch) accumulator 106, effect circuit 107, refresh counter 10
8, a CPU access controller 109, a selector 110, a selector 111, a system clock generator 112, and a channel (ch) counter 113.

The control register 101 stores designation information for a plurality of channels transmitted from the CPU 204 (the sound source unit 207).
This is a control register for storing instructions and parameter information for the The CPU 204 sets predetermined designation information in the control register 101 for each sounding channel and issues a sounding start instruction. The specification information to be set includes specification information such as a memory read pitch (frequency number), a memory read section, a waveform data compression method, an envelope, and an effect coefficient.

Upon receiving the sound generation start instruction, the tone generator 207 starts the operation of generating a musical tone waveform. First, the address generator 102 sequentially generates read addresses of the waveform memory 208. The read address is a value obtained by sequentially accumulating the designated read pitch from the beginning of the designated read section. In particular, the sound source unit 207 includes the decoder 1
04 is provided with a sample RAM as a sample buffer, so that only a necessary number of waveform samples (waveform data) are read from the waveform memory 208 for each channel, and the number of times of access to the waveform memory in each channel can be varied. It has become. Therefore, the address generator 102 sequentially and continuously outputs the addresses of the waveform memory corresponding to the number of accesses to each channel at a timing different from the time division channel timing.

An address output from the address generator 102 is performed at a timing different from the time division channel timing, so that an empty time slot can be obtained. The refresh counter 108 and the CPU access control unit 109 perform refresh of the waveform memory 208 or CP
This is for accessing the waveform memory 208 from the U 204. The selectors 110 and 111 determine whether the refresh counter 108 or the CP
It is controlled to connect the U access control unit 109 to the waveform memory 208.

The read address generated by the address generator 102 is sent to the waveform memory 208 via the selector 110.
, Whereby the waveform data is read from the waveform memory 208. The decoder 104 receives the waveform data via the selector 111 at the timing when the address generator 102 sends out the address. In this embodiment, the compression method of waveform data is 16-bit uncompressed, 8
Either bit uncompression or 8-bit compression. Thus, the decoder 104 decodes the uncompressed waveform as it is, and decodes the compressed waveform, and stores it in the sample RAM.

The interpolator 103 reads the waveform data of each channel from the sample RAM in the decoder 104,
Interpolation processing (basically, four-point interpolation is performed and two-point interpolation is performed only when waveform data for four points cannot be secured). The volume change control circuit 105 adds an envelope to the tone waveform data of each channel. Channel accumulator 106
Accumulates the tone waveform data of each channel. The effect circuit 107 applies various effects (effects) to the result of channel accumulation. The tone waveform data to which the effect has been applied is input to the DAC 210 shown in FIG. 2 and is converted into an analog signal.

The tone generator 207 operates on 32 time-division channels. The system clock 112 is supplied to the sound source unit 207
Are supplied with a control clock signal .PHI. As a reference signal for performing a time-division operation. Channel counter 11
3 counts a channel count value CHC for performing the time-division channel operation (specifically, repeatedly counts 0 to 31) and supplies the count to each block in the sound source unit 207.

Next, with reference to FIGS. 3 and 4, an outline of the timing of the main part in the tone generator 207 of this embodiment will be described. In FIG. 3, “process A” indicates a section in which, among the processes performed by the address generator 102, a process of creating an address of each channel is performed. “Process B” indicates an interval in which, among the processes performed by the address generator 102, a process of sending an address to the waveform memory 208 is performed. “Decode” indicates a processing section of the decoder 104, in particular, a section in which a process of receiving waveform data output from the waveform memory 208 is performed. “Interpolation” indicates a processing section of the interpolator 103. In each processing section, one sampling period is divided into the first half and the second half, and the first to fifteenth channels are processed in the first half, and the sixteenth to thirty-first channels are processed in the second half.

FIG. 4 shows the state of the channel during each processing of FIG. “Processing A first half ch” in FIG. 4 corresponds to section 3 in FIG.
1 shows the state of the channel at 01. "Process B" in FIG.
“First half channel” indicates the state of the channel in the section 302 of FIG. “First half channel of decoding” in FIG. 4 shows the state of the channel in the section 303 of FIG. “First half channel of interpolation” in FIG. 4 indicates the state of the channel in the section 304 in FIG. In FIG. 4, each channel timing is vertically aligned and described, but in actuality, the timing of each process is shifted as shown in FIG.

In this embodiment, as can be seen from FIG.
The address generation process A by the address generator 102 and the interpolation process by the interpolator 103 operate in synchronization with the time division channel timing in the sound source. on the other hand,
Address sending process B from address generator 102
The processing of receiving the waveform data by the decoder 104 operates at a timing independent of the time-division channel timing (specifically, under the control of a processing B control unit in FIG. 5 described later).

For example, in FIG. 3 and FIG.
In the first half section 301, the address generator 102
The addresses of the channels 0 to 15 are sequentially created according to the time-division channel timing. In the first period 302 of the process B, the address generator 102 assigns one address of the 0th channel at a timing different from the time-division channel timing.
Addresses of the 0th to 15th channels are sent out, such as three addresses for the second channel, one address for the fifth channel, and so on. The time width of the section in which one address is sent out is half the time width of the section in which processing for one channel is performed at the time-division channel timing. The number of addresses to be sent out in each channel is different because the sample RAM in the decoder 104 holds the past waveform data and it is sufficient to read out only the required number of waveform data for each channel, or This is because there is a channel that does not need to be pronounced and does not need to send an address. Here (FIG. 4) shows a case where it is necessary to read from the waveform memory for channel 0 for 1 access, channel 2 for 3 accesses, channel 5 for 1 access, and channel 7 for 2 accesses. I have. The other channels are channels that are not sounding or that can generate musical tones only with samples that have already been read and stored in the waveform buffer 307. The non-sounding channel is a channel whose volume level is lowered, such as EG, and the channel is controlled so that the access timing of the waveform memory in the process B is not used.

In the first half section 303 of the decoding, the waveform data read out from the waveform memory 208 is received in accordance with the address sending timing of the first half section 302 of the processing B. Although described later in detail, the decoder 104
When the received waveform data is a compressed waveform, decoding is performed, and when the received waveform data is an uncompressed waveform, the data is directly written into an internal sample RAM. The interpolator 103 performs the interpolation process on the 0th to 15th channels using the data of the sample RAM in accordance with the time division channel timing in the section 304 of the first half of the interpolation. At the time of performing interpolation on a certain channel, waveform data of the channel required for performing interpolation is prepared in a sample RAM.

As described above, the musical tone waveform data of the 0th to 15th channels is generated. The same applies to the 16th to 31st channels processed using the latter half section.

An empty time slot appears because the address sending process B in the address generator 102 and the waveform data receiving process in the decoder 104 are performed at a timing different from the time division channel timing. In the sections 302 and 303 of FIG.
“ch” indicates an empty time slot that is not used for reading samples of any channel. This empty time slot section can be used arbitrarily. In the present embodiment, the refresh processing of the waveform memory 208 by the refresh counter 108 in FIG. 1 or the access processing to the waveform memory 208 by the CPU access control unit 109 is performed in the section of the empty time slot.

Next, the address generator 102 will be described in detail. FIG. 5 shows a block configuration of the address generator 102. The address generator 102 is connected to the selector 50.
1, 502, 503, adder 504, shifter 505, vibrato modulator 506, octave (OCT) shifter 5
07, read integer part latch 508, integer part latch (ILAT) 509, decimal part latch (FLAT) 51
0, an address RAM 511, an integer part synthesizing unit 512, an interpolation decimal part latch 513, a control unit A 514, a processing B control unit 515, and a control RAM 517. Processing B
An accumulator (ACC) 51 is provided inside the control unit 515.
6 are provided.

In FIG. 5, selectors 501, 502,
Reference numeral 503 denotes selectors for selectively outputting a predetermined input in each time slot of the time division. Adder 5
Reference numeral 04 denotes a 23-bit adder, which inputs the selected output data of the selector 501 and the selected output data of the selector 502 to execute addition. This adder 504 is described as “2D” because there is a delay of two clocks before the addition result is output. Shifter 505 includes adder 50
The result of addition of 4 or the decimal part data of the decimal part latch 510 is shifted and output. The shift amount of the shifter 505 is variable. The integer part latch (ILAT) 509 is a 23-bit latch, and the decimal part latch (FLAT) 510 is a 9-bit latch.

FIG. 6 shows a memory map of the address RAM 511 of FIG. The address RAM 511 includes areas for each of the 0th to 31st channels, and stores the current address value of each channel in these areas. The area of each channel is composed of an address upper ADH and an address lower ADL. The size of each of the ADH and ADL areas is 16 bits. A 32-bit address value including the address upper ADH and the address lower ADL is divided into an integer part and a decimal part. The address integer part corresponds to the address of the waveform memory 208. That is, corresponding to one value of the address integer part,
There is one sample (waveform data) in the waveform memory 208. The address decimal part indicates a finer unit, and is information used in interpolation processing using some waveform data. The address integer part is 23 bits, and the address decimal part is 9 bits. Therefore, the address RAM 511
ADH of each channel indicates the upper 16 bits of the 23-bit address integer part, and ADL indicates 16 bits obtained by combining the lower 7 bits of the 23-bit address integer part and the 9 bits of the address decimal part. Become.

It is to be noted that a symbol attached to an area indicates the area itself and also indicates data stored in the area. For example, the address lower ADL indicates the area storing the lower 16 bits of the current address value itself, and also indicates the lower data of the address value stored in that area. Hereinafter, the same applies to the symbols attached to the respective regions.

In FIG. 5, an integer part synthesizing unit 512 reads an address value of an arbitrary channel in the address RAM 511 and outputs the decimal part or the integer part. Specifically, when outputting the decimal part of the address, the address RA
The lower ADL of M511 is read, and the lower 9 bits are output as an address decimal part. When outputting the address integer part, the upper 7 bits of the ADL, that is, the lower 7 bits of the address integer part, are first taken in, then the upper 16 bits of the address integer part of the ADH are taken in, and they are combined to form a complete 23-bit address. Generates and outputs the integer part.

The control unit A 514 receives the clock Φ and the channel count value CHC, generates control signals for controlling the entire operation of the process A and the basic operation of the process B (described later in FIG. 8), Supply to Processing B control unit 5
Reference numeral 15 controls each block in order to perform the processing B described with reference to FIGS. In particular, the processing B control unit 515
In the first half of the processing B (302 in FIG. 3), the 0th to 15th 1
The accumulator 516 accumulates the number of accesses for the sixteen channels and accumulates the number of accesses for the sixteenth to thirty-first channels in the latter half of the process B (306 in FIG. 3). This is for storing the accumulated value. The operation of the processing B control unit 515 and the accumulator 516 will be described later in detail.

FIG. 8 is a timing chart of the address generator 102 shown in FIG. Each section demarcated by a vertically drawn dotted line indicates a time slot of one clock. FIG. 8 is a diagram in which two channel times out of the operation of 384 clocks (12 clocks × 32 channels in time division) of one DAC cycle are extracted. Slot numbers (0 to 11) are sequentially assigned to each section of 12 clocks for one channel. In FIG. 8, a section in which a series of slot numbers 0 to 11 are enclosed by a square is a section for one channel.

The numbers 1 to 6 in the row described as "Process A" correspond to the following process numbers, and the process of the process number is performed in the time slot in which the process number is described. For example, regarding the process A, “1” is described at the position of the slot number 0 and “2” is described at the position of the slot number 2, which is the slot of the slot number 0 and the following process number 1 indicates that the processing of the following processing number 2 is performed in the slot of the slot number 2. As for the process A, an address for one channel is created in six clocks. Hereinafter, with reference to FIG. 8 and FIGS.
02, the process number 1 of process A for creating an address
Step 6 will be described.

1. In the processing number 1, the selector 501
ITCH is selected and output, and the selector 502 selects and outputs LTUNE. PITCH indicates a pitch within an octave, and is designated by the CPU 204 via the control register 101. LTUNE indicates loop tune. The waveform data stored in the waveform memory 208 is divided into an attack portion and a loop portion, and LTUNE is 0 while the attack portion is being read. When entering the loop portion from the attack portion, the pitch value may be different between the attack portion and the loop portion.
The pitch is adjusted by adding TUNE to the pitch PITCH. LTUNE is controlled by the CPU 204 in the control register 1
Specify via 01.

The adder 504 is provided as PITCH + LTUNE
Is calculated. The addition result VIBM is output after two clocks and input to the vibrato modulator 506. The vibrato modulator 506 performs a process of adding the amount of the fluctuation in order to make the musical sound have a slow temporal fluctuation. The result of the vibrato modulation is an octave shifter 5
07 to perform an octave shift. OCT input to the octave shifter 507 indicates a shift amount for an octave, and is designated by the CPU 204 via the control register 101.

The output of the octave shifter 507 is input to the selector 501 as a pitch PITX. This pitch PITX is the advance value (frequency number) of the address in the channel. Actually, the addition result VIBM calculated in the slot of the processing number 1 of the previous channel timing is processed by the vibrato modulator 506 and the octave shifter 507, and is used as the pitch PITX of the processing number 2 of the channel timing.

2. In the process number 2, the selector 501 selects and outputs the pitch PITX output from the octave shifter 507, and the selector 502 reads the address decimal part ARAM (ADF) of the channel from the address RAM 511.
Is selected and output. The ARAM (ADF) is prepared by the integer part synthesizing unit 512. That is, the integer part combining unit 512 calculates
ADL for the channel in address RAM 511
Is read out, and only the lower 9 bits of the address decimal part are extracted and input to the selector 502 as the address decimal part ARAM (ADF). At the same time, the integer part synthesizing unit 512
Is an address integer part ARAM (AD
The lower bits of I) are obtained in an internal register.

The adder 504 is composed of ARAM (ADF) + P
Calculate and output ITX. The addition result UD is output after two clocks, and is used in the next processing number 3 via the shifter 505. Further, the result of this addition is represented by a decimal part latch (FL).
AT) 510, and the lower 9 bits are latched.
This is the data of the new address decimal part. The data of the decimal part of the address of the decimal part latch 510 is later written into the lower 9 bits of the ADL of the address in the address RAM 511 via the selector 503. Further, the integer part (overflow value) of the UD at this time is taken into the processing B control unit 515 as the number of samples to be read according to the new address.

3. In process number 3, data UD ↓ 9 (* bit-downshifted data is denoted as UD ↓ *) in which the addition result UD of process number 2 is shifted down 9 bits by shifter 505 is supplied to selector 501. Then, the selector 501 selects and outputs the data UD ↓ 9. The selector 502 selects and outputs the address integer part ARAM (ADI) of the corresponding channel of the address RAM 511. The ARAM (ADI) includes an integer part synthesis unit 51
2 prepares. That is, the integer part synthesizing unit 512 first reads out the ADL of the channel in the address RAM 511 with the processing number 2 and fetches the upper 7 bits, then reads out the ADH of the channel with the processing number 3, and
16 bits of DH and upper 7 ADL extracted earlier
And an address integer part ARAM (AD
Obtain I). The integer part synthesizing unit 512 performs processing for synthesizing the address integer part in advance, and outputs an ARAM (ADI) at the timing of this processing number 3.

The adder 504 is composed of ARAM (ADI) + U
Calculate D ↓ 9. UD ↓ 9 (the above-mentioned integer part = overflow value) is the pitch PITX in the address decimal part with the processing number 2.
ARAM (ADI) + UD ↓ 9 adds the overflow to the address integer part, because the result of addition of the (advance value of the address) corresponds to the overflow of 9 bits of the address decimal part. It is a calculation. This addition result UD
Are output two clocks later, and are used in the next processing number 4 via the shifter 505. Further, the addition result is input to an integer part latch (ILAT) 509 and latched. This is the data of the new address integer part. The data of the address integer part of the integer part latch 509 is later provided to the selector 5
03, the ADH and the upper 7 bits of the ADL of the address in the address RAM 511 are written.

4. In the processing number 4, the addition result UD of the processing number 3 is directly input to the selector 502 (the shift amount of the shifter 505 is 0), and the selector 502 selectively outputs the data UD. The selector 501 is -LPLEN
Is selected and output. -LPLEN is a value obtained by adding a minus to the data length LPLEN of the loop portion of the waveform data to be read to make it a negative number. -LPLEN is the CPU 20
4 is designated via the control register 101. Adder 20
8 calculates -LPLEN + UD and outputs the addition result two clocks later.

The waveform data on the waveform memory 208 is composed of an attack portion and a loop portion following the attack portion. When accessing the waveform data, the start position of the loop portion (that is, the end position of the attack portion) is set to the address 0. It is the standard. Therefore, when -LPLEN + UD becomes positive (when no carry occurs), the address value has exceeded the final position of the loop portion, and in this case, it is necessary to return the address to the beginning of the loop portion. Therefore, when a carry occurs due to the addition of the processing number 4, the following processing numbers 5, 6
When no carry occurs, the following process numbers 5 and 6 are performed to return to the address near the beginning of the loop portion.

5. In the processing number 5, 32 is obtained by combining the addition result UD (new address integer part) of the processing number 4 and the address decimal part of the decimal part latch (FLAT) 510.
A bit address value UD (I & FLAT) is generated (this data generation is performed by shifter 505), and selector 50
2 selectively outputs the data UD (I & FLAT). The selector 501 selects and outputs the loop decimal part data LPFR. The LPFR is designated by the CPU 204 via the control register 101. Adder 208
Calculates UD (I & FLAT) + LPFR, and outputs the addition result two clocks later.

The loop decimal part data LPFR is offset data for correction when returning to the vicinity of the head of the loop part.
The return address was calculated for the integer part by adding -LPLEN to the address integer part at process number 4, but when returning to the vicinity of the beginning of the loop part, adjustment of the decimal part is also necessary. Value UD (I &
FLAT) and the loop decimal part data LPFR
Subtle return address adjustments are made.

The result of addition of the processing number 5 is input to a decimal part latch (FLAT) 510, and the lower 9 bits are latched. This is the data of the new address decimal part. The data of the decimal part of the address of the decimal part latch 510 is written into the lower 9 bits of the ADL of the address in the address RAM 511 via the selector 503.

6. In processing number 6, data UD ↓ 9 obtained by shifting down the addition result UD of processing number 5 by 9 bits with shifter 505 is input to selector 502, and selector 502 selects and outputs this data UD ↓ 9. The selector 501 selectively outputs -AS. -AS is the initial value of the address integer part at the time of note-on rise, and indicates data which becomes 0 in other cases. -AS is the CPU 20
4 is designated via the control register 101. Adder 50
4 calculates −AS + UD ↓ 9, and outputs the addition result two clocks later. The result of this addition is an integer part latch (IL
AT) 509 and latched. This is the data of the new address integer part. The data of the address integer part of the integer part latch 509 is transferred via the selector 503 to the ADH and ADL of the address in the address RAM 511.
Written to upper 7 bits.

In short, in the processing number 6, except for the time of note-on rising, the address integer part obtained by shifting down the addition result UD (new address value) of the processing number 5 by 9 bits is stored in the integer part latch 509 and the address RAM 51.
Write to 1. Then, when the processing number 6 is executed at the time of the note-on rising (UD is 0 at this time), the initial value of the address integer part is written to the address RAM 511 via the integer part latch 509. As described above, since the waveform data sets the start address of the loop portion as the reference address 0, the start address of the attack portion is a negative number -AS. Therefore, it is necessary to write this initial value to the address RAM 511 at the time of note-on rise.

Thereafter, the above-described processing numbers 1 to 6 are executed in the sampling cycle, so that the RAM 5
After the address written in 11 gradually changes from the attack part start address to the loop part start address, the change from the loop part start address to the loop part end address is repeated.

As described above, the processing numbers 1 to 6 are executed at the timing shown in the processing A of FIG. 8 to create the address value of each channel on the address RAM 511. An outline of the above-described process A is shown below by process number using only formulas.

1. 1. PITCH + (LTUNE) → VIBM ARAM (ADF) + PITX → UD, FLAT →
ARAM 3. ARAM (ADI) + UD ↓ 9 → UD, ILAT →
ARAM 4. -LPLEN + UD → UD (I & FLAT) (UD (I & FLAT) + LPFR → UD, FLA
T → ARAM) ((-AS) + UD ↓ 9 → ILAT → ARAM)

However, the LTUNE of the process number 1 is parenthesized to indicate that it is 0 except for the loop portion (attack portion). Similarly, -AS of process number 6 is parenthesized to indicate that it is 0 except at the time of note-on startup. The processing numbers 5 and 6 are executed only when no carry occurs in the processing number 4, so that the processing numbers 5 and 6 are parenthesized as a whole.

Next, the operation of sending addresses in the process B will be described. Before actually performing the process of sending an address from the address generator 102 of FIG. 5 at the timing shown in process B of FIG. 8, the process B control unit 515 performs pre-processing of address sending. FIG. 10 is a flowchart showing the operation of the pre-processing. Address generator 1
02 is executing the process A for the first half of the first to fifteenth channels (section 301 in FIG. 3), the process B control unit 515 executes the process A of FIG. Is performed. Further, when the address generator 102 is executing the processing A for the 16th to 31st channels in the latter half (section 30 in FIG. 3).
5), the process B control unit 515 performs the operation of FIG. 10 as a pre-process for sending out the addresses of the 16th to 31st channels. Hereinafter, the processing for the 0th to 15th channels is referred to as the first half processing, and the processing for the 16th to 31st channels is referred to as the second half processing.

In FIG. 10, in step 1001,
The first half / second half accumulator (ACC) 516 inside the processing B control unit 515 is initialized (cleared to zero). As the accumulator (ACC) 516, the 0th to 0th
The first half accumulator for accumulating the number of waveform memory accesses for the fifteenth channel and the second half accumulator for accumulating the number of waveform memory accesses for the sixteenth to thirty-first channels are provided independently.
If the process A being executed in parallel is performing the process of creating the addresses of the first half of the 0th to 15th channels, the first half of the accumulator is initialized, and the addresses of the second half of the 16th to 31st channels are set. If the process of creating is performed, the second half accumulator is initialized. In the following description of FIG. 10, the term “accumulator ACC” simply refers to the first half accumulator in the first half processing and the second half accumulator in the second half processing.

Step 1002 does not perform any processing, but the next steps 1003 to 1008
Focus on the first channel as a target channel (hereinafter referred to as a target channel). The first channel is the 0th channel in the first half processing and the 16th channel in the second half processing.

Next, in step 1003, for the target channel, the channel number, the compression method, the number of samples, and the least significant bit of the address are received. The channel number can be known from the count value CHC from the channel counter 113.

The compression method received in step 1003 is a compression method of the waveform data of the target channel to be read, and is any one of 16-bit non-compression, 8-bit non-compression, and 8-bit compression. The compression method may be different for each channel. The compression method for each channel can be understood by referring to information set in the control register 101 by the CPU 204.

FIG. 9A shows 16 waveforms in the waveform memory 208.
This shows the format of bit uncompressed waveform data. 90
1 to 906 each represent one sample of 16-bit uncompressed waveform data. Since the addresses are assigned in sample units, if the sample 901 is set as the reference position of the address 0, the addresses of the samples 902, 903, 904,... Are 1, 2, 3,. In FIG. 9B,
8 shows the format of 8-bit uncompressed or 8-bit compressed waveform data in the waveform memory 208. 911-922
Indicates one sample of 8-bit uncompressed or compressed waveform data, respectively. Since the addresses are assigned in sample units, if the sample 911 is the reference position of the address 0, the addresses of the samples 912, 913, 914,... Are 1, 2, 3,. Waveform memory 208
The access to the waveform data of
It is performed in units of 16 bits. Therefore, in the 16-bit uncompressed system, the number of samples to be read and the number of accesses to the waveform memory match. In the 8-bit non-compression or compression method, the number of samples to be read and the number of accesses to the waveform memory do not always match.

The number of samples received in step 1003 is the number of samples to be read in the target channel. The number of samples is the processing number 2 of the processing A described above.
Is obtained by taking into the processing B control unit 515 from the adder 504 an overflow amount (overflow value) of the addition result of the upper part of the 9 bits of the address decimal part. In addition, when the carry does not occur by the addition of the process number 4 of the process A,
Returning to the address near the beginning of the loop section, in this case, past samples in the sample RAM 1205 (FIG. 13) cannot be used. Therefore, the processing B control unit 515 performs processing A
Is detected, the number of samples to be read is forcibly designated as 4 so as to read all 4 samples for interpolation.

The least significant bit of the address received in step 1003 is the least significant bit of the address integer part of the target channel. The least significant bit of the address is obtained by adding the result of addition of process number 3 or process number 6 of process A (particularly, the least significant bit) from adder 504 to process B controller 5.
15 to understand.

Next, in step 1004, it is determined whether or not the number of samples is zero. If the number of samples is 0, there is no need to read out a new sample from the waveform memory 208 for this target channel, so the process proceeds to step 1009.
If the number of samples is not 0, the write pointer is incremented in step 1005, and the channel number and the number of samples for the target channel are written in the control RAM 517 in step 1006.

FIG. 7 shows the configuration of the control RAM 517.
The control RAM 517 includes a plurality of areas for storing a channel number and the number of samples to be read in the channel. The processing B control unit 515 includes a write pointer and a read pointer. When the number of samples to be read in each channel is written in the control RAM 517, the write pointer is recommended (step 1005 described above). When the number is read and the read address for the channel is transmitted, the read pointer is advanced (step 110 in FIG. 11 described later).
2). The control RAM 517 is used in a ring shape, and the write or read pointer is controlled by the control R.
When the pointer reaches one end of the AM 517, the position of the next pointer is the other end of the control RAM 517. Writing and reading are performed so that the position indicated by the read pointer follows the position indicated by the write pointer, but it is assumed that the size of the area is secured such that the write pointer does not overtake the read pointer. As with the accumulator ACC, the write pointer and the read pointer are separately provided for the first half and for the second half, respectively. When simply referred to as the write pointer and the read pointer, the first half processing indicates the one for the first half processing, and the second half processing indicates the one for the second half processing. In addition to the configuration as shown in FIG. 7, an address may correspond to each channel one by one, and the required number of samples may be written there.

Returning to FIG. 10, in step 1007, the number of necessary waveform memory accesses for the target channel is calculated and stored in the work register AT. The number of accesses is obtained from the compression method, the number of samples, and the least significant bit of the address obtained in step 1003. 16
In the bit uncompressed method, "access count = sample count"
It is. In the 8-bit uncompressed or compressed system, FIG.
When the reading of the 8-bit sample is started from the position of the 16-bit boundary as shown in FIG. 9C, the number of accesses = the number of samples / 2, and the position of the 8-bit boundary which is not the 16-bit boundary as shown in FIG. From 8
When the reading of the bit sample is started, “the number of accesses = the number of samples / 2 + 1” is obtained (however, the number of samples / 2 is truncated below the decimal point). 9 (c) and 9 (d) show an example in which four samples are read in the order of 0, 1, 2, and 3. In the case of FIG. 9 (c),
9D can be determined by the least significant bit of the address. 9 when the least significant bit of the address is 0
In the case of (c), the case of 1 is the case of FIG. 9 (d).

FIG. 4 shows that the number of required waveform memory accesses is 1 for the 0th channel, 3 for the second channel,
This is the case of 1 for the fifth channel and 2 for the seventh channel. The other channels are channels that are not sounding or whose overflow value is 0 (that is, it is not necessary to read samples from the waveform memory).

In step 1008, the accumulator A
The number of accesses AT is accumulated in CC. Step 1009
Then, it is determined whether or not the target channel is the last channel (the fifteenth channel is the last in the first half processing, and the thirty-first channel is the last in the second half processing). Step 10 by setting the channel (the number of channels is +1)
Return to 03.

If the last channel has been reached in step 1009, in step 1011 the accumulator ACC
Is determined not to exceed the maximum accessible number in the first half or the second half of the processing B for actually executing the access, and the number of accesses and the interpolation order for each channel are determined. In the present embodiment, the maximum accessible number is 32. As described with reference to FIG. 4, the time width of the section where one address is sent out in the processing B is half the time width of the section where the processing for one channel is performed at the time-division channel timing, and the first half of the processing B and the second half of the processing B In this case, 32 accesses are possible. Therefore, if the accumulative access count value of the accumulator ACC does not exceed 32, the control RAM 51
Since the number of samples of each channel in the first half or the second half written in 7 can be accessed, the number of accesses and the interpolation order of each channel are determined according to the number of samples. In this case, four-point interpolation is possible for all 16 channels in the first half or the second half. On the other hand, if the accumulative access count value of the accumulator ACC exceeds 32, it is not possible to access all the sample numbers of each channel written in the control RAM 517.
The number of accesses to any one of the channels is reduced to lower the interpolation order. As a method of determining a channel for reducing the number of times of access, for example, the following methods are available.

The number of accesses is reduced from one end in channel order. The number of accesses is reduced from the channel reproducing the 16-bit waveform. Since the waveform is a 16-bit waveform, the reduction effect is large. At that time, the number of accesses is reduced from the channel having the lower volume level. In this way, the influence on the musical sound is small. The volume level of each channel is known from the envelope value.

In this embodiment, four-point interpolation is basically performed for each channel. However, when the number of accesses is reduced, the number of samples must be ensured so that at least two-point interpolation can be performed. Therefore, the number of accesses is not reduced so that two-point interpolation cannot be performed. Also, in the case of a compressed waveform, reproduction cannot be performed if a sample in the middle is skipped.

FIG. 14 shows a specific example (including an example in which the number of accesses is not reduced) in this embodiment. FIG.
In (a) to (g), the advance amount is the advance amount of the waveform memory sample address (specifically, the sample address integer part indicating each sample recorded in the address RAM 511), and the number of samples obtained in step 1003. That is. The downward arrow ↓ indicates a convenient reference position for indicating the address advance amount (the position where reading was completed in the previous process B of the same channel). ×, ○, and ●
One sample of waveform data is shown. ● already sample RA
M indicates a sample existing in M, and ○ indicates a sample to be read from now on.

FIG. 14A shows a case where the amount of advance of the address is 0. Since the samples for the four points required for the four-point interpolation exist in the sample RAM, new reading is unnecessary and the number of accesses is zero. Naturally, the number of accesses is not reduced.

FIG. 14B shows the case where the address advance amount is one. Since three of the necessary four samples already exist in the sample RAM, only one sample is read. Therefore, one access is required regardless of the compression format. In this case, the number of accesses is not reduced.

FIG. 14C shows the case where the address advance amount is 2. Since two of the necessary four samples already exist in the sample RAM, only two samples are read. In the case of the 16-bit uncompressed format, the number of accesses is two, and in the case of the 8-bit compressed or uncompressed format, the number of accesses is one or two. In this case, the number of accesses is not reduced.

FIG. 14D shows a case where the advance amount of the address is 3. Since one of the necessary four samples already exists in the sample RAM, only three samples are read. In the case of the 16-bit uncompressed format, the number of accesses is three, and in the case of the 8-bit compressed or uncompressed format, the number of accesses is two. In this case, when the number of accesses is reduced (limited to the uncompressed format), FIG.
(D) As described below, the number of accesses is reduced by newly reading out two samples necessary for two-point interpolation.

FIG. 14E shows a case where the advance amount of the address is four. Sample RAM for 4 necessary samples
All four samples are read out because they do not exist in. 1
When the format is 6-bit uncompressed, the number of accesses is 4
In the case of the bit compression or non-compression format, the number of accesses is required two or three. In this case, when the number of accesses is reduced (limited to the uncompressed format), FIG.
(E) As described below, the number of accesses is reduced by newly reading out two samples necessary for two-point interpolation.

FIG. 14 (f) shows a case where the waveform data is in an uncompressed format and the advance amount of the address is 5 (the same applies to the case of 5 or more). Sample RAM for 4 necessary samples
All four samples are read out because they do not exist in. 1
When the format is 6-bit uncompressed, the number of accesses is 4
In the case of bit uncompressed format, the number of accesses is 2 or 3
Times needed. In this case, when the number of accesses is reduced, the number of accesses is reduced by newly reading out two samples required for two-point interpolation, as shown in the lower part of FIG.

FIG. 14 (g) shows a case where the waveform data is in the 8-bit compression format and the address advance amount is 5. Since the necessary samples for the four points do not exist in the sample RAM, all the four samples required for the four-point interpolation are read out.
Since it is a compression format, it is not possible to skip samples in the middle, so a total of five samples are read. The number of accesses is three. In the case of a compressed waveform, the amount of advance may be limited so that the case shown in FIG.

Next, referring to FIG.
02 will be described. As can be seen from FIG. 8, in the process B, one address is sent out by performing the processes of the following process numbers 1, 2, and 3 with the slot numbers 1, 3, and 5. Thereby, the waveform memory 20
8 is accessed once. The same processing is performed for slot numbers 7, 9, and 11, and one access is executed. Therefore, processing for one access is possible with three clocks, and two accesses are possible within the time per channel of the time division channel timing. It is. The access processing of the waveform memory in the processing B is not related to the processing according to the time-division channel timing of the processing A, and is sequentially performed for each channel that needs to be read. The channels and the number of samples that need to be read have been determined in the above-described preprocessing of FIG. As described with reference to FIG. 3, when the process B is performed on a certain channel, the process A on the channel has already been executed.
Is executed, the address value of the channel is already set in the address RAM 511. Hereinafter, FIG.
The processing of the processing numbers 1 to 3 of the processing B will be described with reference to FIGS.

1. In the process number 1, the selector 501
FS, and the selector 502 selects the ARAM (AD
Selectively output I). The ARAM (ADI) is an address integer part of a channel to be processed in the address RAM 511 (the order of channels for sending out an address is determined based on the control of the processing B control unit 515, which will be described later in detail with reference to FIG. 12). Yes, process number 3 of process A
The integer part synthesizing unit 512 prepares in the same manner as described above.
OFS is an offset generated and output by the processing B control unit 515, and is an added value for sequentially accessing samples of a required number of samples (16-bit data including necessary samples in the case of the 8-bit sample format). is there. FIG.
The offset OFS of each access timing in is
For example, 0 in the 0th channel, and the first time of the second channel is -2 (in the case of an 8-bit sample, -4 ← 1/2 later)
The second time is -1 (same as -2), the third time is 0, the fifth
The first time of the channel is -1 (the same as -2), the second time is 0, and the like, and as a result, the samples corresponding to the previously described の in FIG. 14 are controlled so as to be sequentially read. Since the compression system, the number of samples to be read out, and the least significant bit of the address have been obtained in step 1003, the process B control unit 515 can sequentially create and output the OFS. The adder 504 has an ARAM (AD
I) Calculate and output + OFS. The addition result UD is output after two clocks, and is used in the next process number 2 via the shifter 505.

2. In processing number 2, data UD ↓ 1 obtained by shifting down the addition result UD of processing number 1 by 1 bit by shifter 505 is input to selector 501, and selector 501 selects and outputs this data UD ↓ 1. The selector 502 selects and outputs the same UD ↓ 1 as the selector 501 when the waveform data is in the form of 16-bit samples, and outputs 0 when the waveform data is in the form of 8-bit samples. Adder 50
No. 4 adds these data and outputs an addition result two clocks later.

In short, when the waveform data is in the form of 16-bit samples, the result is the same as when the addition result of process number 1 is passed without performing addition, and the waveform data becomes 8 bits.
In the case of the bit sample format, the addition result of the process number 1 is halved and output. Since the addresses of the samples are assigned in sample units, in the case of the 8-bit sample format, if the address is halved, the position of the waveform data of the 16-bit boundary including the sample is calculated. In the case of the 16-bit sample format, it appears that the least significant bit of the addition result of processing number 1 is discarded.
UD ↓ 1, which is input to 1,502, is data including one bit after the decimal point. Since the adder 504 performs addition including the one bit after the decimal point, the least significant bit is not discarded. This processing number 2 indicates that the waveform data address to be accessed has been calculated.

3. In the processing number 3, the selector 501 selectively outputs the address reference value WAD, and the selector 502 selectively outputs the addition result UD of the processing number 2. Adder 504
Adds these data and outputs an addition result MALAT two clocks later. The address obtained by the processing number 2 is an address using the head position of the loop portion as a reference of the address 0. On the other hand, actually, the waveform data is stored in the waveform memory 20.
8 is stored at a predetermined address. Therefore, the read address is converted to an address on the waveform memory 208 by adding the address reference value WAD of the waveform data (the address of the beginning of the loop portion of the waveform data on the waveform memory 208).

The addition result MALAT is supplied to the address terminal of the waveform memory 208 via the read integer part latch 508, whereby the waveform data at the address is read.

The operation of the process B is performed by the process B control unit 51
5 is performed. Hereinafter, the processing B control unit 51
Operation 5 will be described. FIG. 11 shows an address generator 102.
9 is a flowchart showing the operation of the process B control unit 515 when performing the above-described process B address sending operation. The operation in FIG. 11 is performed in parallel with the operation of the pre-processing in FIG. For example, when the address generator 102 is performing the process A for the first half to the fifteenth channel, the process B control unit 515 performs the operation of FIG. In parallel with this, the process B control unit 515 performs the address sending process of FIG. 11 for the 16th to 31st channels for which the preprocessing has already been completed.

In FIG. 11, in step 1101,
It is determined whether the value of the read pointer indicating the control RAM 517 shown in FIG. 7 matches the value of the write pointer. The value of the write pointer refers to the value of the write pointer updated in the process of FIG. 10 executed immediately before. If the value of the read pointer is different from the value of the write pointer in step 1101, step 11
In step 023, the read pointer is incremented, and in step 1103, the channel number and the number of samples indicated by the read pointer are read from the control RAM 517.

Next, in step 1104, the compression method and the least significant bit of the address of the channel of the read channel number are received. These may be obtained in the same manner as in step 1003 of FIG. 10, but the values obtained in FIG. Step 110
Reference numeral 5 indicates that the address sending processing to be performed in the next step 1106 is the first access, although no particular processing is performed. Step 1106
Instructs each block of the address generator 102 to create a read address for the first access. Thus, the operations of the process numbers 1 to 3 of the process B described above are executed, and the address is sent out at the first access.

Further, in step 1107, it is determined whether or not the number of accesses to the channel has been completed. If the number of accesses has not been completed, the process proceeds to step 1108 (step 1108 does not perform any processing, but indicates that the next access will be performed in step 1106). Perform When the number of times of access to the channel is completed in step 1107, the process returns to step 1101.

If the value of the read pointer matches the value of the write pointer in step 1101, it means that there is no more address to be sent to the waveform memory 208, and the flow advances to step 1109. Step 1
At 109, it is determined whether or not there is an extra access time.
If there is extra access time, refreshing of the waveform memory 208 and access processing of the waveform memory 208 from the CPU 204 are executed in step 1110 using the empty time slot, and the process returns to step 1109. When the extra access time runs out, the process ends.

Next, the decoder 104 of FIG. 1 will be described in detail. FIG. 12 shows the decoder 104 and the interpolator 1
3 shows a block configuration of No. 03. The decoder 104 includes a selector 1201, an adder 1202, a delay circuit 1203, a selector 1204, a sample RAM 1205, an expansion coefficient generator 1206, multipliers 1207 and 1208, and a controller D1209.

FIG. 13 shows the configuration of the sample RAM 1205. The sample RAM 1205 includes four sample storage areas for each channel. The four sample storage areas are used in a ring shape. That is, a pointer is provided for each channel, and when writing a sample, writing is performed at the position indicated by the pointer and the pointer is advanced by one. For example, if the pointer is the i-th channel in FIG.
Sample 1 → 2 → 3 → 4 → 1 → 2 →... In the sample RAM 1205 of FIG. 12, the terminals described as “1D” and “2D” are terminals for reading the sample one before and two from the current pointer position, respectively.

The operation of the decoder 104 will be described in detail with reference to FIGS. The waveform data read from the waveform memory 208 based on the address sent out in the process B is input to the selector 1201 and the delay circuit 1203. The size of this waveform data is 16 bits, and the format is 16 bits uncompressed, 8 bits.
Either bit uncompression or 8-bit compression. If the data is 8-bit compressed or uncompressed data,
Since only one of the input upper 8 bits and lower 8 bits of the 16 bits is a desired sample, the selector 1
At 201, a desired sample of either the upper 8 bits or the lower 8 bits is selected.

The control section D1209 outputs a selection control signal of the selector 1201. The control unit D1209 performs processing B
Decoder control data output by the control unit 515 in synchronization with the address transmission (channel number, compression format, and, in the case of an 8-bit sample, whether the desired sample is upper 8 bits or lower 8 bits, in the case of an 8-bit sample). Based on the information shown), it is determined whether to select the upper 8 bits or the lower 8 bits of the input waveform data.

The uncompressed or compressed 8-bit sample output from the selector 1201 is input to an adder 1202. Further, the adder 1202 includes the sample RA.
The samples one and two before the current pointer position are read from M1205, and the multipliers 1207 and 1208 input the multiplication results obtained by multiplying them by the expansion coefficient from the expansion coefficient generator 1206, respectively. The adder 1202 is connected to the selector 1
Current sample from 201 and multipliers 1207,12
08 is added, and the addition result is added to the selector 12.
Enter in 04. When the waveform data currently being processed is an 8-bit compressed waveform, a predetermined expansion coefficient is output from the expansion coefficient generation unit 1206, one sample is reproduced from the compressed sample, and output from the adder 1202. If the waveform data currently being processed is an 8-bit uncompressed waveform,
The expansion coefficient generator 1206 outputs 0 as an expansion coefficient, and an uncompressed sample is output through the adder 1202.

On the other hand, when the sample read from the waveform memory 208 is 16-bit uncompressed data, the sample is input to the selector 1204 after a predetermined time delay by the delay circuit 1203. The delay is performed by the delay circuit 1203 because the 8-bit sample is input to the selector 1204 via the adder 1202, so that the timing is adjusted.

The selector 1204 selects and outputs the sample from the delay circuit 1203 in the case of a 16-bit sample, based on the selection control signal from the control unit D 1209,
In the case of a bit sample, the sample from the adder 1202 is selectively output. The sample output from the selector 1204 is written into the sample RAM 1209 at the position indicated by the pointer of the channel, and the pointer is advanced by one.

The above operation is performed for each sample of each channel in synchronization with the timing at which the address generator 102 sends out the address in the process B. In the section 303 of the first half channel of decoding in FIG. 3, the above operation is performed for the 0th to 15th channels, thereby
A sample is set in the sample storage area of the 0th to 15th channels of the AM 1205. The same applies to the 16th to 31st channels in the latter half. Basically, since four-point interpolation is performed, four samples (including samples already stored) are prepared in the sample RAM 1205 for each channel. However, the number of channels for which the interpolation order is reduced from four to two due to the reduction in the number of accesses to the waveform memory is two samples.

Next, the interpolator 103 shown in FIG. 1 will be described in detail. In FIG. 12, an interpolator 103 includes a multiplier 1
210, interpolation coefficient generation unit 1211, interpolation accumulator 121
2 and a control unit I1213.

When the interpolator 103 starts the first-half processing, that is, the interpolation of each channel for the 0th to 15th channels, all four samples of each channel used for the interpolation are set in the sample RAM 1209. The same applies to the 16th to 31st channels in the latter half. The interpolator 103 sequentially performs interpolation processing on the 0th to 15th channels in the first half and on the 16th to 31st channels in the second half in accordance with the time division channel timing. The control unit I1213 receives the control clock Φ, the channel count value CHC, and the interpolation order (output by the processing B control unit 515 corresponding to each channel), and performs processing in accordance with the time-division channel timing. Control the block. The interpolation process for one channel is as follows.

First, under the control of the control unit I1213,
Four samples of the channel are sequentially read from the sample RAM 1205. The read samples are sequentially input to the multiplier 1210. In synchronization with the input of the four samples, interpolation coefficients to be multiplied to each sample are sequentially input from the interpolation coefficient generation unit 1211 to the multiplier 1210. The interpolation coefficient generation unit 1211 generates and outputs an interpolation coefficient corresponding to each sample based on the address decimal part of the channel output from the address generator 102. This address decimal part corresponds to the address R of the address generator 102 in FIG.
This is output from the AM 511 via the interpolation decimal part latch 513. The multiplier 1210 multiplies each sample by the corresponding interpolation coefficient, and accumulates the multiplication result in the interpolation accumulator 1212. Thus, interpolated musical tone waveform data is generated and output. For channels whose interpolation order is reduced from four to two due to the reduction in the number of accesses to the waveform memory, two-point interpolation is performed using two samples instead of four samples to obtain interpolated tone waveform data.

In the above embodiment, it is determined in step 1011 of FIG. 10 whether or not the accumulative number of accesses of the accumulator ACC does not exceed the maximum accessible number of 32. The number, the number of accesses, and the interpolation order are determined.
The maximum accessible number may be determined with priority given to performing other processing. For example, if it is known in advance that the waveform memory will be refreshed or accessed by the CPU, the number of accesses for such processing is secured in advance, and the remaining number is set as the maximum accessible number and the determination in step 1011 is performed. May be performed.

In particular, when a DRAM is used as a waveform memory, refreshing is always required, and therefore, the number of accesses for the refreshing should be preferentially secured. Also, reading / writing of the waveform memory from the CPU is as follows.
It is advisable to respond according to the degree of urgency. For example, when the urgency of the waveform memory access from the CPU is low, the access is performed using an empty time slot not used in the sound source channel. When the degree of urgency is high, a portion for waveform memory access from the CPU is secured first, and the rest is used for the sound source channel.

Further, in the above embodiment, as shown in FIG. 4, continuous waveform memory access is performed in the front slot of the first half and the second half in which the processing B and the decoding are performed. You may. For example, for the above-mentioned refresh or access from the CPU, the processing is performed in the front slot in the section, and continuous waveform memory access for each channel is performed in the rear slot. It may be. In this case, however, it is necessary to start the interpolation process of the first half section 304 after the processing of the first half section 303 of FIG. 3 is completed and all the samples necessary for interpolation are prepared in the sample RAM. Processing is the same). Therefore, it is necessary to shift the section in which interpolation is performed (it suffices to start the first half of the interpolation process after the first half of the decode process is completed, and to start the second half of the interpolation process after the second half of the decode process is completed).

Further, in the above embodiment, one sampling period is divided into half (first half and second half), and the first half processing and the second half processing are alternately performed. Not limited to For example, one sampling cycle may be divided into 1/3, 1/4,... And processing may be performed in units of those sections. Instead of equal division, irregular sections may be divided (for example, 0th to 1st
4 channels and 15th to 31st channels).
Further, one sampling period may be used as a unit without dividing the section. However, before the address is sent in the process B and the waveform memory is accessed, the rewriting of the address RAM by the process A is not performed.
Need to guarantee. For this purpose, for example, when the sections are not divided, two sets of address RAMs are prepared and the processing A
It is necessary to employ a method of alternately using two sets of address RAMs for rewriting the address by the above and sending the address by the processing B. If one sampling cycle is divided into the first half and the second half, processing A and processing B can be performed alternately with one set of address RAM, so that the circuit configuration can be simplified and rationalized. .

[0112]

According to the first or second aspect of the present invention,
Prior to reading the waveform memory, an address for each channel is created and temporarily stored in the address storage means.
Further, the number of accesses is calculated based on the advance amount of the address of each channel, and the waveform memory is continuously accessed by the number of accesses. Further, the waveform samples read from the waveform memory are temporarily stored in the waveform sample storage means, and the musical tone generation means generates a musical tone for each channel sampling period based on the waveform samples of each channel stored in the waveform sample storage means. Generate. Since the address and the waveform sample are buffered in the address storage means and the sample storage means, the timing of reading the waveform sample can be appropriately adjusted, and continuous access can be performed in accordance with the speed of the waveform memory. Therefore, when there is no need to read out waveform samples on a certain channel, or when only a small number of waveform samples need to be read out because a buffered waveform sample can be used on a certain channel, etc. The time slot can be transferred to another processing. Moreover, since the remaining time slots can be used for access in other channels, the number of cases where the interpolation order must be reduced due to such a relationship between channels is reduced.

According to the invention of claim 6, an accumulating means and a judging means are further added to the structure of claim 1 to accumulate the number of times of access for a predetermined number of channels, and to make an access corresponding to the predetermined number of channels. Since it is determined whether access is possible for the accumulated number of times during the period,
In addition to the effects of the invention described above, it is possible to know beforehand whether necessary access to the predetermined number of channels is possible before starting the waveform memory access, and to cope with it. In particular, in the invention according to claim 8,
If the determination unit determines that the number of accesses is not possible, the number of accesses to any one of the predetermined number of channels is reduced (the order of interpolation is reduced). The case of reduction can be minimized.

According to the third or seventh aspect of the present invention, the sampling period is divided into a plurality of sections and the processing is performed in units of sections, so that the circuit configuration such as the address storage means can be simplified. In particular, the sampling period is set to 1/2
And the first half processing and the second half processing, only one set of address storage means is required.

According to the fourth aspect of the present invention, it is possible to properly reproduce a waveform sample even when returning to the vicinity of the head of the loop portion. According to the invention according to claim 5 or 9, the first
Utilizing the extra time of the access by the access means, other processing by the second access means (for example, refresh processing of the waveform memory of the DRAM configuration or access of the waveform memory by the CPU) is possible.

As described above, according to the present invention, in the sound source of the waveform memory reading system which simultaneously generates musical tones for a plurality of channels by the time-division channel operation, the waveforms can be efficiently generated by the necessary amount for each channel. The memory can be accessed.

[Brief description of the drawings]

FIG. 1 is a block diagram of a sound source unit to which a sound source device according to the present invention is applied.

FIG. 2 is an overall block configuration diagram of an electronic musical instrument to which the tone generator of the embodiment is applied.

FIG. 3 is a diagram showing timings of main parts in a sound source unit according to the embodiment;

FIG. 4 is a diagram showing a state of a channel during each processing of FIG. 3;

FIG. 5 is a block diagram of an address generator.

FIG. 6 is a diagram showing a memory map of an address RAM of FIG. 5;

FIG. 7 is a configuration diagram of a control RAM.

FIG. 8 is a timing chart of an address generator.

FIG. 9 is a diagram showing a compression method of waveform data.

FIG. 10 is a flowchart showing the operation of a process B control unit during process A;

FIG. 11 is a flowchart illustrating an operation of a process B control unit during a process B;

FIG. 12 is a configuration diagram of a decoder.

FIG. 13 is a configuration diagram of a sample RAM.

FIG. 14 is a diagram showing a specific example of access frequency reduction according to the embodiment;

[Explanation of symbols]

101: control register, 102: address generator, 10
3 Interpolator, 104 Decoder, 105 Volume change control unit, 106 Channel (ch) accumulator, 107 Effect circuit, 108 Refresh counter, 109 CPU
Access control unit, 110, 111 ... selector, 112 ...
System clock generator, 113 channels (ch)
Counter, 204 central processing unit (CPU), 207
Sound source unit, 208: waveform memory, 210: digital-to-analog converter (DAC), 211: sound system (S
S), 212: external storage device, 213: bus, 501,
502, 503 ... selector, 504 ... adder, 505 ...
Shifter, 506: vibrato modulator, 507: octave (OCT) shifter, 508: read integer latch (509), integer latch (ILAT), 510: decimal latch (FLAT), 511: address RAM, 51
2 ... integer part synthesizing part, 513 ... interpolation decimal part latch, 51
4 ... Control unit A, 515 ... Processing B control unit, 517 ... Control R
AM, 516: Accumulator (ACC).

Claims (9)

(57) [Claims] 1. A waveform memory tone generator for generating musical tones of a plurality of channels by operating in a predetermined sampling cycle in a time-division manner on a plurality of channels, wherein the waveform memory stores waveform samples. A device that can be accessed a predetermined number of times; address storage means for storing an address of each channel; waveform sample storage means for storing a waveform sample of each channel; An address creation unit for creating an address of a channel and storing the address in the address storage unit; an access count calculation unit for calculating an access count of the waveform memory for each channel based on an advance amount of an address of each channel; Address of each channel stored in the address storage means A first access means for continuously accessing the waveform memory according to the number of access times of each channel calculated by the access number calculation means, and storing a read waveform sample of each channel in the waveform sample storage means; A tone generator for generating a tone for each sampling period of each channel based on the waveform sample of each channel stored in the waveform sample storage. 2. A waveform memory tone generator for generating a musical tone of a plurality of channels by operating in a predetermined sampling cycle in a time-division manner on a plurality of channels, wherein the waveform memory stores waveform samples. An access unit that can be accessed a predetermined number of times, an address storage unit for storing an address of each channel, and a waveform sample storage unit for storing n (n is an integer of 2 or more) waveform samples for each channel Prior to reading out the waveform memory, an address creating means for creating an address for each channel and storing the address in the address storage means; and based on an advance amount of the address of each channel, to the waveform memory for each channel. Access number calculating means for calculating a required number of times of access; Based on the address of each channel stored in the means, the waveform memory is continuously accessed by the number of times of access of each channel calculated by the number of times of access calculation means, and each of the waveform memories already stored in the waveform sample storage means is accessed. First access means for sequentially replacing the waveform samples of the respective channels read out by the continuous access from the waveform samples having the smallest addresses among the n waveform samples of the channel; A waveform memory tone generator comprising: a tone generator for generating a tone for each sampling period of each channel by performing an interpolation process using n waveform samples. 3. The method according to claim 1, wherein the sampling period is divided into m (m is an integer of 2 or more) sections. 3. The waveform memory tone generator according to claim 1, wherein the waveform memory is accessed continuously. 4. The waveform data stored in the waveform memory includes an attack section and a loop section, and the address creating section is configured to execute the processing when the created address enters the loop section from the attack section of the waveform data to be read in the channel. For each cycle of the loop portion of the waveform data, return the address in progress in the reverse direction and repeatedly create the same address in the loop portion, the access count calculating means, when the return of the address is executed, 3. The waveform memory tone generator according to claim 1, wherein a predetermined number of accesses is specified for the channel regardless of the advance amount of the address. 5. The apparatus according to claim 1, further comprising a second access unit for performing at least one of reading and writing of the waveform memory, wherein the second access unit utilizes a remaining time after the access of the waveform memory by the first access unit. hand,
3. The waveform memory tone generator according to claim 1, wherein the waveform memory is accessed. 6. A waveform memory tone generator for generating musical tones of a plurality of channels by operating in a predetermined sampling cycle in a time-division manner on a plurality of channels, wherein the waveform memory stores waveform samples. A device that can be accessed a predetermined number of times; an address storage device for storing an address of each channel; a waveform sample storage device for storing a waveform sample of each channel; Address creation means for creating an address of a channel and storing the address in the address storage means; access number calculation means for calculating the access number of the waveform memory for each channel based on the amount of advance of the address of each channel; Access number calculation means for a number of channels Accumulating the calculated number of accesses, and accumulating means for outputting the accumulated number of times, within the access period corresponding to said predetermined number of channels,
Determining means for determining whether access is possible for the cumulative number of times; and if the determining means determines possible, calculating by the access number calculating means based on an address of each channel stored in the address storage means. The waveform memory is continuously accessed by the number of accesses of each
First access means for storing the read waveform samples of each channel in the waveform sample storage means; and generating musical tones for each channel sampling period based on the waveform samples of each channel stored in the waveform sample storage means. A waveform memory sound source device comprising: a musical sound generating means. 7. The method according to claim 1, wherein the sampling period is divided into m (m is an integer of 2 or more) sections, and the accumulating means performs, for each of the divided sections, the number of accesses to a plurality of channels to be processed in the section. The determination means performs the determination for each of the divided sections using the section as the access period. The first access means performs processing for each of the divided sections in each of the divided sections. 7. The waveform memory tone generator according to claim 6, wherein the waveform memory is continuously accessed for a plurality of channels to be accessed. 8. The waveform memory tone generator according to claim 6, wherein said determination means reduces the number of times of access to any one of said predetermined number of channels when it is determined that said determination is impossible. 9. The apparatus according to claim 9, further comprising: a second access unit for performing at least one of reading and writing of the waveform memory, wherein the second access unit is configured to perform the second access when the determination unit determines that it is possible.
7. The waveform memory tone generator according to claim 6, wherein the access unit accesses the waveform memory by using a portion of the total number of accesses within the access period which is not used in the access by the first access unit. .