JPH09139734A - Frame synchronization circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce mis-discrimination of synchronization establishment by discriminating it to be established synchronization when all unique word detection information having been detected and recorded in advance in two preceding frames are coincident when a CPU detects unique word information. SOLUTION: A ring buffer 2 stores unique word detection information in received data detected by a unique word detector 1 to a dual port RAM. Then a value of an address scanner 3 designating an address is latched by an address latch 4 in the case of storing the unique word to the ring buffer 2 and given to a CPU 5. The CPU 5 in the case of detecting a unique word discriminates it to be established synchronization when all unique word detection information having been detected and recorded in advance in two preceding frames are coincident.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a frame synchronization circuit used especially on the receiving side for establishing frame synchronization between transmission and reception, which is necessary when transmitting a pulse signal in frame units.

[0002]

2. Description of the Related Art Conventionally, as a frame synchronizing circuit of this type, a unique word (hereinafter abbreviated as UW) inserted at the beginning position of each frame for detecting synchronization is simply detected twice in succession. The method is taken that synchronization has been established.

[0003]

However, such a conventional method has a problem that when the same bit pattern as UW occurs due to a burst error or the like, it is erroneously recognized as "synchronization establishment".

It is an object of the present invention to provide a frame synchronization circuit which eliminates the above-mentioned drawbacks in the prior art, reduces the probability of mistaking it as establishment of synchronization, and can establish synchronization with high reliability. .

[0005]

To achieve this object, a frame synchronization circuit according to the present invention, when receiving frame data, detects a unique word included in the frame data. A unique word detector that outputs a unique word detection pulse, a ring buffer that records the unique word detection information output by the unique word detector in a dual port RAM, and the dual port RAM when the ring buffer records the unique word The address scanner that specifies the address of the address, the address latch circuit that latches the value of the address scanner when a unique word is detected, and the value of the ring buffer and the address latch when the unique word is detected are referred to for synchronization. Equipped with a CPU that determines whether or not it has been established When the unique word is detected, the CPU assigns an address corresponding to the unique word detected at least k frames before (k = n-1) in the ring buffer for n (n is an integer of 2 or more) frames before the unique word is detected. The recorded unique word detection information is collated, and if all match, it is determined that synchronization has been established.

[0006]

BEST MODE FOR CARRYING OUT THE INVENTION In the present invention, at least a predetermined number of K (an integer of 2 or more) of UW detection information detected by the UW detector is sequentially recorded in the ring memory, and the recorded UW detection information is recorded. Is used to determine the establishment of synchronization.

[0007]

1 shows an embodiment of the present invention, in which 1 is a unique word (UW) detecting circuit for detecting a unique word (UW) from received data 0, 2 is a ring buffer such as dual port RAM, 3 Is an address scanner, 4 is an address latch, 5 is a CPU, and 6 is a synchronization establishment determination output. The UW detection information detected by the UW detector 1 is sequentially recorded in the ring buffer 2 as shown in FIG. The UW detection information recorded in the ring buffer 2 is controlled by the address scanner 3 and the address latch 4, and the CPU
5 is used to make a synchronization establishment determination.

Below, the processing flow of FIG. 2 and FIGS.
The operation of this embodiment will be described for the case of n = 2 with reference to the time chart of the signal of FIG. a) UW detection pulse 11 from received data 01 in FIG.
Is detected, the CPU 5 executes interrupt processing (step 50). b) The address latch 4 latches the value of the address scanner 3 as the address A by the UW detection pulse 11 (step 51). c) In FIG. 3, the data 21 of the address 31 one frame before the current address of the ring buffer 2 is searched to check whether or not there is UW detection (step 52). In this case, one frame before is adopted with K = n-1 = 1. d) If there is data representing UW detection in the data of the address one frame before in FIG. 3, synchronization is established (steps 53 and 55). However, if there is no data indicating UW detection in the data of the address one frame before, the synchronization is not established (steps 53 and 54). The determination output 61 for establishing synchronization is obtained by performing the above processing.
Is output.

On the other hand, FIG. 4 shows a case where UW erroneous detection is performed due to a burst error or the like. At time t _x of address 32, UW detection pulse 12 is obtained from received data 02,
The data 22 of _{x and} the data 22 of A-n _(x-1) one frame before are compared, but since they do not match, synchronization is not established. Further, the address data search one frame before, as shown in step 52 of FIG.
If the processing is extended so as to compare the UW detection data three frames before, there is an advantage that the reliability of synchronization establishment can be increased.

[0010]

As described above in detail, according to the present invention, the problem of false detection of synchronization establishment due to false detection of UW can be solved.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention.

FIG. 2 is a flowchart showing a processing operation in the present invention.

FIG. 3 is a time chart showing the operation of the present invention.

FIG. 4 is a time chart showing the operation of the present invention.

[Explanation of symbols]

 0 Received data 1 Unique word detector 2 Ring buffer 3 Address scanner 4 Address latch 5 CPU 6 Synchronization establishment judgment output 51 to 55 Step number of CPU interrupt processing 01 Received data (when there is no false detection) 11 UW detection pulse (wrong detection) 21) Ring buffer data (without false detection) 31 Ring buffer address (without false detection) 61 Synchronization establishment judgment output (without false detection) 02 Received data (with false detection) 12 UW detection pulse (with false detection) ) 22 ring buffer data (with erroneous detection) 32 ring buffer address (with erroneous detection) 62 synchronization establishment judgment output (with erroneous detection)

Claims (1)

[Claims] 1. A unique word detector that outputs a unique word detection pulse when a unique word included in the frame data is detected when the frame data is received, and an output from the unique word detector. A ring buffer for recording the unique word detection information in the dual port RAM, an address scanner for designating the address of the dual port RAM when the ring buffer records the unique word, and a value of the address scanner for detecting the unique word. An address latch circuit for latching; and a CPU for determining whether or not synchronization is established by referring to the values of the ring buffer and the address latch when detecting the unique word, wherein the CPU is the unique word When detected, the ring buffer The unique word detection information recorded at the address corresponding to the unique word detection at least k frames before (k = n−1) over n (n is an integer of 2 or more) frames before unique word detection is collated, and all A frame synchronization circuit configured to determine that synchronization has been established when the two match.