JPH09139656A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To eliminate the need for a margin that takes dispersion in process into account by suppressing fluctuation in an operation margin due to dispersion in the process. SOLUTION: A basic circuit 1 of this device is made up of transistors(TRs), operated based on an input signal IN to provide an output of a signal OUT in response to the input signal IN. An adjustment TR 2 controls a current flowing in the basic circuit 1 to adjust the operating speed of the basic circuit 1. A detection circuit 3 detects the operating speed of the basic circuit 1. A control circuit 4 controls a current drive capability of the adjustment TR 2 so that the operating speed of the basic circuit 1 reaches the preset speed based on the detection result of the detection circuit 3.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device,
Specifically, it relates to improvement of characteristics of a circuit formed on a semiconductor device.

Although the operating speed of semiconductor devices has been increased due to the recent miniaturization and higher integration of semiconductor devices, variations in device characteristics cannot be ignored due to process variations during manufacturing. Such variations in element characteristics cannot be particularly ignored in an oscillation circuit or the like that creates a certain time inside a semiconductor device. However, at present, no good circuit has been devised to eliminate this process variation. Therefore, circuit design is performed including a margin in consideration of process variations.

Therefore, if variations in characteristics can be detected by the semiconductor device itself and a certain time as an absolute value can be measured in the semiconductor device, a margin considering process variations is not necessary, and a highly accurate semiconductor device can be obtained. Can be developed.

[0004]

2. Description of the Related Art A dynamic RAM (DRAM), which is one form of a semiconductor device, generally has a self-refresh function. The self-refresh function is to enter the refresh operation mode of the memory cell by itself when a predetermined time (for example, 100 microseconds) has elapsed after applying a predetermined input signal. With this self-refresh function, it is necessary to measure an absolute time inside the DRAM.

Usually, this time measurement is performed by a ring oscillator which outputs an oscillation signal of a predetermined frequency and a counter which counts pulses of the oscillation signal. As shown in FIG. 4, the ring oscillator 50 is formed by connecting an odd number (9 in FIG. 4) of CMOS inverters 51 in series. Each CMOS inverter 51 sequentially outputs a signal obtained by inverting the potential of the input signal from the drains of the pMOS transistor and the nMOS transistor connected in series between the high potential power supply and the low potential power supply to the CMOS inverter 51 of the next stage. Output signal φ of final stage CMOS inverter 51
2 is input to the first-stage CMOS inverter 51 as an input signal φ1. Therefore, the oscillation cycle of the ring oscillator 50 is the sum of the delay times of all the CMOS inverters 51.

[0006]

DISCLOSURE OF THE INVENTION Problems to be Solved by the Invention
If there is a process variation of M, the CMOS inverter 5
The characteristics of the pMOS transistor and the nMOS transistor that form element 1 vary, and the delay time of each CMOS inverter 51 varies from the design value. Therefore, there is no choice but to design the circuit in consideration of process variations.

The present invention has been made in order to solve the above-mentioned problems, and an object thereof is to suppress fluctuations in operating speed due to process variations and to eliminate the need for a margin considering process variations. It is to provide a highly accurate semiconductor device.

[0008]

FIG. 1 is a diagram illustrating the principle of the present invention. The basic circuit 1 is composed of transistors, operates based on the input signal IN, and outputs a signal OUT corresponding to the input signal IN.

The adjusting transistor 2 adjusts the operating speed of the basic circuit 1 by controlling the current flowing through the basic circuit 1. The detection circuit 3 detects the operating speed of the basic circuit 1.

The control circuit 4 controls the current drive capability of the adjusting transistor 2 based on the detection result of the detection circuit 3 so that the operating speed of the basic circuit 1 becomes a preset value. (Operation) Therefore, when the operating speed of the transistor fluctuates from the preset value due to the process variation, the operating speed of the basic circuit 1 fluctuates from the preset value. The operating speed of the basic circuit 1 is detected by the detection circuit 3, and the current drivability of the adjusting transistor 2 is controlled by the control circuit 4 based on the detection result, and the current flowing through the basic circuit 1 is controlled. Therefore, the fluctuation of the operating speed of the basic circuit 1 from the preset value is suppressed.

[0011]

BEST MODE FOR CARRYING OUT THE INVENTION An embodiment of the present invention will be described below with reference to FIGS. As shown in FIG. 2, the semiconductor device 10 of the present embodiment includes a ring oscillator 11,
Adjustment transistor 21, detection circuit 22, control circuit 23
And an nMOS transistor 24 as a reset circuit.

The ring oscillator 11 includes an odd number (nine in FIG. 2) of CMOS inverters 12 to 12 as a basic circuit.
20 are connected in series. Each CMOS inverter 12
18 to 20 are p connected in series between the power source Vcc as a high potential power source and the ground GND as a low potential power source.
It is composed of a MOS transistor and an nMOS transistor. The CMOS inverter 19 is composed of a pMOS transistor and an nMOS transistor connected in series between the power supply Vcc and the adjusting transistor 21.

Each of the CMOS inverters 12 to 19 sequentially delays the signals S1 to S8 obtained by inverting the potential of the input signal by the delay time thereof and successively outputs the CMOS inverters 13 to 2 of the next stage.
Output to 0. The final stage CMOS inverter 20 is a CM
The oscillation signal φ2 is output by inverting the potential of the output signal S8 of the OS inverter 19, and the oscillation signal φ
2 is output as the input signal φ1 to the CMOS inverter 12 in the first stage.

Therefore, the oscillation cycle of the ring oscillator 11 is the sum of the delay times of all the CMOS inverters 12-20. The adjustment transistor 21 is an nMOS transistor, the drain is connected to the source of the nMOS transistor forming the CMOS inverter 19, and the source is connected to the ground GND. The adjustment transistor 21 is an nMO that constitutes the CMOS inverter 19.
CM by controlling the current flowing through the S transistor
The operating speed of the OS inverter 19 is adjusted so that the operating speed of the ring oscillator 11 becomes a preset value.

The detection circuit 22 includes three CMOS inverters 13 to 15 constituting the ring oscillator 11 and a NAND.
A pulse generating circuit including a circuit 25, which outputs a pulse based on a change in an input signal,
The operating speed of the inverters 12 to 20 is detected.

The NAND circuit 25 is a CMOS inverter 1
The output signal S1 of 2 and the output signal S4 of the CMOS inverter 15 are input, and a signal S9 based on both signals S1 and S4 is output. Therefore, when the output signal S1 changes from H level to L level, as shown in FIG.
An L level pulse is output to. This output signal S9
The L-level pulse width T1 of the CMOS inverter 13 to
This is the sum of the delay times of 15 and the CMOS inverter 13
Detecting the delay times of ˜15 means detecting the operating speeds of the CMOS inverters 13-15.

The control circuit 23 outputs the output signal S of the detection circuit 22.
Adjustment transistor 2 based on L level pulse of 9
1 to control the current drive capacity. Control circuit 23
Includes an integrator circuit including a resistor R1 and a capacitor C1, and a pMOS transistor 26 as a switch.

That is, the source of the pMOS transistor 26 is connected to the power supply Vcc via the resistor R1, the drain is connected to the ground GND via the capacitor C1, and is connected to the gate of the adjusting transistor 21. The gate of the pMOS transistor 26 is NAND
The output signal S9 of the circuit 25 is input.

Therefore, an L-level pulse is added to the output signal S9.
The pMOS transistor 26 is
Turn on. When the pMOS transistor 26 turns on, the
Source V _CCVia resistor R1 and pMOS transistor 26
Then, the current I1 flows. Based on this current I1,
The sensor C1 is charged, and the output signal S9 is applied to the capacitor C1.
A reference voltage N1 having a value proportional to the L-level pulse width T1
Is generated. The capacitor C1 is the generated reference voltage
Supply N1 to the gate of the adjusting transistor 21
Controls the current drive capacity of the adjusting transistor 21
Therefore, the current flowing through the CMOS inverter 19 is controlled.
The operating speed of the CMOS inverter 19 by adjusting
Adjust.

The drain of the nMOS transistor 24 is p
It is connected to the drain of the MOS transistor 26, and its source is connected to the ground GND. The output signal S2 of the CMOS inverter 14 is input to the gate of the nMOS transistor 24. The nMOS transistor 24 has a signal change opposite to the signal change in which the pulse generation circuit 22 generates an L level pulse, that is, an H level output signal S.
By turning on based on 2, the capacitor C1 is discharged to bring the reference voltage N1 to the ground GND level.

Next, the operation of the ring oscillator 11 configured as described above will be described with reference to FIG. FIG. 3 (a)
, The input signal φ1 of the CMOS inverter 12
Changes from H level to L level, a signal change is transmitted to each of the CMOS inverters 12 to 20 with a delay time corresponding to the operating speed of each of the CMOS inverters 12 to 20. In this case, the output signal S8 of the CMOS inverter 19 changes from H level to L level.

Based on the change of the output signal S1 from L level to H level, the output signal S9 of the NAND circuit 25 is L level.
The output signal S9 goes to the H level based on the change of the output signal S4 from the H level to the L level. That is, as the output signal S9, an L level pulse having a pulse width T1 from the time when the output signal S1 changes to the H level to the time when the output signal S4 changes to the L level is output.

The pMOS transistor 26 is turned on based on the L level pulse of the output signal S9, and the current I1 flows through the pMOS transistor 26. At this time, the output signal S
Since the nMOS transistor 24 is turned on while 2 is at the H level, the capacitor C1 is not charged and the reference voltage N
1 becomes the ground GND level.

When the output signal S2 becomes L level during the period in which the L level pulse of the output signal S9 is output, the nMOS transistor 24 turns off and the capacitor C
1 is charged by the current I1, and the reference voltage N1 having a value proportional to the pulse width T1 is generated in the capacitor C1.

The current driving capability of the adjusting transistor 21 is controlled based on the value of the reference voltage N1, and the current flowing through the nMOS transistor of the CMOS inverter 19 is controlled. Thereby, the operating speed of the CMOS inverter 19 is adjusted, and the changing speed of the output signal S8 from the H level to the L level is adjusted.

Now, it is assumed that the capability of the transistor formed on the semiconductor device 10 is higher than the design value due to process variations. Then, since the delay time of each of the CMOS inverters 12 to 20 of the ring oscillator 11 is short, the L-level pulse width T1 of the output signal S9 becomes short.

Therefore, the period during which the current I1 flows through the pMOS transistor 26 becomes short, and as a result the potential of the reference voltage N1 becomes low. Therefore, the current driving capability of the adjusting transistor 21 becomes low, the operation speed of the CMOS inverter 19 becomes low, and the changing speed of the output signal S8 from the H level to the L level becomes slow. As a result, ring oscillator 1
The total of the delay times in 1 as a whole is adjusted to be a preset value.

Further, it is assumed that the capability of the transistor on the semiconductor device 10 is lower than the design value due to the process variation. Then, since the delay time of each CMOS inverter 12 to 20 of the ring oscillator 11 is long,
The L-level pulse width T1 of the output signal S9 becomes longer.

Therefore, the period in which the current I1 flows through the pMOS transistor 26 becomes longer, and as a result, the potential of the reference voltage N1 becomes higher. Therefore, the current driving capability of the adjusting transistor 21 is increased, the operating speed of the CMOS inverter 19 is increased, and the changing speed of the output signal S8 from the H level to the L level is increased. As a result, ring oscillator 1
The total of the delay times in 1 as a whole is adjusted to be a preset value.

As shown in FIG. 3B, the CMOS
When the input signal φ1 of the inverter 12 changes from the L level to the H level, the signal change is transmitted to each of the CMOS inverters 12 to 20 with a delay time corresponding to the operating speed of each of the CMOS inverters 12 to 20. In this case, C
The output signal S8 of the MOS inverter 19 changes from L level to H level.
Change to a level.

Since the output signal S4 changes from the L level to the H level later than the change of the output signal S1 from the H level to the L level, the output signal S9 of the NAND circuit 25 changes to the H level.
Maintained at the level. Therefore, the pMOS transistor 26 remains off, and the capacitor C1 is not charged.

On the other hand, the nMOS transistor is turned on based on the change of the output signal S2 from the L level to the H level,
The capacitor C1 is discharged, and the reference voltage N1 is the ground G.
Reset to ND level.

Therefore, the total delay time in the entire ring oscillator 11 when the input signal φ1 changes from the L level to the H level is the total delay time corresponding to the operating speed based on the process.

The present embodiment has the following effects. (1) In the semiconductor device 10 of the present embodiment, the detection circuit 22 that detects the operating speed of the CMOS inverters 12 to 20 as a basic circuit by a pulse, and the control circuit 23 that generates the reference voltage N1 proportional to the pulse width thereof. And an adjusting transistor 21 for controlling the current flowing through the CMOS inverter 19 based on the reference voltage N1 to adjust the operating speed of the CMOS inverter 19 to a preset value.
And provided. Therefore, if there is process variation, CM
Although the operating speeds of the OS inverters 12 to 20 themselves fluctuate, by adjusting the operating speed of the CMOS inverter 19 by the adjusting transistor 21, fluctuations in the operating speed of the entire ring oscillator 11 can be suppressed, and thus process variations are taken into consideration. It is possible to manufacture the highly accurate semiconductor device 10 that does not require a margin.

(2) The semiconductor device 10 of the present embodiment is
CM as a basic circuit constituting the ring oscillator 11
Of the OS inverters 12 to 20, a plurality of CMOS inverters 13 to 15 are included in the detection circuit 22 including a pulse generation circuit. Therefore, by generating a pulse that is the sum of the delay times of the CMOS inverters 12 to 20, the pulse width can be easily detected as the operating speed.

(3) The capacitor C1 is discharged by the nMOS transistor 24 when the operating speed of the CMOS inverter 19 is not adjusted. Therefore, when the operating speed of the CMOS inverter 19 is adjusted, a constant reference voltage N1 can be generated in the capacitor C1, and the operating speed of the CMOS inverter 19 can be adjusted stably.

The present invention can be embodied by arbitrarily changing it as follows. (1) The adjusting transistor is provided on the high potential power supply V _CC side of the CMOS inverter 19, and the current driving capability of the adjusting transistor is determined by the output signal S8 of the CMOS inverter 19.
The control may be performed when the L level changes from the L level to the H level. Also in this case, the same effect as the above-mentioned embodiment is obtained.

(2) The adjusting transistor 21 is a CMOS
CMOS inverters 13, 15 other than the inverter 19,
17 or CMOS inverter 1
It may be connected to a plurality of 3, 15, 17, and 19.

[0039]

As described above in detail, the present invention provides a highly accurate semiconductor device capable of suppressing fluctuations in operating speed due to process variations and not requiring a margin in consideration of process variations. You can

[Brief description of the drawings]

FIG. 1 is a diagram illustrating the principle of the present invention.

FIG. 2 is a circuit diagram showing a ring oscillator according to an embodiment.

FIG. 3 is a time chart showing the operation of the ring oscillator shown in FIG.

FIG. 4 is a circuit diagram showing a conventional ring oscillator.

[Explanation of symbols]

 1 basic circuit 2 adjusting transistor 3,22 detecting circuit 4,23 control circuit 24 nMOS transistor as reset circuit 26 pMOS transistor as switch C1 capacitor forming an integrating circuit IN input signal N1 reference voltage OUT output signal R1 integrating circuit Resistance

Claims (4)

[Claims] 1. A semiconductor device comprising a transistor and having a basic circuit which operates in response to an input signal and outputs a signal corresponding to the input signal, wherein a current flowing through the basic circuit is controlled. Adjustment transistor for adjusting the operating speed of the basic circuit by doing, a detection circuit for detecting the operating speed of the basic circuit, the operating speed of the basic circuit based on the detection result of the detection circuit A semiconductor device comprising: a control circuit for controlling the current driving capability of the adjusting transistor so that the value has a preset value. 2. The detection circuit is a pulse generation circuit that outputs a pulse based on a change in an input signal, and the control circuit generates a reference voltage having a value proportional to the pulse width of the pulse, and the generated reference voltage. The semiconductor device according to claim 1, wherein a voltage is output to the adjusting transistor. 3. The control circuit includes an integrating circuit including a resistor and a capacitor, and a switch for supplying power to the integrating circuit to charge the capacitor by turning on based on the pulse. 2. The semiconductor device according to item 2. 4. The semiconductor device according to claim 3, wherein the pulse generation circuit includes a reset circuit for discharging the capacitor based on a signal change opposite to a signal change for generating a pulse.