JPH09134145A - Electron source driving device, image forming device driving device, and methods therefor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To make a luminescence of each picture element uniform by correcting non-uniform distribution to an effective voltage impressed on each electron emitting element. SOLUTION: Voltage drop arithmetic circuit 201 calculates a voltage drop ΔV to correspond to horizontal component count m from a picture signal DO, and a shift register group 237a-237c and a latch circuit 242 supply the voltage drop to an A/D converter 202 in synchronization with a timing signal Q3. Following this, a voltage V0 (drive voltage for ΔV=0) is added in an analog adder 203 to obtain drive voltages V1-Vm for each row.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a driving device for an electron source,
The present invention relates to an image forming apparatus and methods thereof, for example, an apparatus and method for driving an electron source in which a plurality of cold cathode electron sources are arranged, an image forming apparatus using the electron source, and a method thereof.

[0002]

2. Description of the Related Art There are two types of electron-emitting devices, a hot cathode device and a cold cathode device. Among them, the cold cathode device includes, for example, a field emission device (hereinafter referred to as “FE type”), a metal / insulating layer / metal type emission device (hereinafter referred to as “MIM type”), a surface conduction electron emission device, and the like. There is.

As an example of the FE type, for example, WP Dyke &
WWDolan, "Field emission", Advance in Electron P
hysics, 8, 89 (1956) or CASpindt, "Phys
icalproperties of thin-film field emission cathode
s with molybdenium cones ", J.Appl.Phys., 47, 5248 (1
976) and so on.

As an example of the MIM type, for example, CAM
ead, "Operation of Tunnel-emission Devices", J.App
l.Phys., 32, 646 (1961), etc.

Further, as the surface conduction electron-emitting device,
For example, MIElinson, Radio Eng. Electron Phys., 10,
1290 (1965) and other examples described later.

The surface conduction electron-emitting device utilizes a phenomenon in which electron emission occurs when a current is passed through a thin film having a small area formed on a substrate in parallel with the film surface. As the surface conduction electron-emitting device, in addition to the SnO2 thin film by Elinson, etc., the Au thin film is used.
[G.Dittmer: "Thin Solid Films", 9, 317 (1972)], In2
O3 / SnO2 thin film [M. Hartwell and CGFonstad:
"IEEE Trans. ED Conf.", 519 (1975)] and carbon thin films [Haraki Araki et al .: Vacuum, Vol. 26, No. 1, 22 (198)
3)] etc. have been reported.

As a typical example of the device configuration of these surface conduction electron-emitting devices, FIG. 1 shows a plan view of the device according to the above-mentioned Hartwell. In the figure, 3001 is a substrate, 30
Reference numeral 04 is a conductive thin film made of metal oxide formed by sputtering. The conductive thin film 3004 is formed in an H-shaped plane shape as shown in the figure. An electron-emitting portion 3005 is formed by performing an energization process called energization forming described later on this conductive thin film 3004. The distance L in the figure is
0.5 to 1 mm, W is set to 0.1 mm. Note that, for convenience of illustration, the electron emitting portion 3005 is shown in a rectangular shape in the center of the conductive thin film 3004, but this is a schematic one and faithfully represents the actual position and shape of the electron emitting portion. It doesn't mean that.

Starting with devices such as Hartwell,
In the above-mentioned surface conduction electron-emitting device, it is general that the electron-emitting portion 3005 is formed by subjecting the conductive thin film 3004 to an energization process called energization forming before emitting electrons. That is, the energization forming means that a constant DC voltage is applied to both ends of the conductive thin film 3004, or a DC voltage that is boosted at a very slow rate of, for example, about 1 V / min is applied to conduct current, and the conductive thin film 3004 is locally applied. That is, the electron emission portion 3005 is formed in a state of being electrically high in resistance by being destroyed, deformed or altered. Note that a crack is generated in a part of the conductive thin film 3004 which is locally broken, deformed or altered. When an appropriate voltage is applied to the conductive thin film 3004 after this energization forming, electrons are emitted near the crack.

The above-mentioned surface conduction electron-emitting device has an advantage that a large number of devices can be formed over a large area because it has a simple structure and is easy to manufacture. Therefore, as disclosed in, for example, Japanese Patent Laid-Open No. 64-31332 by the present applicant, a method for arranging and driving a large number of elements has been studied.

Regarding the application of the surface conduction electron-emitting device, for example, an image forming apparatus such as an image display device and an image recording device, and a charged beam source have been studied. Particularly as an application to an image display device, for example, as disclosed in USP 5,066,883 by the present applicant and Japanese Patent Application Laid-Open No. 2-257551, a combination of a display conduction type emission element and a phosphor that emits light by irradiation of an electron beam is combined. The image display device used for the above is being studied. An image display device using a combination of a surface conduction electron-emitting device and a phosphor is expected to have better characteristics than other conventional image display devices. For example, it can be said that it is superior in that it does not require a backlight and has a wide viewing angle because it is a self-luminous type, as compared with a liquid crystal display device that has become widespread in recent years.

[0011]

DISCLOSURE OF THE INVENTION The inventors of the present invention have described various materials and manufacturing methods, including those described in the above-mentioned conventional examples.
A surface conduction electron-emitting device having a structure has been tried. further,
We have conducted research on a multi-electron beam source in which a large number of surface conduction electron-emitting devices are arranged, and an image display device to which this multi-electron beam source is applied.

The inventors have tried, for example, a multi-electron beam source by the electronic wiring method shown in FIG. That is, it is a multi-electron beam source in which a large number of surface conduction electron-emitting devices are two-dimensionally arranged and these devices are arranged in a matrix as shown in the figure.

In the figure, 4001 schematically shows a surface conduction electron-emitting device, 4002 is a row direction wiring, and 4003 is a column direction wiring. The row wiring 4002 and the column wiring 4003 actually have finite electric resistance, but they are shown as wiring resistances 4004 and 4005 in the drawing. Such a wiring method is called “simple matrix wiring”. Although a 6 × 6 matrix is shown for convenience of illustration, the scale of the matrix is not limited to this, for example, in the case of a multi-electron beam source for an image display device, desired image display is performed. The necessary elements are arranged and wired.

In the multi-electron beam source in which the surface conduction electron-emitting devices are wired in a simple matrix, appropriate electric signals are applied to the row-direction wiring 4002 and the column-direction wiring 4003 in order to output a desired electron beam. For example, in order to drive the surface conduction electron-emitting device of any one row in the matrix, the selection voltage Vs is applied to the row direction wiring 4002 of the selected row, and at the same time, the row direction wiring 4002 of the non-selected row is applied. Is applied with a non-selection voltage Vns. In synchronization with this, column direction wiring 400
A drive voltage Ve for outputting an electron beam is applied to 3.

According to this method, the wiring resistances 4004 and 40
Ignoring the voltage drop due to 05, the voltage Ve-Vs is applied to the surface conduction electron-emitting devices in the selected row, and the voltage Ve-Vns is applied to the surface conduction electron-emitting devices in the unselected row. . If Ve, Vs, and Vns are set to appropriate voltages, an electron beam with a desired intensity should be output only from the surface conduction electron-emitting devices of the selected row, and the column-direction wiring 40
If different drive voltages Ve are applied to the respective 03, electron beams of different intensities should be output from the elements of the selected row. Further, since the response speed of the surface conduction electron-emitting device is high, if the length of time for applying the driving voltage Ve is changed, the length of time for which the electron beam is output should be changed.

Therefore, the multi-electron beam source in which the surface conduction electron-emitting devices are wired in a simple matrix has various potential applications. For example, if an electric signal according to image information is appropriately applied, it can be used for an image display device. It can be suitably used as an electron source. However, the multi-electron beam source in which the surface-driven electron-emitting devices are wired in a simple matrix has the following problems.

In various image forming panels to which a surface conduction electron-emitting device is applied, including a flat panel CRT,
High-quality and high-definition image formation is desired. To achieve this, a method of using a large number of surface conduction electron-emitting devices wired in a simple matrix is conceivable, but in this case, the number of rows and columns reaches hundreds to thousands, and a very large number. In addition to device arrangement, it is desired that each surface conduction electron-emitting device emits a uniform amount of electrons.

However, m rows (hereinafter, "X
Wiring in the column direction (hereinafter sometimes referred to as “direction”) and wiring in n column directions (hereinafter sometimes referred to as “Y direction”) are connected to the pair of opposing device electrodes of the surface conduction electron-emitting device. Thus, when a simple matrix configuration is formed in which a large number of surface-conduction electron-emitting devices are arranged in a matrix, each device is subject to voltage drop caused by wiring resistance in the row and column directions. The problem arises that the voltage applied to each electrode is different. As a result, the effective voltage applied to each element has a non-uniform distribution, and correspondingly, the brightness of each pixel also has a non-uniform distribution.

In the following, this problem will be explained in more detail. FIG. 3 is a diagram showing an m × n simple matrix circuit of surface conduction electron-emitting devices arranged in a matrix and its wiring resistance, and FIG. 4 is a diagram showing voltages applied to each device electrode in the column direction. .

Here, voltage is applied to the m × n simple matrix circuit shown in FIG. 3 from one direction in both the row and column directions. In addition, the row wiring and the column wiring are assumed to have resistance components of rx and ry in each element. Since the surface conduction electron-emitting devices are arranged at equal intervals in the row direction and the column direction, unless the width and film thickness of the wiring are varied due to manufacturing, the row direction and the column direction are almost in each device unit. Have equal resistance. Further, all the surface conduction electron-emitting devices have substantially the same resistance value.

As is clear from the circuit configuration of FIG. 3, the element closer to the voltage application terminal is applied with a larger voltage, and the element farther from the voltage application terminal is applied with a smaller voltage. for that reason,
As shown in FIG. 4, since the drive applied voltage has a non-uniform distribution, the amount of electrons emitted from each surface conduction electron-emitting device also has a non-uniform distribution. This non-uniform distribution of the amount of emitted electrons becomes a problem when trying to obtain a high-quality image.

FIG. 5 is a diagram showing the voltage applied to each element on the same line when the luminance values have a distribution. That is, in FIG. 5, the signal A represents the element applied voltage when the luminance value of one line alternates with 255 → 0 → 255 → 0 at the point where the line is divided into four. . Also,
Contrary to the signal A, the signal B indicates the element applied voltage when the brightness value of one line alternates from 0 to 255 → 0 → 255 with the line dividing the line into four. There is. As is clear from Figure 5, for two different display patterns,
The voltage applied to the element where the same brightness should be displayed is slightly different. However, the two patterns have the same sum or average value of the brightness values except that the positions of the brightness values to be displayed are different. Therefore, in order to perform accurate correction, it is necessary to perform calculation for each display image.

The present invention is for solving the above-mentioned problem, and is capable of correcting the non-uniform distribution of the voltage supplied to the electron source, which is caused by the voltage drop in the wiring. An object of the present invention is to provide an image forming apparatus and methods thereof.

Another object of the present invention is to provide an image forming apparatus and an image forming method capable of forming a high-quality and high-definition image by correcting the non-uniform distribution of the voltage supplied to the electron source. The purpose of.

[0025]

The present invention has the following configuration as one means for achieving the above object.

In the electron source driving apparatus according to the present invention, at least a plurality of cold cathode electron sources are two-dimensionally arranged, and a multi electron source in which each electron source is connected in a matrix by row-direction wiring and column-direction wiring. Scanning means for scanning the row-direction wirings row by row, input means for inputting a predetermined voltage to an input terminal of a row scanned by the scanning means, and the row-direction wirings and the columns based on an input image signal. Calculating means for calculating the voltage drop due to the directional wiring for each column; modulating means for generating a modulated signal combining a plurality of pulses based on the input image signal in synchronization with the scanning of the scanning means; A driving means for supplying the driving voltage of the electron source, which is calculated by the calculating means and compensated for the voltage drop for each column, to the input end of the column direction wiring according to the modulation signal. .

In the image forming apparatus according to the present invention, at least a plurality of cold cathode electron sources are two-dimensionally arranged, and the electron sources are connected in a matrix by row-direction wirings and column-direction wirings. Scanning means for scanning the row-direction wiring one row at a time, input means for inputting a predetermined voltage to the input terminal of the row scanned by the scanning means, and the row-direction wiring and the column-direction wiring based on the input image signal. Calculating means for calculating the voltage drop due to each column, modulating means for generating a modulated signal combining a plurality of pulses based on the input image signal in synchronization with the scanning of the scanning means, and the modulated signal. In accordance with the above, the driving voltage of the electron source, which is calculated by the calculating means and compensated for the voltage drop for each column, is supplied to the input end of the column direction wiring, and is emitted from the cold cathode electron source. And having a light emitting means for emitting light by electrons.

In the electron source driving method according to the present invention, at least a plurality of cold cathode electron sources are two-dimensionally arranged, and each electron source is connected in a matrix by row wirings and column wirings. A driving method, comprising a scanning step of scanning the row-direction wiring line by line, an input step of inputting a predetermined voltage to an input terminal of a row scanned in the scanning step, and a row direction based on an input image signal. A modulation step of calculating a voltage drop due to the wiring and the column-direction wiring for each column, and a modulation for generating a modulation signal in which a plurality of pulses are combined based on the input image signal in synchronization with the scanning of the scanning step. Step, and the drive voltage of the electron source, which is compensated for the voltage drop for each column calculated in the calculation step in accordance with the modulation signal, is supplied to the input end of the column direction wiring. And having a feeding step.

In the image forming method according to the present invention, at least a plurality of cold cathode electron sources are two-dimensionally arranged, and the electron sources are connected in a matrix by row-direction wirings and column-direction wirings, An image forming method of an image forming apparatus, comprising: a light emitting unit that emits light by electrons emitted from a cold cathode electron source, comprising a scanning step of scanning the row-direction wiring line by line, and a row scanning in the scanning step. An input step of inputting a predetermined voltage to an input terminal, a calculation step of calculating a voltage drop due to the row-direction wiring and the column-direction wiring for each column based on the input image signal, and synchronization with scanning of the scanning means Then, a modulation step of generating a modulation signal in which a plurality of pulses are combined based on the input image signal, and a column calculated in the calculation step according to the modulation signal The driving voltage of the electron source to compensate for voltage drops and, and having a supply step of supplying to the input end of said column direction wiring.

[0030]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, an image forming apparatus according to an embodiment of the present invention will be described in detail with reference to the drawings.

First, the calculation of the voltage value for compensating for the voltage drop depending on the wiring resistance will be described.

The voltage applied to each element drops according to the amount of current flowing through the wiring and the element, which varies depending on the image to be displayed. That is, the voltage drop is uniquely determined from the resistance components of the row wirings and the column wirings, the current-voltage characteristics of the electron-emitting devices, and the displayed image. Therefore, the voltage value for compensating the voltage drop can be obtained from these parameters, and in order to flow the desired current to each element, the voltage value to be applied to each terminal is calculated according to the input image. Good. For example,
The voltage that compensates for the voltage drop is obtained by the following calculation.

A voltage E (j) is applied to the horizontal (row direction) wiring terminal j to drive one line, and the element (i, i,
Consider a case in which a device current I (i, j) that gives a desired electron emission amount corresponding to the magnitude of an image signal is to be supplied to j).

The element (i, j) has an IV characteristic I = ψi, j (V),
The horizontal wiring resistance is rx (i, j), and the vertical (column direction) wiring resistance is ry.
(i, j). The element characteristics when not selected is the linear resistance Ro (i, j)
When approximated by, the voltage Vi (j) to be applied to the vertical wiring terminal i is obtained by the following equation. When column i is on Vi (j) = {1 + Yoff (i, j)-Xoff (i, j)} ・ E (j) + {1 + Yof
f (i, j)} ・ {ψ'i, j (Ii (j))} + ΣBi, i '(j) ・ Ii' (j) where ψ'is the inverse function sequence i of ψ is off Vi (j) = 0 ... (1) In equation (1), Bi, i '(j) ≡η (i, j) δi, i' + ξ (k, j) where k = min (i ', i) and when i '<i Bi, i' (j) = ξ (i ', j) When i' = i Bi, i '(j) = η (i, j) + ξ (i , j) i '> i Bi, i' (j) = ξ (i, j)… (2) When column i'is on Ii '(j) ≡I (i', j) column i ' Is off Ii '(j) ≡ 0… (3) Xoff (i, j) ≡ Σ {ξ (k, j) / Ro (i', j)} where k = min (i ', j) Σ operation is the sum where column i ′ is off Yoff (i, j) ≡Σ {η (i, λ) / Ro (i, j ')} where λ = min (j', j) Σ operation Sum when row j'is off ξ (i, j) ≡Rx (i ', j) Σ operation is i' = 1 to i η (i, j) ≡ΣRy (i, j ') Σ operation is From i '= 1 to j, from j' = 1 to j (4)

Here, if the resistance values of the portions for extracting the horizontal wirings and the vertical wirings (hereinafter referred to as "extraction resistances") are Ra and Rb respectively, and the horizontal wiring and vertical wiring resistances of the respective elements are constant values rx and ry, respectively. It looks like this: ξ (i, j) ≡Ra + irx η (i, j) ≡Rb + jry… (5)

When the linear resistance Ro (i, j) is larger than the resistance when the element is selected, the terms Yoff (i, j) and Xoff (i, j) can be ignored, so that Vi (j ) Is as follows. Vi (j) = E (j) + ψ'i, j (Ii (j)) + ΣBi, i '(j) ・ Ii' (j) when column i is on Vi (j ) = 0… (6)

Further, focusing on the equation (7) when the vertical wiring terminal i is on (when current is flowing through the element),
The second term on the right-hand side is the voltage across the element that gives the current that is about to flow to the element, and the third term is the component that depends on the wiring resistance, but when trying to flow currents I1 to Im on each of the m elements, The voltages V1 to Vm to be supplied are obtained by the equation (7) obtained from the equation (6).
Can be expressed as Vi = ΔVi + Vo = irxΣIi '+ RaΣIi' + (Rb + jry) Ii + Vo However, the Σ operation of the first term on the right side is from i '= 1 to i The Σ operation of the second term on the right side is from i' = 1 Up to m… (7)

The first term on the right side of the equation (7) is obtained by multiplying the sum of lateral wiring resistances up to the i-th column by the sum of current values up to the i-th column.
The second term is the take-out resistance Ra of the horizontal wiring multiplied by the current value for one line, and the third term is the sum of the vertical wiring resistances up to the jth row including the take-out resistance Rb of the vertical wiring, It is obtained by multiplying the current value in the i-th column, and the constant Vo in the fourth term is the voltage to be supplied when the voltage drop ΔV is zero. In this equation, some terms can be omitted in the calculation depending on the magnitude relation among the element resistance of the horizontal wiring, the extraction resistance of the horizontal wiring, and the extraction resistance of the vertical wiring.

[0039]

First Embodiment An image forming apparatus according to the first embodiment of the present invention will be described below.

[Driving of Image Forming Panel] FIG. 6 is a block diagram for explaining a driving method of the image forming panel.

In the figure, the video intermediate frequency circuit 31 is
A video intermediate frequency signal is created from the input NTSC signal and supplied to the video detection circuit 32. The video detection circuit 32 extracts the video signal S from the video intermediate frequency signal and supplies it to the sync separation circuit 33 and the A / D conversion circuit 35. Sync separation circuit 3
3 separates the horizontal synchronizing signal and the vertical synchronizing signal from the video signal S and supplies them to the timing control circuit 34. Further, the sync separation circuit 33 outputs a LINE signal that counts a timing signal having a frequency obtained by multiplying the vertical frequency by the number of vertical pixels n, in synchronization with the vertical synchronization signal. Indicates this scan line number
The LINE signal is input to the arithmetic circuit 45 described later.

The timing control circuit 34 outputs timing signals Q0 and Q2 having a frequency obtained by multiplying the horizontal scanning frequency by the number m of pixels in the horizontal direction of the image forming section 41 from the horizontal synchronization signal, and the timing signal Q1 from the vertical synchronization signal to both synchronizations. A timing signal Q3 is generated from the signal. FIG. 7 is a timing chart showing an example of these timing signals.

For example, the 8-bit A / D conversion circuit 35 samples the video signal S at the cycle of the timing signal Q0 and outputs the 8-bit parallel digital signal D0. The parallel digital signal D0 is sequentially transferred to, for example, the 8-bit latch circuit 36 and the arithmetic circuit 45 in synchronization with the timing signal Q0.

The output of the latch circuit 36 is a shift register group.
It is connected to 37a and 37c. The shift register group 37a is m / 2
Timing signal Q0 is composed of bit shift registers arranged for the number of digital signal bits (for example, 8 bits).
The image data input from the latch circuit 36 is shifted in synchronism with. The 8 × m / 2 matrix-shaped shift register group 37b, which is arranged ahead of the shift register group 37a, has image data input from the shift register group 37a in a horizontal direction in the figure in synchronization with the timing signal Q0. Shift in the direction indicated by the arrow. Shift register group 37
Like the shift register group 37b, c is in the form of, for example, a matrix of 8 × m / 2, and the image data input from the latch circuit 36 is synchronized with the timing signal Q2 in the directions indicated by the horizontal arrows in the figure. shift. Note that m is the number of pixels in the horizontal direction of the image forming unit 41, and also the number of pixel columns and the number of column wirings.

FIG. 8 is a diagram showing how the digital signal D0 is stored in the shift register groups 37a to 37c. If the timing signals Q0 and Q2 have the waveforms shown in FIG. 7, the digital signal D0 is stored in the shift register group 37a in the first 1 / 2H (H is one horizontal scanning period).
Then, at the next 1 / 2H, the digital signal D0 stored in the shift register group 37a is transferred to the shift register group 37a.
At the same time, the 1 / 2H digital signal D0 that has been transferred to b and A / D converted during the 1 / 2H is stored in the shift register group 37c. When the image data for 1H is stored in the shift register groups 37b and 37c, the timing signal Q3 is supplied from the timing control circuit 34 to the shift register groups 37b and 37c.

As shown in FIG. 7, this timing signal Q3 is, for example, when the 1H period is divided into 2 ^ 8 (square of 2), its (2 ^ k) -1 (where k = 1, …, 7) th, ie 1,3,7,15,
A signal that goes high at the times corresponding to the 31,63th and 127th, and the image data stored in the shift register groups 37b and 37c by this timing signal Q3 is shifted in the direction of the downward arrow in the figure. And is supplied to the m-bit latch circuit 42.

Since the latch circuit 42 latches each bit of the image data in order from the lower bit in synchronization with the interval of the timing signal Q3, the signal output from the latch circuit 42 is a PWM signal corresponding to the image data. Become. Since this PWM signal is applied to the gate of the transistor 38 that drives each column wiring of the image forming unit 41, such as a surface conduction electron-emitting device electrically connected to each column wiring of the image forming unit 41. A voltage PWMed according to the image data is applied to the cold cathode element.

Further, the ring counter 39 inputs the timing signal Q1 and generates a signal for sequentially moving the row wirings of the nth row of the image forming section 41 every horizontal period. This signal is supplied to the scanning side drive circuit 40, converted into an appropriate voltage, and then input to each row wiring of the image forming unit 21 as a scanning signal D1 in synchronization with the modulation side (column wiring side). .

In this way, when the 1H period ends, the shift register group is loaded with image data (for example, 8 × m bits) corresponding to the next 1H period, and the image forming unit 41 is repeated by repeating the procedure described above. , A gradation image corresponding to the input image signal is formed.

On the other hand, the source (or drain) of each transistor 38 has a voltage for compensating the voltage drop generated from each video signal by the operation of the operation circuit 45 (hereinafter referred to as "voltage drop compensation signal"). Is applied). In this way, N kinds of drive waveforms having a peak value according to the level of each voltage drop compensation signal and having M = 2 ^ N with respect to the number of gradations M are supplied to the elements of the image forming unit 41. Supplied.

FIG. 9 is a diagram showing an example of the timing signal Q3. In this embodiment, in order to obtain N kinds of drive waveforms, a waveform having a pulse width T of 1 / (M / 2) of the scanning period 1H is obtained. Select the combination of. That is, the symbol A shown in FIG. 9 is the pulse width.
Waveform of T, code B is pulse width 2T, code C is pulse width 4
Waveform of T, code D is pulse width 8T, code E is pulse width 1
6T waveform, code F is a pulse width 32T waveform, code G is a pulse width 64T waveform, code H is a pulse width 128T waveform. By combining these eight types of drive waveforms, H / 256
With the period as a unit, it is possible to obtain a drive waveform for driving the element during an arbitrary period in one scanning period 1H.

[Arithmetic Circuit] The surface conduction electron-emitting device used in this embodiment has a resistance value of about 7 KΩ when selected and a resistance value of about 1 MΩ when not selected. The arithmetic circuit 45 may be any circuit as long as it realizes the arithmetic operation represented by the equation (7). FIG. 10 is a block diagram showing a configuration example of the arithmetic circuit 45.

In FIG. 10, the input image signal D0 is input to the voltage drop calculation circuit 201, and the voltage drop ΔV depending on the wiring resistance is calculated. The calculated voltage drop ΔV is stored in the shift register groups 237a to 237c and latched by the latch circuit 242 synchronized with the timing signal Q3. Since the shift register groups 237a to 237c and the latch circuit 242 perform the same operation at the same timing as the shift register groups 37a to 37c and the latch circuit 42 shown in FIG. 6, detailed description thereof will be omitted. Unlike the register groups 37a to 37c and the latch circuit 42 which store and transfer data bit by bit, the register groups 37a to 37c store and transfer data with a bit width of the voltage drop ΔV. The bit width of ΔV is
It is set so that a voltage drop compensation signal with a desired accuracy can be obtained according to the wiring resistance, the extraction resistance, and the magnitude of the element current If.

From the latch circuit 242, the timing signal Q3
In synchronization with, the voltage drop ΔV corresponding to each bit of the image data is output. The voltage drop ΔV1 to ΔVm output from the latch circuit 242 is converted into an analog voltage by the D / A converter 202, and then the analog adder 203 converts the voltage Vo (voltage drop ΔVm).
Is to be supplied when V is zero), and is supplied to the corresponding transistor 38 as V1 to Vm which are the voltage drop compensation signals corresponding to the equation (7).

FIG. 11 is a block diagram showing a detailed configuration example of the voltage drop calculation circuit 201, and shows only the circuit configuration corresponding to 1 bit of the image signal D0.

Each bit of the input image signal D0 is input to the up counter 301 which is cleared by the timing signal Q1 and the element current Ii for one line is counted. The output (ΣIi ′) of the up counter 301 is input to the multiplier 302, is multiplied by the value of the take-out resistance Ra of the horizontal wiring stored in the register 302a, and then is latched in synchronization with the timing signal Q1.
Latched to 303. In other words, the latch 303 is
The voltage drop due to (corresponding to the second term on the right side of equation (7)) will be latched.

On the other hand, the down counter 304 cleared by the timing signal Q1 counts down from the initial value m in synchronization with the timing signal Q0 and outputs the pixel column value i corresponding to the input image signal D0. The pixel column value i is input to the multiplier 305 together with the output of the up / down counter 301, and is multiplied by the value of the horizontal wiring resistance rx stored in the register 305a. That is, the output of the multiplier 305 represents a voltage drop amount (corresponding to the first term on the right side of Expression (7)) due to the wiring resistance rx.

Further, the LINE signal from the sync separation circuit 33 is multiplied by the value of the wiring resistance ry in the vertical direction stored in the register 306a by the multiplier 306, and the vertical wiring of the vertical wiring stored in the register 307a is added by the adder 307. After being added to the value of the take-out resistance Rb, it is ANDed with the bit of the input image signal D0 by the AND gate 308. That is, the output of the AND gate 308 is the output resistance Rb.
And the voltage drop due to the wiring resistance ry (corresponding to the third term on the right side of Expression (7)).

Each voltage drop thus obtained is
After being added by the adder 309, it is multiplied by the value of the device current If stored in the register 310a by the multiplier 310, latched by the latch 311 synchronized with the timing signal Q0, and output from the voltage drop calculation circuit 201. The element current If is multiplied by the multiplier 310 because Ii is processed by "1" (on) or "0" (off) in the calculation up to the adder 309. Gives a specific current value.

Although FIG. 11 shows that each register is attached to each arithmetic unit, since the value stored in the register is common to each bit of the image signal D0, each arithmetic operation corresponding to each bit is performed. Each register can be shared by the container. The value stored in each register is set or adjusted according to the characteristics of the image forming unit 41 or the like when the device is shipped.

Needless to say, the calculation in the voltage drop calculation circuit 201 is also achieved by the CPU executing the program code of the software that realizes the function based on each timing signal.

As described above, according to this embodiment, the voltage drop compensation signals corresponding to the number m of elements in the horizontal direction are calculated from the image signal D0, and the corresponding transistor 38 is synchronized with the timing signal Q3. By supplying the same, the effective voltage applied to each electron-emitting device can be made uniform, and the emission brightness of the phosphor can also be made uniform. Therefore, a high-quality and high-definition image can be formed.

A method of correcting the image signal D0 itself to compensate for the influence of the voltage drop ΔV is also conceivable. However, when the image signal D0 is, for example, 8 bits, only 1/256 unit correction can be performed. On the other hand, according to the present embodiment, the voltage drop Δ
Since V itself can be represented by 8 bits, for example,
When ΔV is 1V at the maximum, correction in 1 / 256V (about 4mV) unit is possible, and more precise compensation can be applied.

Further, according to this embodiment, when calculating each voltage drop component (first term to third term on the right side of the equation (7)) and when obtaining the sum of the obtained voltage drop components, Since the current is represented by "0" or "1" instead of the specific current value, the current value can be integrated with a counter and the multiplication can be obtained with a logic gate. It is possible to realize high-speed calculation with a simple configuration.

Further, in the present embodiment, at the time of gradation display of an image, the number of gradations M (for example, 256) whose drive waveform has a peak value corresponding to the intensity of each correction voltage signal
So that M = 2 ^ N, for example, 1 / eight of the eight scanning times 1H
A drive waveform obtained by combining waveforms having a pulse width T of (M / 2) is used. Driving the image forming panel using such a driving waveform has the following advantages.

If the calculation according to the present invention is used in the PWM gradation display system in which the pulse length of the drive voltage is controlled and gradation display is performed, the drive signal is, for example, 256 gradation display, High resolution TV such as HDTV when one line is selected
Then, the waveform changes every 1/256 of about 30 μs.
Therefore, calculation must be performed for each change.
To finish the calculation in a short time of 56 μs,
It becomes necessary to use an expensive high-speed arithmetic element. However, if the method used in the present embodiment is used, for example, all drive waveforms are generated by combining eight types of waveforms, so that it is sufficient to perform, for example, eight times within 30 μs, and the operation speed is 1 Since the calculation can be completed even if the element of / 32 is used, the cost of the calculation circuit for realizing this calculation can be suppressed.

[Structure and Manufacturing Method of Display Panel] FIG. 12 is a perspective view of the display panel used in the present embodiment, in which a part of the panel is cut away to show its internal structure.

In the figure, 1005 is a rear plate, 1006 is a side wall,
Reference numeral 1007 denotes a face plate, which forms an airtight container for maintaining the inside of the display panel in a substantially vacuum state. When assembling the airtight container, it is necessary to seal the joints of the respective members so as to maintain sufficient strength and airtightness. For example, frit glass is applied to the joint portion and sealed by firing at 400 ° C. to 500 ° C. for 10 minutes or more in the air or a nitrogen atmosphere. The method of evacuating the airtight container to a substantially vacuum will be described later.

The substrate 1001 is fixed to the rear plate 1005, and N × M surface conduction electron-emitting devices 1002 are formed on the substrate 1001. Both N and M are
It is a positive integer of 2 or more and is appropriately set according to the target number of display pixels. For example, in a device intended to display a high-definition television, N = 3,000, M = 1,0
Although it is desirable to set a number of 00 or more, in this embodiment, for example, N = 3,072 and M = 1,024. The N × M surface-conduction electron-emitting devices are arranged in a simple matrix by M row-direction wirings 1003 and N column-direction wirings 1004. Here, it goes without saying that the row direction and the column direction are directions substantially orthogonal to each other.

The portion constituted by the respective parts 1001 to 1004 is called a multi-electron beam source, and its manufacturing method and structure will be described in detail later. Further, in this embodiment, the substrate 1001 of the multi-electron beam source is fixed to the rear plate 1005 of the airtight container, but if the substrate 1001 has sufficient strength, the substrate 1001 itself is the rear plate of the airtight container. You may use as.

A fluorescent film is formed on the lower surface of the face plate 1007.
1008 is formed. Since the present embodiment is an apparatus for forming a color image, the phosphor film 1008 is separately coated with phosphors of the three primary colors of red, green and blue used in the field of CRT. Phosphor 92 of each color
For example, as shown in FIG. 13A, they are painted in stripes, and black conductors 91 are provided between the phosphor stripes. The purpose of providing the black conductor 91 is to prevent the display color from being displaced even if the irradiation position of the electron beam is slightly displaced, and to prevent the reflection of external light to prevent the deterioration of the display contrast. , Fluorescent film 1008 by electron beam
To prevent the electrification of. The black conductor 91 uses graphite as a main component, but other materials may be used as long as they are suitable for the above purpose.

How to separately paint the phosphors 92 of the three primary colors is shown in FIG. 13A.
The arrangement is not limited to the stripe-shaped arrangement shown in, but may be, for example, a delta arrangement as shown in FIG. 13B or another arrangement. When a monochrome display panel is created, a monochromatic phosphor material may be used for the phosphor film 1008, and the black conductive material 91 is not always necessary. As a coating method of the phosphor 92, a precipitation method or a printing method is used in the case of monochrome, but a slurry method is used in the case of color. However, if a printing method is used in the case of color, of course, an equivalent coating film can be obtained.

A metal back 1009 known in the field of CRT is provided on the surface of the fluorescent film 1008 on the rear plate 1005 side. The purpose of providing the metal back 1009 is to specularly reflect part of the light emitted by the fluorescent film 1008 to improve the light utilization rate, protect the fluorescent film 1008 from the collision of negative ions, and apply an electron beam acceleration voltage. For example, to act as a conductive electrode for electrons that have excited the fluorescent film 1008. Metal back 1009 is a fluorescent film 10
After forming 08 on the face plate 1007, the fluorescent film 1008
Surface smoothing process (usually called filming)
Then, Al (aluminum) is formed thereon by, for example, a method of vacuum vapor deposition. When a low voltage phosphor material is used for the fluorescent film 1008, the metal back 1009 is not used. Although not used in this embodiment, a face plate is used for the purpose of applying an acceleration voltage and improving the conductivity of the fluorescent film 1008.
A transparent electrode made of, for example, ITO may be provided between the 1007 and the fluorescent film 1008.

Dx1 to Dxn, Dy1 to Dym and Hv are terminals for electrical connection having an airtight structure provided for electrically connecting the display panel and an electric circuit (not shown). Dx1 to Dxn are multi-electron beam source row-directional wiring 1003, Dy1 to Dym are multi-electron beam source column-directional wiring 1004, and Hv is a face plate
It is electrically connected to the metal back 1009 of 1007.

To evacuate the inside of the airtight container to a vacuum, after assembling the airtight container, an exhaust pipe (not shown) and a vacuum pump are connected to the airtight container, and the inside of the container is evacuated to a vacuum of about 10 ^ (-7) Torr. Exhaust up to a degree (a ^ b represents a raised to the bth power). Then, the exhaust pipe is sealed, but in order to maintain the degree of vacuum in the container, a getter film (not shown) is formed at a predetermined position in the airtight container immediately before or after the sealing. The getter film is, for example, a film obtained by heating a getter material containing Ba as a main component with a heater or high-frequency heating, and the inside of the container is 10 ^ (-5) to 10 ^ (-7) due to the adsorption action of the getter film. Maintained at Torr vacuum. Assembling the airtight container, that is, the face plate 1007,
When sealing the joint between the side wall 1006 and the rear plate 1005,
Since the phosphors 92 of the respective colors must correspond to the electron-emitting devices, it is necessary to perform sufficient alignment.

[Preferable Device Structure and Manufacturing Method of Surface Conduction Electron-Emitting Device] The basic structure and manufacturing method of the display panel of this embodiment have been described above. Next, the multi-electron device used in the display panel of this embodiment is described. A method of manufacturing the beam source will be described.

The electron beam source used in the image forming apparatus of the present embodiment is not limited in the material, shape or manufacturing method of the surface conduction electron-emitting device as long as it is an electron source in which surface conduction electron-emitting devices are arranged in a simple matrix. . However, the inventors have found that among the surface conduction electron-emitting devices, the one in which the electron-emitting portion or its peripheral portion is formed of a fine particle film has excellent electron-emitting characteristics and can be easily manufactured. . Therefore, it can be said that the surface conduction electron-emitting device in which the electron-emitting portion or its peripheral portion is formed of a fine particle film is most suitable for use in a multi-electron beam source of an image forming apparatus having high brightness and a large screen. Therefore, the basic structure, manufacturing method, and characteristics of a preferable surface conduction electron-emitting device will be described first, and then the structure of a multi-electron beam source in which a large number of devices are wired in a simple matrix will be described.

There are two types of typical structures of the surface conduction electron-emitting device in which the electron-emitting portion or its peripheral portion is formed of a fine particle film, that is, a planar type and a vertical type, and these will be described in order.

[Flat Surface-Conduction Electron-Emitting Device] First, the device structure and manufacturing method of the flat surface-conduction electron-emitting device will be described. FIG. 14A is a plan view illustrating the configuration of a flat surface conduction electron-emitting device, and FIG. 14B is a sectional view thereof.

In the figure, 1101 is a substrate, 1102 and 1103 are element electrodes, 1104 is a conductive thin film, 1105 is an electron emission portion formed by energization forming treatment, and 1113 is a thin film formed by energization activation treatment.

As the substrate 1101, for example, various glass substrates such as quartz glass and soda lime glass, various ceramic substrates such as alumina, or an insulating layer made of, for example, SiO 2 is laminated on the above various substrates. A substrate or the like is used.

The device electrodes 1102 and 1103 provided on the substrate 1101 so as to face each other in parallel to the substrate surface are made of a conductive material. For example, Ni, Cr, Au, Mo, W, Pt,
Materials such as Ti, Cu, Pd, Ag, and other metals, alloys of these metals, metal oxides such as In2O3-SnO2, and semiconductors such as polysilicon are appropriately selected and used. The device electrodes 1102 and 1103 can be easily formed by combining a film forming technique such as vacuum deposition and a patterning technique such as photolithography / etching, but can also be formed by another method such as a printing technique. It doesn't matter. The shapes of the device electrodes 1102 and 1103 are appropriately designed according to the application purpose of the electron-emitting device. The electrode interval L is usually designed by selecting an appropriate value from the range of several hundred Å to several hundred μm, but the range of several μm to several tens μm is preferable for application to the image forming apparatus. In addition, the thickness d of the device electrodes 1102 and 1103 is usually selected from an appropriate value within the range of several hundred Å to several μm.

A fine particle film is used for the conductive thin film 1104. The fine particle film described here refers to a film (including an island-shaped aggregate) containing a large number of fine particles as a constituent element. A microscopic examination of a fine particle film usually reveals a structure in which individual fine particles are spaced apart, a structure in which fine particles are adjacent to each other, or
A structure in which the fine particles overlap each other is observed. The particle size of the fine particles used in the fine particle film is in the range of several Å to several thousand Å, but the range of 10 Å to 200 Å is preferable. Further, the thickness of the fine particle film is appropriately set in consideration of various conditions described below. That is,
Conditions necessary for good electrical connection to the device electrode 1102 or 1103, conditions required for conducting the energization forming described below satisfactorily, and necessary for adjusting the electric resistance of the fine particle film itself to an appropriate value described below. Conditions. Specifically, it is set in the range of several Å to several thousand Å, but the preferred one is
It ranges from 10Å to 500Å. The material used to form the fine particle film is, for example, Pd, Pt, Ru, Ag, Au, Ti, In,
Cu, Cr, Fe, Zn, Sn, Ta, W, Pb and other metals, PdO, SnO2, In2O3, PbO, Sb2O3 and other oxides, HfB2, ZrB2, LaB6, CeB6YB4, GdB4, etc. The first carbide, Ti

N, ZrN, HfN and other nitrides, S
There are semiconductors such as i and Ge, carbon, and the like, and they are appropriately selected from these.

As described above, the conductive thin film 1104 is formed of a fine particle film, and its sheet resistance value is 10 ^ 3 to 10 ^ 7Ω.
Set to be included in the range of / cm ^ 2. Since it is desirable that the conductive thin film 1104 and the device electrodes 1102 and 1103 are electrically connected well, the conductive thin film 1104 and the device electrodes 1102 and 1103 have a structure in which some of them overlap each other. Note that FIG. 14B shows an example in which the substrate 1101, the device electrodes 1102 and 1103, and the conductive thin film 1104 are stacked in this order from the bottom, but in some cases, the substrate 110 from the bottom may be stacked.
1. The conductive thin film 1104 and the device electrodes 1102 and 1103 may be laminated in this order.

The electron emitting portion 1105 is a crack-like portion formed in a part of the conductive thin film 1104, and has an electrically higher resistance than the surrounding conductive thin film 1104. The crack is formed by subjecting the conductive thin film 1104 to an energization forming process described later. Fine particles having a particle size of several to several hundreds of mm may be arranged in the crack. Note that it is difficult to accurately and accurately illustrate the actual position and shape of the electron emitting portion 1105, and they are schematically shown in FIGS. 14A and 14B.

The thin film 1113 is a thin film made of carbon or a carbon compound, and covers the electron emitting portion 1105 and its vicinity. The thin film 1113 is formed by performing an energization activation process described later after the energization forming process. Thin film 1113
Is single crystal graphite, polycrystalline graphite, amorphous carbon, or a mixture thereof, and the film thickness is 500.
It is less than Å, more preferably less than 300Å. Note that it is difficult to precisely and accurately illustrate the actual position and shape of the thin film 1113, and it is schematically shown in FIGS. 14A and 14B. 14A and 14B show a state in which a part of the thin film 1113 is removed.

The basic structure of the preferred device has been described above. In the embodiment, soda lime glass is used for the substrate 1101, Ni thin films are used for the device electrodes 1102 and 1103, and the thickness d of the device electrodes 1102 and 1103 is about 1000Å. The electrode spacing L is about 2 μm, Pd or PdO is used as the main material of the fine particle film, the thickness of the fine particle film is about 100 Å, and the width W is about 100 μm.

Next, a method of manufacturing a suitable flat surface conduction electron-emitting device will be described. 15A to 15E are cross-sectional views for explaining the manufacturing process of the surface conduction electron-emitting device.

Step 1: Device electrodes 1102 and 1103 on the substrate 1101
(Fig. 15A). Specifically, the substrate 1101 is a detergent,
The electrode material is deposited by thoroughly washing in advance with pure water and an organic solvent. For this deposition, a vacuum film forming technique such as a vapor deposition method or a sputtering method is used. Then, the deposited electrode material is patterned by using a photolithography / etching technique to form a pair of device electrodes 1102 and 1103.

Step 2: Form the conductive thin film 1104 (FIG. 15)
B). Specifically, the substrate 1 on which the device electrodes 1102 and 1103 are formed
101 is coated with an organic metal solution, dried, and heated and baked to form a fine particle film, which is then patterned into a predetermined shape by photolithography and etching to form a conductive thin film.
Form 1104. Here, the organometallic solvent is a solution of an organometallic compound whose main element is the fine particle material used for the conductive thin film, and Pd was used as the main element in this example. Although the dipping method is used as the coating method, other methods such as a spinner method or a spray method may be used. Further, as a method for forming a conductive thin film composed of a fine particle film, other than the method of applying the organometallic solution used in this example, for example, a vacuum vapor deposition method, a sputtering method, or a chemical vapor deposition method ( CVD) or the like can be used.

Step 3: Appropriate voltage is applied from the forming power supply 1110 between the device electrodes 1102 and 1103, and energization forming processing is performed to form the electron emitting portion 1105 (see FIG.
15C). Here, the energization forming process is a process of energizing the conductive thin film 1104 made of a fine particle film to appropriately destroy, deform, or alter a part of the conductive thin film 1104, and change it to a structure suitable for electron emission. That is. Appropriate cracks are formed in the thin film in the portion of the conductive thin film 1104 formed of a fine particle film that has been changed to a structure suitable for emitting electrons, that is, in the electron emitting portion 1105. It should be noted that, compared with before forming the electron emitting portion 1105, after forming the element electrode
The electrical resistance between 1102 and 1103 is greatly increased.

FIG. 16 is a diagram for explaining in detail the energization method in the energization forming process.
An example of an appropriate voltage waveform applied from 1110 is shown. When forming the conductive thin film 1104 made of a fine particle film, it is preferable to apply a pulsed voltage waveform. In the case of the present embodiment, as shown in FIG. 16, a triangular pulse having a pulse width T1 is repeated at an interval T2. To apply continuously. At that time, the peak value Vpf of the triangular wave pulse is sequentially boosted.

In this embodiment, for example, 10 ^ (-
5) In a vacuum atmosphere of about Torr, for example, pulse width T1 is about 1 m
s, the repeating interval T2 was set to about 10 ms, and the peak value Vpf was increased by about 0.1 V for each pulse. A monitor pulse Pm with a peak value Vpm of about 0.1 V is inserted at a rate of once every five pulses of the triangular wave so that the forming process is not adversely affected, and the current flowing at that time is changed to the current. The formation state of the electron emission portion 1105 is monitored by measuring with the total 1111. The electric resistance between the device electrodes 1102 and 1103 is 1M.
When the value becomes Ω or more, that is, when the current measured by the ammeter 1111 when the monitor pulse Pm is applied becomes 0.1 μA or less, the energization for the forming process is terminated. This method is preferable for the surface-conduction type electron-emitting device of the present embodiment, and when the design of the surface-conduction type electron-emitting device is changed, such as the material and film thickness of the fine particle film, or the device electrode spacing L, It is desirable to appropriately change the energization conditions accordingly.

Step 4: Appropriate voltage is applied from the activation power supply 1112 between the device electrodes 1102 and 1103 to carry out energization activation treatment to improve electron emission characteristics (FIG. 15D). here,
The energization activation process is a process of energizing the electron emitting portion 1105 formed by the energization forming process under appropriate conditions to deposit carbon or a carbon compound in the vicinity thereof. FIG. 15D schematically shows a deposit made of carbon or a carbon compound as the member 1113. Note that the emission current at the same applied voltage after the treatment can be increased to 100 times or more in a typical case as compared with before the energization activation treatment.

More specifically, 10 ^ (-4) to 10 ^ (-5) Torr
By periodically applying a voltage pulse in a vacuum atmosphere in the range of, carbon or a carbon compound originating from an organic compound existing in the vacuum atmosphere is deposited. Sediment
1113 is any one of single crystal graphite, polycrystalline graphite, and amorphous carbon, or a mixture thereof, and its film thickness is 500 Å or less, more preferably 300 Å or less. Next, the energization method will be described in more detail.

FIG. 17A is a diagram showing an example of an appropriate voltage waveform applied during the energization activation process. In the present embodiment, a rectangular wave of a constant voltage is periodically applied to perform energization activation processing. Specifically, the rectangular wave voltage Vac is about 14 V, the pulse width T3 is about 1 ms, and the pulse interval T4 is To about 10 ms. This energization condition is a preferable condition for the surface conduction electron-emitting device of the present embodiment, and when the design of the surface conduction electron emission device is changed, it is desirable to appropriately change the energization condition accordingly.

Reference numeral 1114 shown in FIG. 15D is an anode electrode for capturing the emission current Ie emitted from the surface conduction electron-emitting device, and is connected to the DC high voltage power supply 1115 and the ammeter 1116. When the substrate 1101 is incorporated into the display panel and the energization activation process is performed, the fluorescent surface of the display panel is used as the anode electrode 1114.

While applying the voltage from the activation power source 1112,
The ammeter 1116 measures the emission current Ie, monitors the progress of the energization activation process, and controls the operation of the activation power supply 1112. FIG. 17B is a diagram showing an example of the emission current Ie measured by the ammeter 1116.When the pulse voltage is started to be applied from the activation power supply 1112, the emission current Ie increases with the lapse of time, but eventually becomes saturated and almost increases. Will not do. In this way, when the emission current Ie is almost saturated, the voltage application from the activation power supply 1112 is stopped, and the energization activation process is terminated.

As described above, a flat surface conduction electron-emitting device, an example of which is shown in FIG. 15E, is manufactured.

[Vertical type surface conduction electron-emitting device] Next, another typical configuration of the surface conduction type electron-emitting device in which the electron emitting portion or its periphery is formed of a fine particle film, that is, vertical type surface conduction The configuration of the electron emission device will be described.

FIG. 18 is a schematic cross-sectional view for explaining the basic structure of a vertical surface conduction electron-emitting device. 1201 is a substrate, 1202 and 1203 are device electrodes, 1206 is a step forming member, 1204
Is a conductive thin film using a fine particle film, 1205 is an electron emission portion formed by an energization forming process, and 1213 is a thin film formed by an energization activation process.

The difference between the planar type and the vertical type described above is that one of the element electrodes (1202) is provided on the step forming member 1206, and the conductive thin film 1204 covers the side surface of the step forming member 1206. There is a point. Therefore, the element electrode interval L in the flat type shown in FIGS. 14A and 14B is set as the step height Ls of the step forming member 1206 in the vertical type. For the substrate 1201, the device electrodes 1202 and 1203, and the conductive thin film 1204 using a fine particle film, the materials listed in the description of the planar type can be similarly used. Also, the step forming member 12
For 06, an electrically insulating material such as SiO2 is used.

Next, a method of manufacturing a vertical type surface conduction electron-emitting device will be described. 19A to 19F are cross-sectional views illustrating a manufacturing process of a vertical type surface conduction electron-emitting device.

Step 1: A device electrode 1203 is formed on the substrate 1201 (FIG. 19A).

Step 2: A step forming member (hereinafter sometimes referred to as “insulating layer”) 1206 is laminated (FIG. 19B). Insulation layer 120
For example, SiO 2 may be formed by stacking SiO 2 by a sputtering method, but other film forming methods such as a vacuum vapor deposition method and a printing method may be used.

Step 3: A device electrode 1202 is formed on the insulating layer 1206 (FIG. 19C).

Step 4: Part of the insulating layer 1206 is removed by using, for example, an etching method to expose the device electrode 1203 (see FIG.
19D).

Step 5: Conductive thin film 1204 using fine particle film
(Fig. 19E). As in the case of the flat type, a film forming technique such as a coating method is used.

Step 6: The same energization forming process as in the case of the flat type is performed to form the electron emitting portion 1205 (see FIG.
19F)

Step 7: The same energization activation process as in the case of the planar type is performed to deposit carbon or a carbon compound in the vicinity of the electron emission portion 1205 (FIG. 19F).

As described above, a vertical surface conduction electron-emitting device, an example of which is shown in FIG. 19F, is manufactured.

[Characteristics of surface conduction electron-emitting device] Next,
The characteristics of the elements used in the device will be described. FIG. 20 is a diagram showing typical examples of Ie (emission current) vs. Vf (device voltage) characteristics and If (device current) vs. Vf (device voltage) characteristics of an element used in an image forming apparatus. Note that the emission current Ie is significantly smaller than the device current If and is difficult to illustrate on the same scale, and these characteristics change by changing design parameters such as the size and shape of the device. Therefore, the two curves showing these characteristics are shown in arbitrary units. The device used in the device has the following three characteristics regarding the emission current Ie.

First, when a voltage larger than a certain voltage Vth (which is called "threshold voltage") is applied to the element, the emission current Ie rapidly increases, but at a voltage lower than the threshold voltage Vth, the emission current Ie increases. Ie is rarely detected. That is, it is a non-linear element having a clear threshold voltage Vth with respect to the emission current Ie.

Secondly, the emission current Ie is the voltage applied to the device.
Since it changes depending on Vf, the magnitude of the emission current Ie can be controlled by the voltage Vf.

Thirdly, with respect to the voltage Vf applied to the element,
Since the response speed of the current Ie emitted from the device is fast, the voltage
The amount of charge of electrons emitted from the device can be controlled by the length of time that Vf is applied.

Due to the above-mentioned characteristics, the surface conduction electron-emitting device can be preferably used in the image forming apparatus. For example, in a device provided with a large number of elements corresponding to the pixels of the screen, by utilizing the first characteristic, it is possible to sequentially scan the screen to form an image. That is,
Depending on the desired emission brightness, the threshold voltage Vt
A voltage of h or higher is appropriately applied, and a voltage lower than the threshold voltage Vth is applied to the non-selected (non-driven) element. In this way, by sequentially switching the elements to be driven, the screen can be sequentially scanned to form an image. Further, since the emission brightness can be controlled by utilizing the second characteristic or the third characteristic, gradation display can be performed.

[Structure of Multi-Electron Beam Source] Next, the structure of the multi-electron beam source in which the above-mentioned surface conduction electron-emitting devices are arranged on the substrate and wired in a simple matrix will be described. 21A is a partial plan view of the multi-electron beam source used for the display panel shown in FIG. 12, and FIG. 21B is AA ′ of FIG. 21A.
It is arrow sectional drawing. On the substrate, surface-conduction type electron-emitting devices similar to those shown in FIGS. 14A and 14B are arranged, and these devices are divided into two groups as shown in FIG. 12, and the groups are arranged in the row direction. Wirings 1003 and column-direction wirings 1004 are connected in a simple matrix. An insulating layer (not shown) is formed at the intersection of the row-directional wiring 1003 and the column-directional wiring 1004 to maintain electrical insulation between the wirings.

The multi-electron beam source having such a structure has a row-direction wiring 1003, a column-direction wiring 1004, and
After forming the interelectrode insulating layer (not shown), the device electrodes 1102 and 1103 of the surface conduction electron-emitting device, and the conductive thin film 1104,
It is manufactured by applying a voltage to each element through the row-direction wiring 1003 and the column-direction wiring 1004 to perform the energization forming process and the energization activation process. [Image forming apparatus]

A multi-function display device configured to display image information provided from various image information sources including, for example, television broadcasting using the above-mentioned display panel will be described below. FIG. 22 is a block diagram showing an example of this multi-function display device.

In the figure, 2100 is a display panel, 2101 is a display panel drive circuit, 2102 is a display controller, 2103 is a multiplexer, 2104 is a decoder, 2105 is an input / output interface circuit, and 2106 is a CP.
U unit, 2107 is an image generation circuit, 2108 to 2110 are image memory interface circuits, 2111 is an image input interface circuit, 2112 and 2113 are TV signal receiving circuits, and 2114 is an input unit.

The CPU unit 2106 includes a CPU, ROM in which programs are stored in advance, work RAM, I / O, etc.
Pointing devices such as a touch panel, a keyboard, and a mouse are connected to 4 as necessary.
Further, when receiving a signal including both video information and sound information, such as a television signal, the present apparatus naturally reproduces sound at the same time as displaying a video. Circuits related to reception, separation, reproduction, processing, storage of sound information that is not directly related,
A description of a speaker that reproduces sound will be omitted. Hereinafter, the function of each unit will be described along the flow of the image signal.

The TV signal receiving circuit 2113 is a circuit for receiving a TV image signal transmitted using a wireless transmission system such as radio waves or spatial optical communication, and outputs the received TV signal to the decoder 2104. . The system of the TV signal to be received is not particularly limited, and various systems such as NTSC, PAL and SECAM may be used. Further, a TV signal having a larger number of scanning lines than these methods, for example, a so-called high-definition TV such as a MUSE method, has advantages of the display panel 2100 of this embodiment suitable for a large area and a large number of pixels. It is a suitable signal source for making the best use of.

The TV signal receiving circuit 2112 is a circuit for receiving a TV image signal transmitted using a wired transmission system such as a coaxial cable or an optical fiber, and outputs the received TV signal to the decoder 2104. . The TV signal receiving circuit 21
Similar to 13, the TV signal system to be received is not particularly limited.

The image input interface circuit 2111 is a circuit for inputting an image signal supplied from an image input device such as a TV camera or an image scanner, and outputs the input image signal to the decoder 2104.

The image memory interface circuit 2110 is a circuit for inputting an image signal reproduced by a video tape recorder (hereinafter abbreviated as "VTR"). The image memory interface circuit 2109 is a circuit for inputting an image signal recorded on a video disc. The image memory interface circuit 2108, like a so-called still image disk,
It is a circuit for inputting an image signal from a medium in which still image data is recorded. The image memory interface circuits 2108 to 2110 output the input image signal to the decoder 2104.

The input / output interface circuit 2105 is a circuit for connecting the present apparatus to an external output device such as a computer or printer directly or via a computer network, and inputs image data or character / graphic information. Not only output, but in some cases CPU2 of this device
It is also possible to input and output control signals and numerical data between the 106 and the outside.

The image generation circuit 2107 is used for display based on image data or character / graphic information input from the outside via the input / output interface circuit 2105 or image data or character / graphic information input from the CPU 2106. This is a circuit for generating image data. Inside this circuit, for example, a rewritable memory for storing image data and character / graphic information, a read-only memory that stores image information corresponding to a character code, and character / graphic information in an image. A circuit required for image generation, including a processor for performing image processing such as expansion, is incorporated. The display image data generated by this circuit is output to the decoder 2104, but in some cases, it can be output to an external computer network or printer via the input / output interface circuit 2105.

The CPU 2106 mainly performs operations related to the operation control of this apparatus and the generation, selection and editing of the display image.
For example, a control signal is output to the multiplexer 2103, and image signals to be displayed on the display panel 2100 are appropriately selected or combined. At that time, a control signal is generated to the display panel controller 2102 according to the image signal to be displayed, and the screen display frequency, the scanning method (for example, interlace or non-interlace), and the scan line of one screen are generated. The operation of the display device such as the number is appropriately controlled. Further, the CPU 2106 directly outputs image data and character / graphic information to the image generation circuit 2107, or accesses an external computer or memory via the input / output interface circuit 2105 to obtain image data and character / figure information. Enter graphic information.

Of course, the CPU 2106 may also be involved in work for purposes other than these. For example, it may be directly related to a function of generating and processing information, such as a personal computer or a word processor. Alternatively, as described above, the computer may be connected to an external computer network through the input / output interface circuit 2105, and work such as numerical calculation may be performed in cooperation with an external device.

The operator of this device uses the input unit 2114
It is for inputting commands, programs, data, etc. in 106. For example, in addition to a keyboard and mouse,
It is possible to connect various input devices such as joysticks, bar code readers, and voice recognition devices.

The decoder 2104 is used by the image generation circuit 2107 to display the TV.
This is a circuit for inversely converting various image signals input from the signal receiving circuit 2113 into three primary color signals or luminance signals and I signals and Q signals. As shown by the broken line in the figure, it is desirable that the decoder 2104 has an image memory inside, and this can be used for image signals that require an image memory for reverse conversion, such as MUSE TV signals. This is for handling. In addition, by providing an image memory, JP
It makes it easy to display still images compressed by EG method and moving images compressed by MPEG method, and image generation circuit.
In cooperation with the 2107 and the CPU 2106, it is possible to easily perform various types of image processing and editing such as image thinning, interpolation, enlargement, reduction, and composition.

The multiplexer 2103 is for appropriately selecting the display image based on the control signal input from the CPU 2106. That is, the multiplexer 2103 is a decoder
A desired image signal is selected from the inversely converted image signals input from 2104 and output to the drive circuit 2101. In that case, by switching and selecting a plurality of image signals within the time for displaying one screen, one screen is divided into a plurality of areas and a different image is displayed for each area, as in a so-called multi-screen television. It is also possible to do so.

The display panel controller 2102 is
Based on the control signal input from the CPU2106, the drive circuit 2
A circuit for controlling the operation of the display panel 2100, which is related to the basic operation of the display panel 2100. For example, a signal for controlling the operation sequence of a power supply (not shown) for driving the display panel 2100 is supplied to the drive circuit 2101. Output. Further, as a component related to the driving method of the display panel 2100, for example, a signal for controlling the screen display frequency and the scanning method is output to the driving circuit 2101. Also,
In some cases, control signals relating to image quality adjustment such as brightness, contrast, color tone, and sharpness of the display image may be output to the drive circuit 2101.

The drive circuit 2101, the display panel 2100
It is a circuit for generating a drive signal to be applied to, and operates based on the image signal input from the multiplexer 2103 and the control signal input from the display panel controller 2102.

Although the functions of the respective units have been described above, the configuration illustrated in FIG. 22 allows the display panel 2100 to display image information input from various image information sources in this apparatus. That is, various image signals such as TV broadcast are inversely converted by the decoder 2104, appropriately selected by the multiplexer 2103, and input to the drive circuit 2101. On the other hand, the display controller 2102 generates a control signal for controlling the operation of the drive circuit 2101 according to the image signal to be displayed. Drive circuit 2101
Applies a drive signal to the display panel 2100 based on these image signals and control signals. As a result, the image is displayed on the display panel 2100. A series of these operations is controlled by the CPU 2106.

Further, in this apparatus, the image memory built in the decoder 2104, the image generation circuit 2107 and the CPU 210.
Due to 6 involved, not only the selected one of a plurality of image information is displayed, but also the image information to be displayed is enlarged, reduced, rotated, moved, edge emphasized, thinned, interpolated, or colored. It is also possible to perform image processing such as conversion and aspect ratio conversion of images, and image editing such as combining, erasing, connecting, replacing, fitting, and cutting out.

Although not particularly mentioned in the above description, a dedicated circuit for processing and editing sound information may be provided as in the above-described image processing and image editing.

As described above, the present apparatus is used for display equipment for TV broadcasting, terminal equipment for videoconference, image editing equipment for handling still images and moving images, computer terminal equipment, office terminal equipment such as word processors, and games. It is possible to combine the functions of a machine with one unit, and has a very wide range of applications for industrial or consumer use.

Note that FIG. 22 merely shows a structural example of a display device using the display panel 2100 having a surface conduction electron-emitting device as an electron beam source, and the display device of this embodiment is not limited to this. Not a thing. For example, of the constituent elements shown in FIG. 22, circuits relating to functions that are unnecessary for the purpose of use may be omitted, and conversely, further constituent elements may be added depending on the purpose of use. For example,
When this device is applied to a videophone, a TV camera, lighting, audio microphone, speaker, transmission / reception circuit including MODEM and NCU, etc. are added to the components.

In this device, a display panel 2100 using a surface conduction electron-emitting device as an electron beam source is used.
Since it can be easily thinned, the depth of the entire device can be reduced. In addition, a display panel 2100 using a surface conduction electron-emitting device as an electron beam source.
Since it is easy to enlarge the screen, has high brightness, and has excellent viewing angle characteristics, this device can display a highly realistic image with high visibility.

[0142]

As described above, according to the present invention,
It is possible to provide an electron source drive device, an image forming apparatus, and methods for correcting an uneven distribution of a voltage supplied to an electron source caused by a voltage drop in a wiring.

Further, it is possible to provide an image forming apparatus and an image forming method for correcting the non-uniform distribution of the voltage supplied to the electron source to form a high quality and high definition image.

[Brief description of the drawings]

FIG. 1 is a plan view showing a typical example of a device configuration of a surface conduction electron-emitting device,

FIG. 2 is a diagram showing an example of a multi-electron beam source by an electronic wiring method,

FIG. 3 is a diagram showing an m × n simple matrix circuit of surface conduction electron-emitting devices arranged in a matrix and its wiring resistance;

FIG. 4 is a diagram showing a voltage applied to each device electrode in a column direction,

FIG. 5 is a diagram showing voltages applied to respective elements on the same line when luminance values have a distribution;

FIG. 6 is a block diagram for explaining a driving method of an image forming panel,

FIG. 7 is a timing chart showing an example of these timing signals,

FIG. 8 is a diagram showing how a digital signal D0 is stored in a shift register group;

FIG. 9 is a diagram showing an example of a timing signal Q3,

FIG. 10 is a block diagram showing a configuration example of an arithmetic circuit,

FIG. 11 is a block diagram showing a detailed configuration example of a voltage drop calculation circuit;

FIG. 12 is a perspective view of a display panel used in this embodiment,

FIG. 13A is a diagram showing an example of a fluorescent film,

FIG. 13B is a diagram showing an example of a fluorescent film,

FIG. 14A is a plan view illustrating the configuration of a planar surface conduction electron-emitting device,

14B is a cross-sectional view of the device shown in FIG. 14A,

FIG. 15A is a cross-sectional view for explaining the manufacturing process of the element shown in FIG. 14A,

15B is a sectional view for explaining the manufacturing process for the device shown in FIG. 14A,

FIG. 15C is a cross-sectional view for explaining the manufacturing process for the device shown in FIG. 14A,

FIG. 15D is a sectional view for explaining the manufacturing process for the device shown in FIG. 14A,

FIG. 15E is a sectional view for explaining the manufacturing process for the device shown in FIG. 14A,

FIG. 16 is a diagram for explaining in detail an energization method in an energization forming process;

FIG. 17A is a diagram showing an example of an appropriate voltage waveform applied during the energization activation process;

17B is a diagram showing the progress of the energization activation process, FIG.

FIG. 18 is a schematic cross-sectional view for explaining the basic configuration of a vertical surface conduction electron-emitting device,

19A is a cross-sectional view illustrating the manufacturing process of the element shown in FIG.

19B is a cross-sectional view illustrating the manufacturing process of the element illustrated in FIG.

19C is a cross-sectional view illustrating the manufacturing process of the element illustrated in FIG.

19D is a cross-sectional view illustrating the manufacturing process of the element illustrated in FIG.

19E is a cross-sectional view illustrating the manufacturing process of the element illustrated in FIG.

19F is a cross-sectional view illustrating the manufacturing process of the element illustrated in FIG.

FIG. 20 is a diagram showing a typical example of a relationship between an emission current Ie and a device current If of a surface conduction electron-emitting device and a device voltage Vf;

21A is a partial plan view of a multi-electron beam source used in the display panel shown in FIG.

FIG. 21B is a sectional view taken along the line AA ′ of FIG. 21A,

FIG. 22 is a block diagram showing an example of a multi-function display device.

[Explanation of symbols]

 1005 Rear plate 1006 Side wall 1007 Face plate 1008 Fluorescent film 1009 Back plate 1013 Row direction wiring 1014 Column direction wiring 1101 Substrate 1102, 1103 Element electrode 1104 Conductive thin film 1105 Electron emission part 1113 Thin film formed by energization activation treatment

 ────────────────────────────────────────────────── ─── Continuing on the front page (72) Inventor Hidetoshi Suzumi 3-30-2 Shimomaruko, Ota-ku, Tokyo Inside Canon Inc.

Claims (9)

[Claims] 1. A multi-electron source in which at least a plurality of cold cathode electron sources are two-dimensionally arranged and each electron source is connected in a matrix by row-direction wirings and column-direction wirings, and the row-direction wirings are scanned row by row. Scanning means, input means for inputting a predetermined voltage to an input terminal of a row scanned by the scanning means, and a voltage drop due to the row-direction wiring and the column-direction wiring for each column based on the input image signal. Computing means for computing, modulation means for generating a modulated signal in which a plurality of pulses are combined based on the input image signal in synchronization with the scanning of the scanning means, and the computing means according to the modulated signal. The driving voltage of the electron source that compensates the voltage drop for each column calculated by
A driving device for an electron source, comprising: a supply unit that supplies the input end of the column direction wiring. 2. The driving of the electron source according to claim 1, wherein the modulation unit generates the modulation signal by combining pulses of width N (positive integer). apparatus. 3. The calculation means sets a current value supplied from the input image signal to each electron source in one row, a preset row-direction wiring resistance and column-direction wiring resistance of the electron source, and preset values. The voltage drop for each column is calculated based on the row resistance and the wiring resistance for guiding the column-direction wiring to the outside of the multi-electron source. Source drive. 4. A multi-electron source in which at least a plurality of cold cathode electron sources are two-dimensionally arranged and each electron source is connected in a matrix by row-direction wirings and column-direction wirings, and the row-direction wirings are scanned row by row. Scanning means, input means for inputting a predetermined voltage to an input terminal of a row scanned by the scanning means, and a voltage drop due to the row-direction wiring and the column-direction wiring for each column based on the input image signal. Computing means for computing, modulation means for generating a modulated signal in which a plurality of pulses are combined based on the input image signal in synchronization with the scanning of the scanning means, and the computing means according to the modulated signal. The driving voltage of the electron source that compensates the voltage drop for each column calculated by
An image forming apparatus comprising: a supply unit that supplies the input end of the column-direction wiring; and a light emitting unit that emits light by electrons emitted from the cold cathode electron source. 5. The image forming apparatus according to claim 4, wherein the modulation unit generates the modulation signal by combining N (positive integer) types of pulses having a width. 6. The calculation means sets a current value supplied from the input image signal to each electron source in one row, a preset row-direction wiring resistance and column-direction wiring resistance of the electron source, and preset values. An image according to claim 4, wherein the voltage drop is calculated for each column based on the row resistance and the wiring resistance for guiding the column wiring to the outside of the multi-electron source. Forming equipment. 7. The modulator according to claim 4, wherein the modulator generates a modulation signal for controlling a light emission amount of the light emitter according to the image signal to form a gradation image. The image forming apparatus described in any one of 1. 8. A multi-electron source driving method in which at least a plurality of cold cathode electron sources are two-dimensionally arranged and each electron source is connected in a matrix by row-direction wirings and column-direction wirings. A scanning step of scanning the wiring line by line, an input step of inputting a predetermined voltage to the input terminal of the row scanned in the scanning step, and a voltage drop due to the row-direction wiring and the column-direction wiring based on the input image signal. A calculation step of calculating each column, a modulation step of generating a modulation signal in which a plurality of pulses are combined based on the input image signal in synchronization with the scanning of the scanning step, and in accordance with the modulation signal. And a supply step of supplying the drive voltage of the electron source, which has been compensated for the voltage drop for each column calculated in the calculation step, to the input end of the column direction wiring. The driving method of the electron source to be. 9. A multi-electron source in which at least a plurality of cold cathode electron sources are two-dimensionally arranged and each electron source is connected in a matrix by row-direction wiring and column-direction wiring; An image forming method of an image forming apparatus, comprising: a light emitting unit that emits light by electrons; a scanning step of scanning the row-direction wiring line by line; and inputting a predetermined voltage to an input terminal of the row scanned in the scanning step. An input step for calculating the voltage drop due to the row-direction wiring and the column-direction wiring for each column based on the input image signal, and the input image signal in synchronization with the scanning of the scanning unit. A modulation step of generating a modulation signal in which a plurality of pulses are combined on the basis of, and before compensating the voltage drop for each column calculated in the calculation step according to the modulation signal. And a supplying step of supplying a driving voltage of the electron source to an input end of the column-direction wiring.