JPH09129838A - Master slice semiconductor integrated circuit device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To enable the writing of data in a read-only storage circuit after a wiring process is finished, by applying a voltage across terminals of a wiring layer electrically connected with a gate electrode, and controlling electrical connection and disconnection of programmable elements. SOLUTION: Programmable elements 111, 112 are arranged on a diffusion region of a transistor 103 for word selection, or on wiring layers 109, 110 electrically connected with the diffusion region, and on gate electrodes 107, 108 of transistor rows 113, 114, or between wiring layers 105, 106 electrically connected with the gate electrodes. Electrical conduction and disconnection of the programmable elements is controlled by applying a programming voltage Vp which is a voltage capable of controlling electrical conduction and disconnection of the programmable elements to voltage applying terminals 119, 120, 121, 122. The programming voltage Vp is a voltage exceeding a circuit operation voltage in order not to control unnecessarily electrical connection and disconnection of the programmable elements at the time of circuit operation.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a master slice type semiconductor integrated circuit device and relates to a read data write and read circuit structure in the case of configuring a programmable memory circuit in the device.

[0002]

2. Description of the Related Art Currently, when a logic including a read-only memory circuit is constructed in a master slice type semiconductor integrated circuit device which realizes a dedicated logic by manufacturing the transistor first and changing a wiring process, In the wiring process, a method of writing data by electrically connecting the transistor and the power supply wiring layer or the transistor for the read-only storage circuit and the power supply wiring layer by a metal wiring to configure a read-only storage circuit is the mainstream is there.

FIG. 5 shows a circuit example of a read-only memory circuit of 5 words × 2 bits by a data writing method in a data string unit in a conventional master slice type semiconductor integrated circuit device. In FIG. 5, 501, 502, and 503 are word lines of the read-only circuit device, and 522 and 523 are bit lines of the read-only memory circuit. The first conductivity type transistor or the second conductivity type transistor, each of which shares the gate electrode and constitutes the transistor array, 51
6 and 517, 518 and 519, 520 and 521, one diffusion region is electrically connected to the bit line, and the diffusion region not connected to the bit line is electrically VDD or V.
It is connected to the potential of SS. In the case of a read-only memory circuit having a 2-bit configuration, 4 bits of a 2-bit data string (0,0), (1,0), (0,1), (1,1) are used.
When the word line 501 is selected for data reading when the transistor array capable of outputting the pattern data exists, the bit line is selected by the transistor array connected to the word selection transistor 504 of the selected word line. The data (0, 0) is output to 522 and 523. In the conventional example of FIG. 5, the word selection transistor 50 is used.
The diffusion regions 4, 505 and 506 are electrically connected to the gate electrodes of the transistor columns through metal wirings and vias 510, 511 and 512, respectively, and are manufactured in the wiring process.

FIG. 6 shows a circuit example of a read-only memory circuit in a conventional master slice type semiconductor integrated circuit device by a bit-by-bit data writing method. In FIG. 6, reference numerals 605, 606, ... 608 denote the first conductivity type transistors or the second conductivity type transistors,
Functions as a data writing transistor. 601 and 602 are word lines of the read-only memory circuit device, and 603 and 604 are bit lines of the read-only memory circuit device. When the word line 601 is selected 605,
The first (second) conductivity type transistor of 606 is turned on,
The first (second) conductivity type transistors 607 and 608 connected to the word line 602 are turned off, and the bit line 60
The potential of VSS is output to 3 and the potential of VDD is output to the bit line 604. The conventional example of FIG. 6 is similar to the conventional example of FIG.
The data writing transistor and the bit line are connected to each other through a metal wiring and a via, and are manufactured in the wiring process.

[0005]

However, in the conventional method, the power supply wiring, the transistor, and the diffusion region of the word selection transistor are connected through the metal wiring manufactured in the wiring process and the via. Therefore, in order to write the data, when the write data is corrected, it is necessary to perform mask correction and remanufacturing. Therefore, in the conventional method, the correction of the write data is an obstacle to the short delivery time which is the characteristic of the master slice type semiconductor integrated circuit device characterized by the short delivery time, and at the same time, the cost for the correction of the write data is high. Will increase. Further, since the data is written in the wiring process, it is impossible to write different individual data for each chip.

The present invention solves the above-mentioned problems, and in a master slice type semiconductor integrated circuit device, a programmable element which can be manufactured in a wiring step and which can be programmed after the manufacturing is completed is used. The purpose is to provide a secure data writing structure.

[0007]

Means for Solving the Problems One or more first conductivity type transistors and one or more second conductivity type transistors forming a logic on a semiconductor substrate, a metal wiring layer, and electrically conductive / non-conductive control. In a master slice type semiconductor integrated circuit device having one or more programmable elements capable of being configured, one or more gate electrodes of the first conductivity type transistor or the second conductivity type transistor are electrically connected. Of the transistor row, a word selecting transistor for selecting data, one diffusion region of the word selecting transistor, or a wiring layer electrically connected to the one diffusion region, and The programmable element is present between the gate electrode or the wiring layer electrically connected to the gate electrode, and the word selection is performed. Existing in one diffusion region of the transistor for use, or a wiring layer electrically connected to the one diffusion region, a gate electrode of the transistor row, or a wiring layer electrically connected to the gate electrode. A memory circuit is configured by controlling conduction and non-conduction of a programmable element by applying a voltage between terminals, and electrically connects with one diffusion region of one word selection transistor or one diffusion region of the word selection transistor. Is electrically connected to the gate electrode of one transistor row, or one diffusion region of one word selection transistor, or one diffusion region of the word selection transistor. The wiring layer electrically connected to the region is electrically connected to the gate electrodes of the plurality of transistor columns.

One or more first conductivity type transistors and one or more second conductivity type transistors forming logic on a semiconductor substrate, a metal wiring layer, and one or more electrically conductive / non-conductive controllable elements. In a master slice type semiconductor integrated circuit device having a programmable element, a transistor array configured by electrically connecting at least one gate electrode of the first conductivity type transistor or the second conductivity type transistor, A word selecting transistor for selecting data, one diffusion region of the word selecting transistor, or a wiring layer electrically connected to the one diffusion region, and a gate electrode of the transistor array,
Alternatively, there is the programmable element arranged between layers of a wiring layer electrically connected to the gate electrode, and a control transistor for controlling electrical connection between the programmable element and the gate electrode of the transistor array. , The control transistor electrically separates the connection between the programmable element and the gate electrode of the transistor row to electrically connect to one diffusion region of the word selection transistor or to one diffusion region of the word selection transistor. A conductive layer and a gate electrode of the transistor array or a terminal existing in a wiring layer electrically connected to the gate electrode by applying a voltage to control conduction and non-conduction of the programmable element to control the memory circuit. And a diffusion region of one of the word selection transistors or an expansion of the one of the word selection transistors. A wiring layer electrically connected to the region is electrically connected to a gate electrode of one transistor row, or one diffusion region of one word selection transistor, or one diffusion region of the word selection transistor. And a wiring layer electrically connected to the gate electrodes of the plurality of transistor columns.

[0009]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 shows a first basic configuration circuit example of a memory circuit having programmable elements according to the present invention and capable of data programming in data string units. FIG.
, 101 and 102 are word lines of a read-only circuit device, 103 and 104 are word selection transistors,
Reference numerals 117 and 118 denote bit lines of the read-only memory circuit. Each of the transistor arrays 11 shares a gate electrode.
3, 114, the first conductivity type transistor or the second conductivity type transistor, 115, 116.
One of the diffusion regions is electrically connected to the bit line, and the diffusion region not connected to the bit line is electrically VDD,
Alternatively, it is connected to the potential of VSS. In the case of a read-only memory circuit having a 3-bit structure, 3-bit data strings (0, 0, 0), (1, 0, 0), (0, 1,
0), ... (1, 1, 1) There are the above-mentioned transistor arrays capable of outputting eight patterns of data. In FIG. 1, 111 and 112 are programmable elements according to the present invention, and 119, 120, 121 and 122 are voltage application terminals to the programmable elements according to the present invention. The programmable elements 111 and 112 include a diffusion region of the word selection transistor 103, or wiring layers 109 and 110 electrically connected to the diffusion region, and gate electrodes 107 and 108 or gates of the transistor rows 113 and 114. Wiring layers 105 and 106 electrically connected to the electrodes
Are located between the layers. Then, the voltage applying terminal 1
Application of a programming voltage VP, which is a voltage capable of controlling conduction / non-conduction of the programming element of the programming element, to 19, 120, 121, 122 controls conduction / non-conduction of the programmable element. Further, the programming voltage VP is a voltage exceeding the circuit operation voltage so that the programming element is not unnecessarily turned on or off during the circuit operation.

FIG. 2 shows an example of a programming circuit of a memory circuit having programmable elements according to the present invention and capable of data programming in data string units. In FIG. 2, 201, 202 and 203 are word selection transistors, 221, 222 and 223 are gate terminals for controlling the word selection transistors, and 204 and 227 are connected to diffusion regions of all word selection transistors. Then
A power supply terminal that supplies a potential when writing data and reading data, and a wiring. And 218, 21
Reference numerals 9 and 220 denote transistor row selection transistors, 22
4, 225 and 226 are gate terminals for controlling the transistor row selecting transistors, and 205 and 228 are connected to the diffusion regions of all the transistor row selecting transistors, and at least power supply terminals for supplying a potential at the time of data writing, and wiring. Is. Also, 209, 210, ...
.. 217 are programmable elements of the present invention. FIG.
In the circuit shown in FIG. 5, when the word selection transistor 201 is selected in a state where VSS (or programming voltage VP) is applied to the voltage application terminal 204 and programming voltage VP (or VSS) is applied to the voltage application terminal 205, When writing data to output the data of the transistor row 1, the transistor 220 that selects the transistor row 1 is turned on, the transistors 218 and 219 that select the transistor row 2, N are turned off, and the word selection transistor 201 is turned on. By turning off the word selection transistors 202 and 203, the programming voltage VP is applied to the programmable element 209 to change from the non-conducting state to the conducting state, and data writing is performed. Except for the programmable element 209, the programmable element 210, ...
0, ..., 217 are in a non-conductive state. Therefore, when the word selection transistor 201 is selected at the time of reading data, only the transistor of the transistor row 1 is enabled and the data of the transistor row 1 is output. In the case where the programmable element is the first conductive element, the gate electrodes of all the transistor rows that are not selected, or the wiring layer electrically connected to the gate electrodes, and one of the word selecting transistors are selected. Data can be written by applying a voltage to a diffusion region or a programmable element arranged between layers of a wiring layer electrically connected to the one diffusion region to change the programmable element from a conductive state to a non-conductive state. It is possible.

FIG. 3 is a diagram showing a second basic configuration circuit example of a memory circuit having programmable elements according to the present invention and capable of data programming in data string units. FIG.
, 304, 305, 306 are word selection transistors, 301, 302, 303 are gate terminals for controlling the word selection transistors, and 307, 30
Reference numeral 8 denotes a power supply terminal connected to the diffusion regions of all the word selection transistors and supplying a potential during data writing and data reading, and wiring. And 32
3, 324, 325 are transistor row selecting transistors, 326, 327, 328 are gate terminals for controlling the transistor row selecting transistors, and 329, 3
Reference numeral 30 is a power supply terminal that is connected to the diffusion regions of all the transistor column selection transistors and supplies a potential at the time of writing data, and a wiring. Also, 309,
Reference numerals 310, ..., 314 are programmable elements of the present invention. Reference numerals 318, 319 and 320 denote transistors for controlling the connection between the programmable element and the transistor row of the present invention, and 321 denotes a gate terminal for controlling the connection control transistor between the programmable element and the transistor row of the present invention. To write data in the circuit shown in FIG. 3, VSS (or programming voltage V
P), programming voltage VP at voltage application terminal 329
(Or VSS) is applied and a voltage is applied to the gate terminal 321 for controlling the connection control transistor of the programmable element and the transistor array to turn off the connection control transistor. When data is written so as to output the data of the transistor array 1 when selected, the transistor 323 that selects the transistor array 1 is turned on, and the transistors 324 and 325 that select the transistor array 2 and N.
Is turned off, the word selection transistor 304 is turned on, and the word selection transistors 305 and 306 are turned off, the programming voltage VP is applied to the programmable element 309 to change from the non-conducting state to the conducting state, and data writing is performed. Be seen. In this embodiment,
By arranging the connection control transistors 318, 319 and 320 and turning off the connection control transistor at the time of writing data, the programming voltage applied to the power supply terminal 307 or the power supply terminal 329 is set to the transistor row. It is not applied to the gate terminals of the constituent transistors. As described above, the programming voltage is equal to or higher than the circuit operating voltage. Therefore, if the connection control transistor of the present invention is not present, the transistors forming the transistor array need to have a gate-source breakdown voltage equal to or higher than the programming voltage. Therefore, it is difficult to use a transistor using a fine process that operates at high speed for the transistor array. However, since the writing circuit of the programming element and the transistor row can be separated by the connection control transistor of the present invention, it is possible to use a transistor that uses a fine process for high-speed operation as a transistor forming the transistor row. is there.

FIG. 4 is a diagram showing a third basic configuration circuit example of a memory circuit having programmable elements according to the present invention and capable of data programming in data string units. FIG.
, 404, 405, 406 are word selection transistors, 401, 402, 403 are gate terminals for controlling the word selection transistors, and 407, 40.
Reference numeral 8 denotes a power supply terminal, which is connected to the diffusion regions of all word selection transistors, supplies a potential when writing data or reading data, and wiring. And 4
27, 428, 429 and 430 are transistor row selecting transistors, 431, 432, 433 and 434 are gate terminals for controlling the transistor row selecting transistors,
435 and 436 are power supply terminals and wirings connected to the diffusion regions of all the transistor column selecting transistors and supplying a potential at the time of data writing or data reading. Also, 409, 410, ... 4
16 is a programmable element of the present invention. And 4
Reference numerals 37 and 438 are bit lines which are composed of different transistor arrays of the present invention and which are electrically isolated.
In the case of the 8-bit read-only memory circuit, the 8-bit data string is (0, 0, 0, 0, 0, 0, 0, 0), (1,
(0, 0, 0, 0, 0, 0, 0), ... (1, 1, 1,
256 patterns of 1, 1, 1, 1, 1), and when forming an 8-bit read-only circuit, the transistor array capable of outputting the 256-pattern data is required. However, when 8 bits are divided into two blocks of 4 bits, it is possible to configure an 8-bit circuit with 32 patterns of transistor arrays, which is twice as many as 16 patterns of 4-bit data arrays. That is, in the circuit shown in FIG. 4, the word selection transistor 404 is selected in the state where VSS (or programming voltage VP) is applied to the voltage application terminal 407 and programming voltage VP (or VSS) is applied to the voltage application terminal 435. When writing data so as to output the data of the transistor row 1 and the transistor row A at the time, the transistor 427 selecting the transistor row 1 and the transistor 430 selecting the transistor row A are turned on and the transistor row 2 is selected. The programming voltage V is applied to the programmable elements 409 and 420 by turning off the transistor 428 and the transistor 429 that selects the transistor array B, turning on the word selecting transistor 404 and turning off the word selecting transistors 405 and 406.
P is applied to change from the non-conducting state to the conducting state, and data writing is performed. Then, when the word selection transistor 404 is selected at the time of data reading, the transistors of the transistor array 1 and the transistors of the transistor array A are enabled, and the data of the transistor array 1 and the transistor array A are output. . Then, the data of the transistor row 1 is combined with the upper bit (lower bit) and the data of the transistor row A is combined with the lower bit (upper bit) to obtain the sum of the bit number of the transistor row 1 and the bit number of the transistor row A. It is possible to represent data corresponding to the number of bits. Therefore, in this embodiment, the transistor row 1 is set to 4
When the number of bits and the transistor array A is 4 bits, the number of metal wirings, transistor arrays, and programmable elements can be reduced as compared with the case where an 8-bit transistor array is used and 256 patterns are formed.

[0013]

As described above, according to the present invention, in the master slice type semiconductor integrated circuit device, it is possible to write the data in the read-only memory circuit after the wiring process is completed, and the data is corrected. Can be realized at low cost in a short time, and data can be written in the read-only memory circuit after the wiring process is completed. Therefore, there is an effect that data dedicated to the chip can be written.

Further, the connection control transistor of the present invention has the effect that the transistor of the write circuit to which the programming voltage exceeding the circuit operating voltage is applied and the transistor of the transistor array can be separated.

Further, by changing the bit configuration of the read-only circuit to form blocks, the number of metal wirings, transistors, and programmable elements forming the circuit of the read-only circuit can be reduced, and read-only can be efficiently programmed. It has an effect that a circuit can be configured.

[Brief description of the drawings]

FIG. 1 is a diagram showing a first basic configuration circuit example of a memory circuit capable of data programming in a data string unit having a programmable element in the present invention.

FIG. 2 is a diagram showing an example of a programming circuit of a memory circuit capable of data programming in data string units having programmable elements according to the present invention.

FIG. 3 is a diagram showing a second basic configuration circuit example of a memory circuit capable of data programming in data string units having programmable elements according to the present invention.

FIG. 4 is a diagram showing a third basic configuration circuit example of a memory circuit capable of data programming in data string units having programmable elements according to the present invention.

FIG. 5 is a diagram showing an example of a 5-word × 2-bit circuit of a read-only memory circuit by a data writing method in data string units in a conventional master slice type semiconductor integrated circuit device.

FIG. 6 is a diagram showing a 4-word × 2-bit circuit example of a read-only memory circuit by a bit-wise data writing method in a conventional master slice type semiconductor integrated circuit device.

[Explanation of symbols]

101, 102, 501, 502, 503, 601, 6
02 ... Gate electrodes of word selection transistors 103, 104, 201, 202, 203, 304, 3
05, 306, 404, 405, 406, 504, 50
5, 506 ... Word selection transistors 105, 106, 107, 108, 206, 207, 2
08, 315, 316, 317, 417, 418, 41
9, 420, 423, 424, 425, 426, 50
7, 508, 509, 513, 514, 515 ...
Gate electrodes of transistor rows or regions 109, 110, 229, 230, 331, 332, 4 electrically connected to gate electrodes of transistor rows in an electric circuit
21, 422 ... Drain region of word selection transistor, or region 111, 112, 209, 210, 211, 212, 2 electrically connected to the drain region of word selection transistor
13, 214, 215, 216, 217, 309, 31
0, 311, 312, 313, 314, 409, 41
0, 411, 412, 413, 414, 415, 416
... Programmable elements 113, 114 ... Transistor rows 115, 116, 516, 517, 518, 519, 5 sharing a gate electrode
20, 521 ... Transistors 117, 118, 437, 438, 522, 523, 6 forming a transistor array sharing a gate electrode
03, 604 ... Bit lines 119, 120 ... Signal connection terminals 121, 122, 204, 307, 407 to regions electrically connected to the gate electrodes of the transistor columns or the gate electrodes of the gate selection transistors ... Signal connection terminals 205, 329, 435 to diffusion regions of word selection transistors or regions electrically connected to diffusion regions of word selection transistors 205, 329, 435 ... Diffusion regions of transistor row selection transistors, Alternatively, signal connection terminals 218, 219, 220, 323, 324, 325, 4 to regions electrically connected to the diffusion regions of the transistor row selection transistors in an electric circuit manner.
27, 428, 429, 430 ... Transistor column selection transistors 221, 222, 223, 301, 302, 303, 4
01, 402, 403 ... Signal connection terminals 224, 225, 226, 326, 327, 328, 4 to the gate terminals of the word selection transistors
31, 432, 433, 434 ... Signal connection terminals 227, 308, 408 to gate terminals of transistor row selecting transistors 227, 308, 408 ... Diffusion regions of word selecting transistors, or diffusion regions of word selecting transistors and electric circuits Wiring 228, 330, 436 to the region electrically connected to each other ... Signal wiring to the diffusion region of the transistor for transistor row selection or to the region electrically connected to the diffusion region of the transistor for transistor row selection 318 319, 320 ... Transistor for controlling connection between programmable element and transistor array 321 ... Signal connecting terminal to control terminal of connection controlling transistor 322 ... Signal wiring to control terminal of connection controlling transistor 510, 511, 512 ... Via 605, 606 607, 608 ... data write transistor

Claims (6)

[Claims] 1. One or more first-conductivity type transistors and one or more second-conductivity type transistors forming a logic on a semiconductor substrate, a metal wiring layer, and one controllable electrically conducting / non-conducting state. In the master slice type semiconductor integrated circuit device having the above programmable element, a transistor array formed by electrically connecting at least one gate electrode of the first conductivity type transistor or the second conductivity type transistor. And a word selecting transistor for selecting data, and one of the word selecting transistors
The programmable element between one of the diffusion regions or the wiring layer electrically connected to the one diffusion region, and the gate electrode of the transistor row or the wiring layer electrically connected to the gate electrode. One of the diffusion regions of the word selection transistor that is present and is electrically connected to the wiring layer electrically connected to the one diffusion region is electrically connected to the gate electrode of the transistor row or the gate electrode. A master slice type semiconductor integrated circuit device, characterized in that a memory circuit is configured by controlling conduction / non-conduction of a programmable element by applying a voltage between terminals existing in a wiring layer. 2. The master slice type semiconductor integrated circuit device according to claim 1, wherein the diffusion region is electrically connected to one diffusion region of one of the word selecting transistors or to one diffusion region of the word selection transistor. A master slice type semiconductor integrated circuit device, wherein a wiring layer is electrically connected to a gate electrode of one transistor array. 3. The master slice type semiconductor integrated circuit device according to claim 1, wherein one diffusion region of one of the word selecting transistors is electrically connected to the one diffusion region. A master slice type semiconductor integrated circuit device, wherein a wiring layer is electrically connected to gate electrodes of the plurality of transistor columns. 4. One or more first conductivity type transistors and one or more second conductivity type transistors forming a logic on a semiconductor substrate, a metal wiring layer, and one electrically controllable one that is electrically conductive or non-conductive. In the master slice type semiconductor integrated circuit device having the above programmable element, a transistor array formed by electrically connecting at least one gate electrode of the first conductivity type transistor or the second conductivity type transistor. And a word selecting transistor for selecting data, and one of the word selecting transistors
One of the diffusion regions, or a wiring layer electrically connected to the one diffusion region, and the gate electrode of the transistor row, or the wiring layer electrically connected to the gate electrode. There is a programmable element and a control transistor for controlling electrical connection between the programmable element and the gate electrode of the transistor array, and the control transistor electrically connects the programmable element and the gate electrode of the transistor array. Electrically separated from each other, one diffusion region of the word selection transistor, or a wiring layer electrically connected to the one diffusion region, and a gate electrode of the transistor row,
Alternatively, a master slice semiconductor integrated circuit characterized in that a memory circuit is configured by controlling conduction / non-conduction of a programmable element by applying a voltage between terminals existing in a wiring layer electrically connected to the gate electrode. Circuit device. 5. The master slice type semiconductor integrated circuit device according to claim 4, wherein one of the word selection transistors is electrically connected to one diffusion region or electrically connected to the one diffusion region. A master slice type semiconductor integrated circuit device, wherein a wiring layer is electrically connected to a gate electrode of one transistor array. 6. The master slice type semiconductor integrated circuit device according to claim 4, wherein the diffusion region is electrically connected to one diffusion region of one of the word selection transistors or to one diffusion region of the word selection transistor. A master slice type semiconductor integrated circuit device, wherein a wiring layer is electrically connected to gate electrodes of the plurality of transistor columns.