JPH09128990A - Semiconductor memory - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent a relief rate from being degradaded by simultaneous defects of adjacent lines by arranging spare word lines in a specified adjacent order in the constitution making plural pieces of spare word lines one set and displacing the defect. SOLUTION: A spare row decoder 10 outputs respective complementary pairs SWS0, /SWS0 and SWS1, /SWS1 of spare word line selection signals through partial spare row decoders 11, 12 according to combination of complementary pair RA0, /RA0 of the least significant bit of a row address signal and row decoder pre-charge signal /RDPi. Thus, the displacement of spare word lines SWL0-3 41-44 provided answering to at every block divided in word lines 256 pieces with a defect row in the answering block making a pair a unit is performed. At this time, cross arrangement is performed so that the spare word lines answering to an address specifying fuse are gotten together. For instance when adjacent spare word lines SWL0, 1 41, 43 are defective, they are relieved.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device having a redundant circuit.

[0002]

2. Description of the Related Art Personal computers and workstations have a memory for storing data. A large amount of data can be read and written in the memory, such as DRAM (Dynamic Random Access Mem).
ory), and is used as the main memory in personal computers, workstations, and the like.

FIG. 7 is a logic circuit diagram when a redundant circuit of a conventional DRAM drives a spare word line. In FIG.
Reference numeral 1 is a decoder, 2 is an AND circuit, SRX0 and SRX1 are spare row address designation fuse signals, RA0 is a row address least significant bit signal, and SWL0, SWL1, SWL2, SWL3 are spare word lines. The numbers 0 to 3 of SWL0, SWL1, SWL2, and SWL3 indicate the physical arrangement order on the memory chip.
Further, in this example, four spare word lines are arranged for each block (for example, 256 word lines) in the memory cell, and two spare word lines form a pair so that one defect can be replaced. In other words, 2 locations (2
The defect of (pair) can be replaced.

The reason for replacing a defect with a plurality of (two in this example) spare word lines as one set will be described. The spare word line replaces a defect of the word line in the memory wafer process, but a large number of spare word lines may be required depending on the size of the defect. For example, in an actual memory mass production factory, a large defect corresponding to four or more spare word lines is often found, which is an obstacle to improving the yield in the wafer process. Now, suppose that there is a defect that must be replaced with four or more spare word lines. If there are less than 4 spare word lines that can be replaced,
This defect cannot be replaced, and the chip cannot be a good product.
If four spare word lines are provided for each block in order to remedy such a defect, if spare word lines are replaced in units of one, four spare row addresses (row addresses of defective parts) are designated. Since it must be done, there are four fuses for specifying the spare row address.
Set is required. This indicates an increase in chip area, which may be one of the causes of a decrease in memory chip productivity.

Therefore, if a plurality of spare word lines are set as one set and a defect is replaced, the number of fuses designating spare row addresses can be reduced, and an increase in chip area can be suppressed. As a matter of course, if a plurality of spare word lines are set as one set and the defect is replaced, the degree of freedom regarding replacement is lowered, but depending on the defect occurrence situation in the memory mass production factory, the above-mentioned degree of defect is larger. Rescue may be important when improving productivity. In other words, it may be necessary to increase the number of spare word lines and simultaneously reduce the number of fuses that specify the spare row address in order to replace a large defect that should be replaced with a plurality of spare word lines. is there. This is the reason for replacing a plurality of (two in this example) spare word lines as one set with defective word lines.

Next, the operation of the redundant circuit shown in FIG. 7 will be described. Consider a case where a defect that should be replaced by two spare word lines occurs in a memory cell, and the defective bit is replaced by using the spare word lines SWL0 and SWL2 to repair the memory chip. In that case, the fuse corresponding to SRX0 that specifies the spare row address according to the row address of the defective portion is laser blown, and the row address of this defective portion is programmed. Then, when the input row address matches the programmed address, SRX0 is boosted to the boosted potential Vpp higher than the power supply potential Vcc. become. At this time, if the row address least significant bit RA0 is at H level (/ RA0 is at L level), SWL0 is activated and the boosted potential Vpp is increased. Next, RA
When 0 is at L level (/ RA0 is at H level), SWL2 is activated and a spare word line is selected in place of the word line at the defective portion. That is, in this example, two word lines corresponding to the row address having the same upper bit except the least significant bit RA0 of the row address are replaced by SWL0 and SWL2 in a set of two. The same operation is performed when the defective bit is replaced using spare word lines SWL1 and SWL3.

[0007]

In the conventional redundant circuit, the spare word line has a role of replacing a defective portion generated in the memory cell, but naturally the defective portion may occur in the spare word line itself. . If a defect occurs in the spare word line and the spare word line loses its function, and at the same time a defect occurs in the memory cell,
The defective part in the memory cell cannot be remedied. FIG. 8 illustrates a case where two of the spare word lines SWL0 to SWL3 shown in FIG. 7 are defective. Most of the defects in the mass production factory are caused by foreign substances generated in the wafer process, and the foreign substances frequently cause defects such as short circuits between physically adjacent lines. Therefore, the spare word line is also highly likely to cause a defect such as a short circuit between adjacent lines due to foreign matter.

Next, consider the case where adjacent spare word lines become defective. First, in the case 1 in which the spare word lines SWL0 and SWL1 are defective as shown in FIG. 8A, the spare word lines SWL0 and SWL2, SWL1 and SWL3 are set, and one set is used for each set. Since the spare word line becomes defective, the signal SRX0 is output as shown in FIG.
Both the set corresponding to and the set corresponding to the signal SRX1 cannot be used to replace the defective portion. next,
Even in case 2 in which the spare word lines SWL1 and SWL2 are defective as shown in FIG. 8B, one spare word line in each set is defective, so that as in case 1 as shown in FIG. , Set corresponding to signal SRX0, signal SRX1
As for the set corresponding to, both sets cannot be used to replace the defective part. Further, as shown in FIG. 8C, the spare word lines SWL2 and SWL3 are defective in case 3
However, since one spare word line in each set becomes defective, as shown in FIG.
Both the set corresponding to SRX0 and the set corresponding to signal SRX1 cannot be used to replace a defective portion. In other words, even if there are spare word lines that have no defects themselves, as a result, all spare word lines cannot be used.

To summarize the above, in the conventional configuration, when two adjacent spare word lines become defective, the remaining spare word lines of the block cannot be used, and it becomes impossible to perform the replacement function. Therefore, there is a problem that it becomes a factor for alienating improvement of chip productivity.

The present invention has been made in view of the above problems, and it is possible to reduce the number of cases in which a plurality of sets cannot be used for replacement even if a defect occurs in adjacent spare word lines. Has an aim.

[0011]

A semiconductor memory device according to the present invention has a plurality of sets of spare word lines, and spare word lines belonging to the same set are adjacent to each other.
Further, a plurality of word drivers for driving one corresponding word line in each set are connected to one decoder,
The word driver receives the corresponding decode signal and the spare word line drive signal corresponding to each set, drives the word line, and selects one of the row addresses for selecting one of the spare word lines in the same set. The decoder has a decoder that receives a signal and outputs a decode signal. Crosses the wiring between the word driver and the spare word line in the memory cell so that the spare word lines corresponding to the addressing fuses are located together. It was made.

[0012]

BEST MODE FOR CARRYING OUT THE INVENTION

Embodiment 1 FIG. Hereinafter, a DRAM according to an embodiment of the present invention will be described.
Will be described with reference to FIGS. 1 and 2. First, FIG.
FIG. 6 is a circuit diagram when the redundant circuit according to the first embodiment drives a spare word line. In FIG. 1, reference numeral 10 is a row address buffer (not shown) that takes in an address signal externally applied in response to the fall of the row address strobe signal / RAS and outputs it as a row address signal.
RA0, / RA0 part of the row address signal from and row decoder precharge signal corresponding to the memory cell block
When a block is selected in response to / RDPi and the corresponding row decoder precharge signal / RDPi is selectively set to H level, if the row address signal RA0 is H level, it is set to H level and L level, respectively. L respectively
Level and H level spare word line selection signal SW
When S0 and / SWS0 and the corresponding row decoder precharge signal / RDPi are selectively set to H level when the row address signal / RA0 is H level, they become H level and L level, respectively. Other than that, the spare row decoder outputs spare word line selection signals SWS1 and / SWS1 which are at L level and H level, respectively.

The spare row decoder 10 includes a row decoder precharge signal / RDPi and a row address signal RA0.
Partial spare row decoder 11 which receives spare word line selection signal SWS0 and its inverted signal / SWS0, and spare word line selection signal SWS1 and its inverse which receives row decoder precharge signal / RDPi and row address signal / RA0 It has a partial spare row decoder 12 which outputs a signal / SWS1. The partial spare row decoder 11 includes p-channel MOS transistors 11a, 11c and 11d and an n-channel MO transistor.
It has S-transistors 11b and 11e. Further, the partial spare row decoder 12 includes a p-channel MOS transistor 12a,
12c, 12d and n-channel MOS transistors 12b, 12e
have.

Reference numeral 21 denotes a spare word line selection signal SWS0 from the partial spare row decoder 11 via the contact hole 21b.
Selection signal wiring for transmitting the spare word line selection signal SWS0, 22 receives the spare word line selection signal / SWS0 from the partial spare row decoder 11 through the contact hole 22b, and receives the spare word line selection signal Select signal wiring for transmitting / SWS0, 23 is contact hole 23
The spare word line selection signal SWS1 from the partial spare row decoder 12 is received via b, and the spare word line selection signal SWS1 is received.
Selection signal wiring for transmitting SWS1, 24 receives the spare word line selection signal / SWS1 from the partial spare row decoder 12 through the contact hole 24b, and the selection signal for transmitting this spare word line selection signal / SWS1 Wiring.

Numeral 25 is output from a corresponding redundant row address program circuit (not shown) in which a portion other than RA0 of the defective row address (redundant row address) is programmed by cutting the fuse by laser blow, and input. The spare word line drive signal SWD0, which has a boosted potential Vpp higher than the power supply potential Vcc, is transmitted when the part of the stored row address signal other than RA0 matches the redundant row address programmed in the corresponding redundant row address program circuit. Drive signal wiring, 26 is redundant row address RA
The part except 0 is output from the corresponding redundant row address program circuit (not shown) which is programmed by cutting the fuse by laser blow, and the part except RA0 of the input row address signal is the corresponding redundant row address. A drive signal wiring for transmitting a spare word line drive signal SWD1 having a boosted potential Vpp higher than the power supply potential Vcc when the redundant row address programmed in the program circuit matches.

Reference numeral 31 is connected to the selection signal wirings 21 and 22 through the contact holes 21a and 22a, respectively, and a spare word line selection signal from the partial spare row decoder 11 is supplied.
Receives SWS0 and / SWS0 and is connected to drive signal line 25 through contact hole 25a
The spare word line drive signal SWD0 transmitted from the spare word line drive signal SWD0 is received from the spare word line selection signal SWS0, / SWS0 and the spare word line drive signal SWD0 to set the potential SWL0 of the corresponding spare word line 41 to the boosted potential Vpp. In the word driver, spare word line selection signals SWS0 and / SWS
When 0 is at H level and L level, respectively, and the spare word line drive signal SWD0 becomes the boosted potential Vpp, the potential SWL0 of the corresponding spare word line 41 becomes the boosted potential Vpp. This spare word driver 31 has n-channel MOS transistors 31a, 31b and 31c.

Reference numeral 32 is connected to the selection signal wirings 21 and 22 through the contact holes 21c and 22b, respectively, and a spare word line selection signal from the partial spare row decoder 11 is supplied.
It receives SWS0 and / SWS0 and is connected to the drive signal wiring 26 through the contact hole 26a.
The spare word line drive signal SWD1 transmitted from the spare word line drive signal SWD1 is received from the spare word line selection signal SWS0, / SWS0 and the spare word line drive signal SWD1 to set the potential SWL2 of the corresponding spare word line 42 to the boosted potential Vpp. In the word driver, spare word line selection signals SWS0 and / SWS
When 0 is at H level and L level, respectively, and spare word line drive signal SWD1 attains boosted potential Vpp, potential SWL2 of corresponding spare word line 42 attains boosted potential Vpp. This spare word driver 32 has n-channel MOS transistors 32a, 32b and 32c.

Reference numeral 33 is connected to select signal wirings 23 and 24 through contact holes 23a and 24a, respectively, and a spare word line select signal from the partial spare row decoder 12 is supplied.
Receives SWS1 and / SWS1 and is connected to drive signal line 25 through contact hole 25b
The spare word line drive signal SWD0 transmitted from the spare word line drive signal SWD0 is received from the spare word line select signal SWS1, / SWS1 and the spare word line drive signal SWD0 to set the potential SWL1 of the corresponding spare word line 43 to the boosted potential Vpp. In the word driver, spare word line selection signals SWS1 and / SWS
When 1 is at H level and L level, respectively, and spare word line drive signal SWD0 becomes boosted potential Vpp, potential SWL1 of corresponding spare word line 43 becomes boosted potential Vpp. This spare word driver 33 has n-channel MOS transistors 33a, 33b and 33c.

Reference numeral 34 is connected to the selection signal wirings 23 and 24 through the contact holes 23c and 24b, respectively, and a spare word line selection signal from the partial spare row decoder 12 is supplied.
Receives SWS1 and / SWS1 and is connected to drive signal line 26 through contact hole 26b to drive signal line 26
The spare word line drive signal SWD1 transmitted from the spare word line drive signal SWD1 is received from the spare word line selection signal SWS1, / SWS1 and the spare word line drive signal SWD1 to set the potential SWL3 of the corresponding spare word line 44 to the boost potential Vpp. In the word driver, spare word line selection signals SWS1 and / SWS
When 1 is at H level and L level, respectively, and spare word line drive signal SWD1 becomes boosted potential Vpp, potential SWL3 of corresponding spare word line 44 becomes boosted potential Vpp. Spare word driver 34 has n-channel MOS transistors 34a, 34b and 34c.

The circuit shown in FIG. 1 is provided corresponding to each block divided in units of 256 word lines, each of which corresponds to a defective row in a block corresponding to one pair of spare word lines. Can be replaced.

Next, the operation will be described. Here, FIG.
It is assumed that the row address (redundant row address) of the defective row in the block corresponding to the redundant circuit shown in (1) has already been programmed by cutting the fuse in the corresponding redundant row address program circuit by laser blow. Then, for the sake of simplicity, the operation when the spare word line 41 is selected will be described. First, when row address strobe signal / RAS is at H level indicating standby, spare word line drive signals SWD0 and SWD1 are both at the ground potential. Also, the row decoder precharge signal / RDPi is at L level, the row address least significant bits RA0 and / RA0 are both at L level, and therefore the p channel M
The OS transistors 11a and 12a are in the conductive state and the n-channel MO
The S transistors 11b and 12b are turned off, and the spare word line selection signals / SWS0 and / SWS1 are set to the H level.

The p-channel MOS transistors 11d and 12d receiving the H-level spare word line selection signals / SWS0 and / SWS1 at their gates are non-conductive, and the n-channel MOS transistors 11e and 12e are conductive and the spare word line is The selection signals SWS0 and SWS1 become L level. Further, the p-channel MOS transistors 11c and 12c receiving the L-level spare word line selection signals SWS0 and SWS1 at their gates become conductive, and the p-channel MOS transistor 11d, the n-channel MOS transistor 11e and the p-channel M transistor, respectively.
The OS transistor 12d and the n-channel MOS transistor 12e hold the spare word line selection signals / SWS0, / SWS1 at H level and SWS0, SWS1 at L level.

Therefore, these spare word line selection signals
The n-channel MOS transistors 31b, 32b, 33b, 34b in the spare word drivers 31, 32, 33, 34 which receive the corresponding one of SWS0, SWS1, / SWS0, / SWS1 are non-conductive, and n
The channel MOS transistors 31c, 32c, 33c, 34c become conductive, and the potentials SWL0, SWL of the spare word lines 41, 42, 43, 44
2, SWL1 and SWL3 are all at ground potential.

Next, when the address signal is applied and the row address strobe signal / RAS is activated to the L level,
The row address buffer latches this address signal as a row address and uses the row address signal RAk for the internal circuit.
(k = 0, 1, ...) And its inverted signal / RAk are output. The spare word line selection signal SWS0 is supplied in response to the row address signals RA0 and / RA0 of H level and L level, respectively.
And / SWS0 are at H level and L level, respectively, and spare word line selection signals SWS1 and / SWS1 are at L level and H level, respectively, and the spare channel drivers 31 and 32 have n channel MOS transistors 31b and
32b is conductive, and n-channel MOS transistors 31c and 32c are nonconductive. Also, the n-channel MOS transistors in the spare word drivers 33 and 34
33b and 34b remain non-conductive, and n-channel MOS transistors 33c and 34c remain conductive.

On the other hand, the redundant row address program circuit compares the redundant row address set in this circuit with the regular row address from the row address buffer, detects that they match, and detects the spare word line drive signal. SWD0 is boosted potential Vpp. Then, the boosted potential is applied to the drain of the n-channel MOS transistor 31b which is in the conductive state, the gate is self-boosted and becomes higher than the boosted potential Vpp, and the boosted potential Vpp is transmitted to the spare word line 41. The potential SWL0 of the spare word line 41 becomes the boosted potential Vpp. Also, the spare word line 43
The potentials SWL1 and SWL3 of 44 and 44 are at the ground potential because the n-channel MOS transistors 33b and 34b are in the non-conducting state and the n-channel MOS transistors 33c and 34c are in the conducting state, and the potential SWL2 of the spare word line 42 is n.
Although the channel MOS transistor 32b is conductive and the n-channel MOS transistor 32c is nonconductive, the spare word line drive signal SWD1 remains at the ground potential, so that it is at the ground potential. The defective word line replaced by the spare word line 41 is controlled so as not to be selected.

Next, each case shown in FIG. 8 in which two adjacent spare word lines are defective will be considered. First, in case 1 in which the spare word lines 41 and 43 are defective as shown in FIG. 8A, adjacent spare word lines 41 and 43, 42 and 44 are set,
Since the two spare word lines 41 and 43 of the same set become defective, as shown in FIG.
Although the set corresponding to D0 cannot be used, the set corresponding to the spare word line drive signal SWD1 can be used to replace a defective portion. Next, in case 2 in which the spare word lines 43 and 42 are defective as shown in FIG. 8B, one spare word line 43 and 42 in each set is defective, so that the case shown in FIG. As described above, in this case, both the set corresponding to the spare word line drive signal SWD0 and the set corresponding to the spare word line drive signal SWD1 cannot be used to replace the defective portion, as in the conventional case. Further, in case 3 where the spare word lines 42 and 44 are defective as shown in FIG. 8C, two spare word lines 42 and 44 of the same set are defective, so that as shown in FIG. Although the set corresponding to the spare word line drive signal SWD1 cannot be used, the set corresponding to the spare word line drive signal SWD0 can be used to replace the defective portion. In other words, in the past, replacement was not possible in all cases, but the number of replaceable sets is small, but the remaining sets are replaceable and defective locations can be repaired.

As described above, in the first embodiment, a plurality of word lines 41 and 43 (or 42 and 4) are used.
Since the partial spare row decoder 11 (or 12) is shared in 4), the layout area of the spare row decoder 10 can be reduced.

Also, the same spare word line drive signal SWD0
(Or SWD1) spare word lines 41 and 43
Since (or 42 and 44) are collectively arranged adjacent to each other, it is possible to increase the repair rate of the defective portion by the redundant circuit, thereby improving the yield.

Embodiment 2 Next, a DRAM which is a second embodiment of the present invention will be described with reference to FIGS. FIG. 3 is a block diagram showing a redundant circuit according to the second embodiment. 3 is different from the circuit diagram shown in FIG. 1 in that the spare word line and the spare word driver are increased to eight, and the spare word line drive signal SWD0
Alternatively, there are four spare word drivers and four spare word lines corresponding to SWD1. Therefore, the one shown in FIG. 1 has a pair of spare word lines (2
While the replacement with the defective row in the corresponding block can be performed in units of (book), the defective row in the block corresponding to four spare word lines in the unit shown in FIG. Can be replaced with.

Further, as the spare word drivers 31-38 and the spare word lines 41-48 are increased, the partial spare row decoder 13-16 also has four spare words corresponding to each spare word line drive signal SWD0 or SWD1. The number of lines 41, 43, 45 and 47 or one of lines 42, 44, 46 and 48 has been increased to four, and the specific circuit configuration (FIG. 4) has also changed. Corresponding selection signal wiring corresponding to this 27, 28, 29, 30
Is also newly added. In FIG. 1, the signal wiring 21-2
Although the schematic diagram of 6 is shown, the signal wiring is shown by a line in FIG. 3 for convenience. However, the wiring is arranged as in FIG. 1 and the signal is transmitted to the circuit connected to the wiring through the contact hole.

FIG. 4 is a circuit diagram showing a specific structure of the spare row decoder 10. The spare row decoder 10 includes a row decoder precharge signal / RDPi and a row address signal RA0.
Partial spare row decoder that outputs spare word line select signal SWS0 and its inverted signal / SWS0
13, a partial spare row decoder 14 which receives the row decoder precharge signal / RDPi and the row address signals / RA0 and RA1 and outputs a spare word line selection signal SWS1 and its inverted signal / SWS1 and a row decoder precharge signal
Spare word line select signal SWS2 and its inverted signal / SWS2 in response to / RDPi and row address signals RA0 and / RA1
And a partial spare row decoder 16 which outputs a spare word line selection signal SWS3 and its inverted signal / SWS3 in response to a row decoder precharge signal / RDPi and row address signals / RA0 and / RA1.
And

The partial spare word decoder 13 includes p-channel MOS transistors 13a, 13c, 13d and an n-channel MO transistor.
In addition to the S transistors 13b and 13e, it has an n-channel MOS transistor 13f. Further, the partial spare word decoder 14 includes p-channel MOS transistors 14a, 14c, 14d.
And n-channel MOS transistors 14b and 14e,
The partial spare word decoder 15 includes an n-channel MOS transistor 14f and a p-channel MOS transistor 15a,
15c, 15d and n-channel MOS transistors 15b, 15e
In addition, it has an n-channel MOS transistor 15f. Further, the partial spare word decoder 16 includes p-channel MOS transistors 16a, 16c, 16d and an n-channel MO transistor.
In addition to the S transistors 16b and 16e, it has an n-channel MOS transistor 16f.

FIG. 5 is a circuit diagram showing a concrete structure of the spare word drivers 31-38, and for the sake of convenience, only the structure of one spare word driver is shown. This spare word driver 31-38 is connected between the corresponding spare word line and the ground potential node, and the n-channel MOS transistors 31b-38b connected between the corresponding drive signal wiring and the corresponding spare word line. , N-channel MOS transistors 31c-38c whose gates are connected to corresponding drive signal lines,
Corresponding selection signal wiring and n-channel MOS transistor
N-channel MOS transistor 31a- connected between the gates of 31b-38b and the gate connected to the power supply potential node
38a and.

Also in the second embodiment configured as described above, since the partial spare row decoder is shared by a plurality of word lines, the layout area of the spare row decoder can be reduced and the same spare word line can be used. Since the spare word lines corresponding to the drive signals are collectively arranged adjacent to each other, it is possible to increase the repair rate of the defective portion by the redundant circuit, thereby improving the yield.

Embodiment 3 FIG. Next, a DRAM which is a third embodiment of the present invention will be described with reference to FIG.
FIG. 6 is a block diagram showing a redundant circuit according to the third embodiment. 6 is different from the circuit diagram shown in FIG. 1 in that in FIG. 1, spare word lines 42 and 43 are physically crossed so that spare word lines corresponding to the same spare word line drive signal are collectively adjacent to each other. However, the thing shown in this FIG. 6 only intersects logically and not physically. Word drivers 32 and word drivers instead of physically crossing spare word lines
Swap the position of 33 to replace this word driver 32 and 33.
Spare word line selection signals SWS1, / SWS1 and SWS0, / SWS0
The selection signal wirings 21, 22, 23, and 24 are extended to provide the signal. Along with this, in FIG. 1, the selection signal wirings 21, 22, 23, 24 have been arranged in two columns, whereas the one shown in FIG. 6 is different in that it is arranged in four columns. . In addition,
Although FIG. 1 shows a schematic view of the signal wirings 21-26, in FIG. 6, the signal wirings are shown by lines for convenience. However, the wiring is arranged as in FIG. 1 and the signal is transmitted to the circuit connected to the wiring through the contact hole.

Also in the third embodiment configured as described above, a plurality of word lines 41 and 43 (or
42 and 44) with partial spare row decoder 11 (or 12)
, The layout area of the spare row decoder 10 can be reduced.

In addition, the same spare word line drive signal SWD0
(Or SWD1) spare word lines 41 and 43
Since (or 42 and 44) are collectively arranged adjacent to each other, it is possible to increase the repair rate of the defective portion by the redundant circuit, thereby improving the yield.

Furthermore, since it is not necessary to physically cross the word lines, it is possible to reduce defects such as those caused by physically crossing the word lines. Note that the third embodiment
As described above, the replacement of the four spare word lines with the set in the second embodiment can be logically crossed without physically crossing the spare word lines.

[0039]

As described above, according to the present invention, the spare word lines are crossed so that a plurality of spare word lines corresponding to the same spare word line drive signal are located in a group. Even if a defect occurs in the line, the probability of using the spare word line is increased, the yield rate of the memory in mass production is improved, and the productivity of the memory can be increased.

[Brief description of the drawings]

FIG. 1 is a circuit diagram of a redundant circuit according to a first embodiment of the present invention.

FIG. 2 is a diagram showing a defect relief state of the redundant circuit according to the first embodiment of the present invention.

FIG. 3 is a block diagram of a redundant circuit according to a second embodiment of the present invention.

FIG. 4 is a circuit diagram of a spare row decoder in a redundant circuit according to a second embodiment of the present invention.

FIG. 5 is a circuit diagram of a spare word driver in a redundant circuit according to a second embodiment of the present invention.

FIG. 6 is a circuit diagram of a redundant circuit according to a second embodiment of the present invention.

FIG. 7 is a circuit diagram of a conventional redundant circuit.

FIG. 8 is a diagram showing an example of a spare word line defect.

FIG. 9 is a diagram showing a defect relief state of a conventional redundant circuit.

[Explanation of symbols]

10 Spare row decoder, 11-16 Partial spare row decoder 31-38 Spare word driver, 41-48 Spare word line

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Yasuhiko Tsukikawa 2-3-3 Marunouchi, Chiyoda-ku, Tokyo Sanryo Electric Co., Ltd.

Claims (1)

[Claims] 1. A spare word line having a plurality of sets of spare word lines, and spare word lines belonging to the same set are grouped and adjacent to each other, and one decoder in each set corresponds to one.
A plurality of word drivers for driving one word line are connected, and the word driver receives the corresponding decode signal and the spare word line drive signal corresponding to each set to drive the word line, and the spare word in the same set. In a semiconductor memory device having a decoder that receives a part of a row address for selecting one of the lines and outputs a decode signal, a wiring between a word driver and a spare word line in a memory cell is addressed. Semiconductor device in which spare word lines are crossed so that spare word lines corresponding to fuses for the fuse are located together.