JPH09120993A - Wiring of integrated circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To conduct a plurality of wirings specified at a time in a desired wiring region in a short time by setting a schematic wiring lattice pattern and a schematic wiring region and specifying a selective wiring forbidden region and checking all the selective wirings for the possiblity of execution of wiring and then conducting a schematic wiring. SOLUTION: A pattern of a schematic wiring lattice 20 and a schematic wiring region 23 are set and displayed. Nextly, a plurality of wirings 26 which will be targets of execution of wiring are selected as selective wirings. And, macro cells 19 which are a silective wiring forbidden region are specified. Then, all the selective wirings 26 are checked for a possiblity of execution of wiring. After that, a schematic wiring 28 is conducted. Thus, a wiring region and a wiring forbidden region are set for a plurality of specified wirings and then the schematic wiring 28 which is constituted of a plurality of the specified wirings is executed. By this method, wiring can be done with such a region that may exist on the way through a wiring path and be difficult to wire being kept away and the time required for correcting the wiring can be shortened accordingly as the number of the specified wirings increases.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an integrated circuit wiring method, and more particularly to an integrated circuit wiring method for performing automatic wiring design by CAD.

[0002]

2. Description of the Related Art In automatic wiring design of a semiconductor integrated circuit (hereinafter referred to as LSI), a standard cell or a macro cell whose layout is designed in advance is used to arrange a cell on a semiconductor substrate and between terminals of the cell according to a preset wiring rule. Wiring etc.

Here, a standard cell is a functional block such as an AND gate, an OR gate, and a flip-flop (FF) designed in advance, registered in a library, arranged in rows, and channels between the rows are used. It is a unit function cell of a standard cell type custom LSI that is wired in the same manner, and basically has almost the same height. A macro cell is a combination of functional blocks such as an AND gate, an OR gate, and a flip-flop (FF) to which a wiring pattern is added to realize a higher-level logical function block. It is designed in advance and registered in the library together with logic function and electrical characteristic data. In the layout design, the arrangement of these macro cells is optimally determined and mutual wiring is performed within the allowed area.

However, in an actual circuit, it is difficult to set all the wiring conditions such as the shapes of blocks and macro cells, the terminal positions, and the wiring areas so as to meet the above wiring rules. There is unwiring that is determined to be unwiring due to non-compliance with the wiring rules. It is necessary for the designer to interactively correct the non-wiring generated after the completion of the automatic wiring while referring to the existing wiring information, the wiring prohibition information and the like.

A conventional integrated circuit wiring method disclosed in Japanese Patent Laid-Open No. 4-148551, which is an example of this kind of interactive wiring correction method, is a wiring information storage means, wiring information display means, and wiring prohibition information display. It has a means, an unwired information display means, a wireable channel display means, a wiring correction execution means, and a correction result display means.

Next, the operation of the conventional integrated circuit wiring method will be described with reference to FIG. 3, which is an explanatory view showing an example of a CRT image displaying the wiring layout of the conventional wiring method. First, (A) The existing wiring information 1, the wiring prohibition information 2, the non-wiring information 3, and the placement prohibition information 9 are displayed on the display screen after the automatic wiring and before the correction shown in FIG.

The designer finds a wiring path connecting the function block 4 in the circuit and the terminal 7 of the function block 5 from the display information, and uses a coordinate input device such as a mouse to determine a predetermined vertical and horizontal directions. The positioning and the wiring layer are set so as to pass over the wiring grid 6. When the wiring passage positions are not determined on the vertical and horizontal wiring lattices 6 during the above positioning, the wiring passage positions are determined on the closest wiring lattice. Also, if the passing coordinates of the wiring exist on the placement prohibition 9 at the time of positioning, these coordinates are not recognized as the wiring passing coordinates. After the coordinates are input from the input device as shown in FIG. 3B, if the wiring 8 between the blocks is completed, this wiring correction is completed.

In this conventional wiring method, only one wiring can be handled by one wiring modification, and after the modification, the wiring route and the wiring layer are uniquely determined by the user. However, since the wiring area is preferentially used for execution of this automatic wiring in the area where automatic wiring is performed, the remaining wirable area for the above correction is limited to a very small area.

Referring to FIG. 4, which is an explanatory diagram showing an example of a CRT image after automatic wiring, as shown in FIG. 4A, the corrected terminal 11 passing only through the wirable area for correction. , 12 is extremely long as compared with the shortest wiring 14 which cannot be wired, and in the worst case, wiring is impossible. Further, as shown in FIG. 4B, in the macro cell 15 having a high internal wiring density, since the wiring area in the macro cell is almost consumed, it is necessary to avoid external wiring having a high possibility of passage. . In this case, even if an attempt is made to avoid the macro cell 15 and make a connection wiring between the macro cells 16 and 17, there is no detour path, so that an unwiring 18 is generated.

[0010]

In the conventional wiring method for the integrated circuit described above, since the wiring area is preferentially used for the execution of this automatic wiring in the automatic wiring execution area, it is necessary to correct the remaining correction. The wirable area is very small and limited,
There is a drawback that the wiring path passing only through the correction writable area becomes extremely long, and in the worst case, wiring is impossible.

Further, the connection wiring between a plurality of macro cells arranged to sandwich macro cells having a high wiring density, which needs to avoid an external wiring having a high possibility of passing, has an unrouted portion because there is no appropriate detour path. There was a drawback that it would end up.

Further, since there is no method for collectively correcting the wiring after the completion of the automatic wiring, it is necessary to interactively correct each wiring, which takes a lot of time.

[0013]

According to an integrated circuit wiring method of the present invention, a macro cell composed of a set of a plurality of circuit elements or functional circuit blocks previously formed on a semiconductor chip is arranged in a predetermined area and is predetermined. In the wiring method of the integrated circuit, the automatic wiring is performed according to the design information of the design target circuit on the wiring grid pattern which is the wiring route candidate in the vertical and horizontal directions set at the first wiring pitch, and the predetermined wiring pattern is generated. A first step of displaying the macro cells in a state where all the macro cells are arranged, a schematic wiring grid pattern of a second pitch for a plurality of predetermined wirings of the first pitch, and a schematic shown by the general wiring grid pattern The second step of setting and displaying the wiring area,
A third step of selecting a plurality of wirings to be controlled for wiring execution as selected wirings, a fourth step of designating a selected wiring prohibited area which is an area in which the wiring execution of the selected wirings is prohibited, A fifth step of checking whether or not it is possible to execute wiring of all wirings, and a sixth step of performing rough wiring to perform wiring on the rough wiring grid pattern with all wirings of the selected wiring as one unit, A seventh step of storing the selected wiring prohibited area, an eighth step of roughly wiring all wirings other than the selected wiring, and a wiring execution of all wirings including the selected wirings on the wiring grid pattern. And the ninth step of performing detailed wiring.

[0014]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, referring to FIG. 1 which is a flow chart showing an embodiment of the present invention, a wiring method of an integrated circuit of the present embodiment shown in this drawing shows a state in which all blocks and macro cells are arranged. In step S1 of displaying a macro cell, step S2 of displaying a block, step S3 of displaying a schematic wiring grid and a schematic wiring area for wiring on this schematic wiring grid, and selecting a plurality of wirings to be modified and controlled. Step S4, step S5 of designating a wiring prohibited area for the selected wiring, step S6 of checking the wiring prohibited area of the selected wiring, step S7 of storing the wiring prohibited area, and a schematic wiring for a specific wiring. Step S8 for performing the wiring, step S9 for performing the general wiring for the wiring of the entire circuit, and all the detailed wiring for the entire circuit are performed. And a step S10.

Next, the operation of the present embodiment will be described with reference to FIG. 1. First, in steps S1 and S2, together with a schematic wiring grid, which is a grid in which a plurality of grids of macrocells and blocks are set as one unit. It is displayed on a display device such as a CRT. The designer can see the information displayed on the CRT and input information such as coordinate information using an input device such as a mouse.

In the present embodiment, the wiring in the prediction area where the wiring becomes impossible due to the congestion of the wiring is prohibited. The wiring prohibited area specified here is valid only for a specific wiring, that is, a selected wiring.

First, the designer selects a plurality of wirings between a plurality of macro cells, between a macro cell and a block, or between a plurality of blocks as selection wirings in step S4.
Next, in step S5, the designer creates an area in which wiring is prohibited only for a plurality of the selected wirings, that is, a selected wiring prohibited area, by using an input device such as a mouse, in units of rough wiring grids. In this wiring prohibited area, wiring execution is prohibited for all the selected wirings specified in step S4.

Here, if the already-specified selected wiring has detailed wiring information, it is deleted in a step of deleting the detailed wiring information (not shown).

If the terminals of the macro cell or block to which the selected wiring belongs are present in the same area as the wiring prohibited area, or if the wirable areas between the macro cells or blocks are all used, the wiring becomes impossible. Therefore, step S
It is checked in 6 that the selected wiring prohibited area does not occupy the wiring planned area of the selected wiring, and it is confirmed that all the selected wirings can be wired. If it is determined in step S6 that wiring is not possible, the process returns to the first steps S1 to S3 to perform processing such as reducing the pitch of the rough grid, that is, the number of wirings, and displaying again on the CRT display device, and re-executing the processing To do. When it is determined that wiring is possible, this wiring prohibited area is saved as a wiring prohibition information file F1 only for the selected wiring in a storage device such as an IC memory or a magnetic disk in step S7. Further, when wiring prohibition information is created for another plurality of selected wirings, the process returns to steps S1 to S3 again, and the same processing is performed. When the setting of the wiring prohibition information for the specific plurality of selected wirings set several times is completed, all are added to the wiring prohibition information file F1 in step S7.

In step S8, the contents of the wiring prohibition information file F1 for the selected wiring set up to now are read,
Approximate wiring for the selected wiring is executed for the set number of times. Finally, the rough wiring for the remaining wiring of the entire circuit is executed in step S9, and all the detailed wiring for the entire circuit is performed in step S10 to create the final wiring information file F2.

Next, referring to FIG. 2 which is an explanatory view showing an example of a CRT image displaying a wiring layout according to the wiring method of the present embodiment, first, a schematic wiring area after steps S1 to S3 is executed is shown. In FIG. 2 (A), a macro cell 19 having a high wiring density, a schematic wiring grid 20, and
Macro cells 21 and 22 which are located on both sides of the macro cell and are planned to be interconnected with each other, a schematic wiring area 23 set by a designer, terminals 24 and 25, and a wiring connection display 27 are displayed. In addition, detailed wiring (step S1
In FIG. 2B showing the wiring area after 1), in addition to the macrocells 19, 21 and 22 and the terminals 24 and 25, the wiring 26 after the detailed wiring actually executed is displayed on the display screen.

Since there are more internal wirings on the macro cell 19 having a high wiring density as compared with the macro cells having a low wiring density, the wiring grid that can be used for correction is very small. Therefore, it becomes impossible to wire other wires that pass over the macro cell 19. The interconnection between the macro cells 21 and 22 on both sides of the macro cell 19 is performed on the macro cell 19 because the automatic interconnection program tries to execute the interconnection on the shortest path unless the designer performs any operation on the interconnection. Wiring becomes impossible.

In the present embodiment, the wiring execution is controlled using the general wiring grid 20 set in step S3. The general wiring grid 20 is generally used in order to automatically determine the general wiring positions of a plurality of selected wirings before the wiring, and specifies the wiring grid in units of several lines. An area surrounded by the rough wiring grid 20 for designating the rough wiring area 23 is used as a control unit.

The designer designates macros 21 and 22 to be interconnected by an input device such as a mouse (hereinafter referred to as a mouse) in order to select a macro cell for determining a rough interconnect route. Further, the macro cell 19 of the high-density internal wiring is designated as the wiring prohibited area (step S5). Terminal 2 that has a mutual connection relationship in the specified macro cells 21, 22
A connection display 27 of a plurality of wirings (selection wirings) showing a connection relationship is displayed on the CRT between 4 and 25. The designer inputs the general wiring area 23 surrounded by the general wiring grid 20 from the positions of the terminals 24 and 25 and the wiring connection display 27 with a mouse. After the input, when the number of wiring grids existing in the designated general wiring area 23 is smaller than the total number of the selected wirings, the width W of the area 23 is increased and the general wiring area 2
3 is set (steps S6 and S7).

Next, after determining the general wiring area 23 between the macros 21 and 22, the general wiring position 28 is preferentially determined within the general wiring area 23 only between the macros 21 and 22. Next, the general wiring positions 28 of the macros 21 and 22 are fixed and the general wiring positions and the detailed wiring positions 26 of the entire circuit are determined (step S8).

In the present embodiment, unlike the conventional wiring method, the designer performs automatic wiring in the rough wiring area 23 after designating the rough positions of a plurality of wirings to be connected, that is, selected wirings. Therefore, the correction time can be shortened as compared with the conventional method by a plurality of parts constituting the specified selection wiring. Further, before executing the automatic wiring, if this wiring correction is used, it is possible to execute the designated wiring while avoiding the wiring area which is predicted to be crowded in advance.

Compared with the conventional method, in the present embodiment, it is possible to modify a plurality of wirings at once, and the wiring itself also has a step of performing a rough wiring and a detailed wiring for a specific wiring. Since the automatic wiring is performed by the steps, it is excellent in that it can be corrected in a relatively short time.

Further, in the conventional method, a route is found between the high-density wiring patterns after the automatic wiring and the wirings to be corrected are combined, but in the present embodiment, the macro cell is completed even before the completion of all the wirings. It is excellent in that wiring can be performed if all blocks and blocks are arranged, and that wiring can be performed ahead of time in a region where wiring is likely to be crowded.

[0029]

As described above, the integrated circuit wiring method of the present invention includes the steps of setting and displaying a rough wiring grid pattern and a rough wiring area, and selecting a plurality of wirings to be controlled for wiring execution. , A step of designating a selected wiring prohibited area, a step of checking the possibility of executing wiring of all the wirings of the selected wiring,
By including the step of performing rough wiring, it is possible to set a wiring target area or a wiring prohibited area for a plurality of designated wirings and execute rough wiring consisting of the plurality of designated wirings. There is an effect that it is possible to avoid the difficult area of the wiring existing in the wiring, and to shorten the wiring correction time by the number of the designated wirings.

[Brief description of the drawings]

FIG. 1 is a flowchart showing an embodiment of an integrated circuit wiring method of the present invention.

FIG. 2 is an explanatory diagram showing an example of a display screen of a display device in the integrated circuit wiring method of the present embodiment.

FIG. 3 is an explanatory diagram showing an example of a display screen of a display device in a conventional integrated circuit wiring method.

FIG. 4 is an explanatory diagram showing a case where wiring is not possible in a conventional wiring method for an integrated circuit.

[Explanation of symbols]

 1 Wiring information 2 Wiring prohibition information 3 Unwiring information 4, 5 Functional block 6 Wiring grid 7, 11, 12, 24, 25 Terminals 8, 10, 26 Wiring 9 Placement prohibition information 13, 14 Wiring route 15-17, 19 , 21,22 Macrocell 18 Unwired 20 General wiring grid 23 General wiring area 27 Wiring connection display 28 General wiring position

Claims (2)

[Claims] 1. A vertical and horizontal direction in which macrocells each consisting of a set of a plurality of circuit elements or functional circuit blocks formed in advance on a semiconductor chip are arranged in a predetermined region and set at a predetermined first wiring pitch. In a wiring method of an integrated circuit, which automatically performs wiring according to design information of a circuit to be designed on a wiring grid pattern which is a wiring route candidate to generate a predetermined wiring pattern, displaying the macro cell in a state where all the macro cells are arranged. A first step, a second step of setting and displaying a schematic wiring grid pattern of a second pitch for a plurality of predetermined wirings of the first pitch, and a schematic wiring area shown by the general wiring grid pattern; A third step of selecting a plurality of wirings to be controlled as executions as a selection wiring, and an area for prohibiting the wiring execution of the selection wirings. A fourth step of designating a certain selected wiring prohibited area, a fifth step of checking whether or not it is possible to execute the wiring of all the selected wirings, and the above-mentioned outline with all the wirings of the selected wiring as one unit. A sixth step of performing rough wiring for performing wiring on a wiring grid pattern, a seventh step of storing the selected wiring prohibited area, and an eighth step of roughly wiring all wirings other than the selected wiring.
And a ninth step of performing detailed wiring for executing all wiring including the selected wiring on the wiring grid pattern. 2. The wiring method for an integrated circuit according to claim 1, wherein the wiring execution priority of the selected wiring is given in a specific area.