JPH09116431A - Pll circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent the radiation of high frequency noise in an unstable state when power is supplied by holding a phase comparison output signal so that VCO output frequency becomes low for a while after power is supplied by means of a power-on reset signal and the like. SOLUTION: The power-on reset signal is given for a while after power is supplied as the control signal Vc of a phase comparator PD. When the control signal Vc is active, phase difference signals Vn and Vp are continued to be outputted in a direction where the frequency of the output signal fout of a voltage control oscillator VCO becomes the lowest. A signal outputted by the judgment of a microcomputer is used as the control signal Vc . In such a case, the VCO output signal fout is kept to be the lowest even if the reference signal Vs is lacked. Thus, the wasteful power consumption of a servo control system and a system control system, which input the output signals of a PLL circuit, can be reduced.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a PLL (phase locked loop) circuit composed of voltage / frequency conversion means such as a VCO, a phase difference detector, a low-pass filter and the like.

[0002]

2. Description of the Related Art Generally, a PLL circuit is used to obtain another signal synchronized with a reference signal. This PLL circuit has, as a basic configuration, a VCO (voltage controlled oscillator) that generates a signal synchronized with the reference signal Vs, a PD (phase detector: phase difference detector) that outputs a phase difference between two signals, and a position. An LPF (low-pass filter: low-pass filter) for removing a high-frequency component of the output of the phase difference detector PD is provided. In this PLL circuit, the phase difference between the output signal of the voltage controlled oscillator VCO and the reference signal Vs is detected by the phase difference detector PD, and the detected signal is input to the voltage controlled oscillator VCO through the low pass filter LPF. By doing so, feedback is applied and the phases of the two signals (VCO output signal and reference signal Vs) are synchronized.

[0003]

The first problem is the PLL.
In the circuit, the frequency of the output signal of the voltage controlled oscillator VCO is indefinite because it does not become stable for a while after the power is turned on, and in many cases, the voltage controlled oscillator VCO is not stable.
Is outputting the maximum frequency that can be output. for that reason,
Not only the operation such as initial setting of other circuits is adversely affected, but also high frequency is emitted as radio noise, which disturbs the image and sound of the television receiver, radio receiver, etc. . According to the present invention, such an inconvenience is eliminated, and high-frequency noise is prevented from being radiated even in an unstable state when the power is turned on (PLLs of claim 1, claim 6, claim 8 and claim 10). circuit).

As a second problem, since the voltage controlled oscillator VCO of the PLL circuit constantly oscillates, power is consumed not only in the VCO section but also in the circuit to which a signal is supplied from this VCO section. . On the other hand, with the downsizing of electronic devices, heat generation and the like have become a problem not only for saving power consumption but also for stable operation. In the present invention,
In a state in which a signal from the voltage controlled oscillator VCO is not required (standby state, etc.), the signal from the VCO unit is reduced to reduce power consumption and take measures against heat generation (claims 2, 7 and 7). 9. The PLL circuit according to claim 11.

As a third problem, the voltage controlled oscillator VCO
If the oscillating frequency is set to a low frequency, it takes time to set the lock state, and this loss time may adversely affect the operation depending on the system.
In the present invention, the free-running frequency of the voltage controlled oscillator VCO is
The adverse effect is avoided by setting the optimum value (PLL circuits according to claims 3 and 4).

As a fourth problem, depending on the system,
A situation occurs in which the reference signal Vs is lost for a short time or for a long time. In such a state, the voltage controlled oscillator VCO oscillates at the maximum or minimum frequency, and the reference signal Vs is input again. When I first started, it took a long time to lock. In the present invention, the adverse effect caused by the lack of the reference signal Vs of the voltage controlled oscillator VCO is avoided (PLL circuit of claim 5).

[0007]

According to a first aspect of the present invention, a VCO or other voltage / frequency conversion means in which the frequency of an output signal changes according to the voltage value of an input signal, and the output signal is output to an external circuit. In addition, the phase comparison signal Vs that is phase-compared with the reference signal Vs to be synchronized and can also be controlled by the control signal Vc from the outside.
Phase difference detector that outputs n and Vp, and phase comparison signal V
Controlled by n and Vp, a certain voltage value V
(H) or V (L) output, or a charge pump that has the function of making the output high impedance and a frequency characteristic that stabilizes the circuit loop, and removes the high frequency component of the output signal of the charge pump And a low-pass filter for outputting as an input signal of the voltage / frequency conversion means, the control signal Vc is a power-on reset signal, and the frequency of the output signal of the voltage / frequency conversion means is maintained for a while after power-on. In this configuration, the phase comparison signal Vn or Vp is continuously output so as to decrease.

According to a second aspect of the present invention, in the PLL circuit of the first aspect, the control signal Vc is a signal controlled by a microcomputer instead of the power-on reset signal, and the external circuit is a voltage / frequency conversion means. When the output signal is not required, the control signal Vc is controlled by the microcomputer to continuously output the phase comparison signal Vn or Vp so that the frequency of the output signal of the voltage / frequency conversion means becomes low.

According to the third aspect of the present invention, the frequency of the output signal changes according to the voltage value of the input signal, and when the input voltage is the same as the reference voltage Vref, the frequency is adjusted to be near the target frequency. VCO or other voltage / frequency conversion means for generating a signal and an output signal are output to an external circuit, and a phase comparison is performed with a reference signal Vs to be synchronized, and control is performed by a control signal Vc from the outside. A phase difference detector that outputs possible phase comparison signals Vn and Vp and a certain voltage value V (H) or V (L) that is controlled by the phase comparison signals Vn and Vp, or the output is high impedance. It has a frequency characteristic that stabilizes the circuit and the charge pump that has the function to stabilize the voltage / frequency by removing the high frequency component of the output signal of the charge pump. The control signal Vc is a power-on reset signal, which is output as an input signal of the conversion means and which is an active filter. The control signal Vc is a power-on reset signal. Both the phase comparison signals Vn and Vp are deactivated so that the frequency is close to the target frequency, and the output of the charge pump becomes high impedance, so that the output of the low-pass filter, which is an active filter, changes to the reference voltage. It has the same configuration as Vref.

According to a fourth aspect of the present invention, in the PLL circuit of the third aspect, the control signal Vc is a signal controlled by a microcomputer instead of the power-on reset signal, and the external circuit is a voltage / frequency conversion means. When the output signal is not required, the control signal Vc is controlled by the microcomputer so that both the phase comparison signals Vn and Vp are inactive so that the frequency of the output signal of the voltage / frequency conversion means becomes close to the target frequency. And the output of the charge pump becomes high impedance, so that the output of the low-pass filter that is an active filter becomes equivalent to the reference voltage Vref.

According to a fifth aspect of the present invention, in the PLL circuit of the third aspect, the control signal Vc is a reference signal missing detection signal from an external circuit instead of the power-on reset signal, and when the reference signal is missing. , The phase comparison signals Vn and Vp both become inactive and the output of the charge pump becomes high impedance so that the frequency of the output signal of the voltage / frequency conversion means becomes close to the target frequency. The output of a certain low-pass filter is equivalent to the reference voltage Vref.

According to a sixth aspect of the present invention, a VCO or other voltage / frequency conversion means in which the frequency of the output signal changes according to the voltage value of the input signal, and the output signal is output to an external circuit and is synchronized. A phase difference detector that performs phase comparison with the reference signal Vs, which is a target, and outputs phase comparison signals Vn and Vp, and a certain voltage value V (H) or V (L) controlled by the phase comparison signals Vn and Vp. Has a frequency characteristic that stabilizes the circuit loop and a charge pump that outputs or outputs high impedance, removes the high frequency component of the output signal of the charge pump, and removes the high frequency component. The control signal Vc is a power-on reset signal, and the control signal Vc is a power-on reset signal.
For a while after the power is turned on, the output voltage of the low-pass filter is largely biased toward the high or low direction so that the frequency of the output signal of the voltage / frequency conversion means becomes low.

According to a seventh aspect of the present invention, in the PLL circuit according to the sixth aspect, the control signal Vc is a signal controlled by a microcomputer instead of the power-on reset signal, and the external circuit is a voltage / frequency conversion means. When the output signal is not required, the control signal Vc is controlled by the microcomputer so that the output voltage of the low-pass filter becomes higher or lower so that the frequency of the output signal of the voltage / frequency conversion means becomes close to the target frequency. It is a configuration that is largely offset in the direction.

According to an eighth aspect of the present invention, there is provided a VCO or other voltage / frequency conversion means in which the frequency of the output signal changes in accordance with the voltage value of the first input signal and the voltage value of the second input signal. , The output signal is output to an external circuit, and is controlled by a phase difference detector that performs phase comparison with the reference signal Vs to be synchronized and outputs phase comparison signals Vn and Vp, and phase comparison signals Vn and Vp. Output voltage of V (H) or V (L), or a charge pump having a function of making the output high impedance, and a frequency characteristic for stabilizing a circuit loop, and an output signal of the charge pump. And a low-pass filter that outputs the signal from which the high-frequency component has been removed as a first input signal of the voltage / frequency conversion means, and a second low-pass filter of the voltage / frequency conversion means. A control signal Vc from the outside is input as an input signal, and the control signal Vc is a power-on reset signal. For a while after power-on, the frequency of the output signal of the voltage / frequency conversion means is The voltage / frequency conversion means is controlled so as to lower the voltage.

According to a ninth aspect of the invention, in the PLL circuit of the eighth aspect, the control signal Vc is a signal controlled by a microcomputer instead of the power-on reset signal, and the external circuit is a voltage / frequency conversion means. When the output signal is not required, the microcomputer controls the control signal Vc to control the voltage / frequency conversion means so that the frequency of the output signal of the voltage / frequency conversion means becomes low.

According to a tenth aspect of the invention, a VCO having an oscillation function is provided, which has a first input for changing the frequency of the output signal according to the voltage value of the input signal and a second input for stopping the oscillation. The other voltage / frequency conversion means and the output signal are output to the external circuit, and the phase comparison signals Vn and Vp are performed by performing the phase comparison with the reference signal Vs which is a synchronization target.
Is controlled by the phase difference detector Vn and Vp, which outputs a voltage value V (H) or V
(L) is output, or the charge pump has the function of making the output high impedance and the frequency characteristic that stabilizes the circuit loop. The high frequency component of the output signal of the charge pump is removed and the voltage / A low-pass filter for outputting as a first input signal of the frequency conversion means,
A control signal Vc from the outside is input as the second input signal of the frequency conversion means, and the control signal Vc is a power-on reset signal.
For a while after the power is turned on, the oscillation of the voltage / frequency conversion means is stopped.

The invention of claim 11 is the PLL of claim 10.
In the circuit, the control signal Vc is a signal controlled by the microcomputer instead of the power-on reset signal, and when the external circuit does not require the output signal of the voltage / frequency conversion means, the control signal Vc is controlled by the microcomputer. Is controlled to stop the oscillation of the voltage / frequency conversion means.

[0018]

BEST MODE FOR CARRYING OUT THE INVENTION

First Embodiment The first embodiment corresponds to the inventions of claims 1 and 2. In the first embodiment, the phase difference detector PD is controlled by the power-on reset signal (invention of claim 1) or the control signal Vc from the microcomputer (invention of claim 2) to control the VCO.
The frequency of the output signal fout of the (voltage controlled oscillator) is lowered. The configuration and operation of the PLL circuit is shown in FIG.
It will be explained by.

FIG. 1 shows a PLL circuit according to the present invention.
It is a functional block diagram showing an example of an embodiment of the main part composition. In the figure, VCO is a voltage controlled oscillator, PD is a phase comparator (phase detector), LPF is a low pass filter (low pass filter), CP is a charge pump, Vs is a reference signal, and Vc is a control signal. ,
fout is the output signal of the voltage controlled oscillator VCO, Vp and Vn
Is the phase comparison signal, V (H) is the maximum voltage that the charge pump CP can output, and V (L) is the minimum voltage.

In the PLL circuit shown in FIG. 1, the phase comparator PD performs a phase comparison between the output signal fout of the voltage controlled oscillator VCO and the reference signal Vs, and two phase comparison signals Vout.
Outputs p and Vn. In normal operation, the charge pump CP is supplied by these two phase comparison signals Vp and Vn.
Is controlled, and its output signal is a low-pass filter L.
It is input to the voltage controlled oscillator VCO via PF. Therefore, the output signal fout of the voltage controlled oscillator VCO is controlled so as to be locked to the reference signal Vs.

In this case, when the power-on reset signal is applied as the control signal Vc of the phase comparator PD (invention of claim 1), when the power-on reset signal is active, the output signal fout of the voltage controlled oscillator VCO.
The phase difference signal is output in the direction in which the frequency becomes lowest. For example, the output of the low pass filter LPF is
Assuming that the frequency is the lowest at the maximum voltage V (H) of the pump CP, one phase comparison signal Vn from the phase comparator PD
Is "H", and the other phase comparison signal Vp is "L".

On the contrary, the minimum voltage V of the charge pump CP
If it is the lowest frequency at (L), the phase comparator PD
One of the phase comparison signals Vn is “L” and the other phase comparison signal Vp is “H”. As described above, by using the power-on reset signal as the control signal Vc of the phase comparator PD, it is possible to prevent the emission of high frequency noise even in an unstable state when the power is turned on (the invention of claim 1). .

If a signal output from a port of a microcomputer is used as the control signal Vc of the phase comparator PD, the frequency of the output signal fout of the voltage controlled oscillator VCO is set to the lowest frequency according to the judgment of the microcomputer. It is also possible (the invention of claim 2). Generally, the PLL circuit is used for a servo control system, system control, etc., and these controls are performed by a microcomputer. Therefore, the control signal Vc for the operation of the PLL circuit can be extremely easily generated. Thus, if the control signal Vc from the microcomputer is used, the reference signal Vc
The disadvantage of radiating high frequency noise due to the VCO generating an abnormal frequency in a mode where s disappears is avoided by the control of the microcomputer. Moreover, since wasteful consumption of electric power is reduced, it is effective as a measure against heat generation.

Second Embodiment The second embodiment corresponds to the inventions of claims 3 to 5. In the second embodiment, a phase difference is caused by a power-on reset signal (invention of claim 3), a control signal Vc from the microcomputer (invention of claim 4) or a reference signal missing detection signal (invention of claim 5). The detector PD is controlled so that the free-running frequency of the output signal fout of the VCO is near the target frequency. The configuration and operation of the PLL circuit will be described with reference to FIG.

FIG. 2 shows a PLL circuit of the present invention.
It is a functional block diagram which shows an example of 2nd Embodiment.
Reference numerals in the figure are the same as those in FIG. 1, OP represents an operational amplifier, and Vref represents its reference voltage.

The PLL circuit shown in FIG. 2 has the same basic configuration as that of FIG. 1, but the low pass filter LPF is
It is characterized in that it is an active filter composed of an operational amplifier OP. The voltage controlled oscillator VCO
When the same voltage as the reference voltage Vref of the operational amplifier OP is input to the voltage controlled oscillator VCO,
The voltage-controlled oscillator VCO adjusts the frequency to be the same as or near the frequency at the time of lock.

Also in this case, when the power-on reset signal is applied as the control signal Vc of the phase comparator PD (invention of claim 3), when the power-on reset signal is active, the phase comparator PD outputs 2 signals. When the two phase comparison signals Vp and Vn become inactive, the output end of the charge pump CP becomes high impedance. Then, the low-pass filter L which is an active filter
In PF, the input becomes high impedance,
The reference voltage Vref of the operational amplifier OP is output.

When the input is the reference voltage Vref, the voltage controlled oscillator VCO outputs a signal having a frequency near the target frequency. Therefore, the output signal fout of the voltage controlled oscillator VCO is kept at the target frequency for a while after power-on. Can be fixed. As a result, it is possible to prevent a situation in which high frequency noise is radiated due to the VCO generating an abnormal frequency in an unstable state when the power is turned on.

If the signal output from the port of the microcomputer is used as the control signal Vc of the phase comparator PD, the frequency of the output signal fout of the voltage controlled oscillator VCO is determined to be near the target frequency according to the judgment of the microcomputer. Can be fixed to (the invention of claim 4). Also in this case, as in the PLL circuit of claim 2, there is a problem that the VCO generates an abnormal frequency and emits high frequency noise in a mode in which the reference signal Vs disappears. Control, and wasteful consumption of electric power can be reduced, which is also effective for problems such as heat generation.

Further, as the control signal Vc, a missing detection circuit for the reference signal Vs is provided, and the detection signal from this missing detection circuit is used. According to the detection signal generated when the reference signal Vs is missing for a certain time due to some cause, Even if the phase comparator PD controls, similarly, the frequency of the output signal fout of the voltage controlled oscillator VCO can be fixed near the target frequency (the invention of claim 5). With this configuration, it is possible to avoid a situation where the VCO generates an abnormal frequency and emits high-frequency noise when the reference signal Vs is missing for some reason. , Reference signal Vs
When is restored, the operation of the PLL can be quickly returned to a stable operation state.

Third Embodiment The third embodiment corresponds to the inventions of claims 6 and 7. Also in the third embodiment, the basic PLL circuit configuration is the same as that of the second embodiment shown in FIG. 2, but the control signal Vc is an active filter instead of the phase comparator PD. It is input to a certain low-pass filter LPF, and is characterized in that this low-pass filter LPF is added to the output of the charge pump CP. The control signal Vc input to the low pass filter LPF is a power-on reset signal (the invention of claim 6).
Alternatively, it is the control signal Vc from the microcomputer (the invention of claim 7) and is added to the output of the charge pump CP in the low pass filter LPF to lower the frequency of the output signal fout of the VCO. . The configuration and operation of the PLL circuit will be described with reference to FIG.

FIG. 3 shows a PLL circuit according to the present invention.
It is a functional block diagram which shows an example of 3rd Embodiment.
Reference numerals in the figure are the same as those in FIG.

The PLL circuit shown in FIG. 3 has the same basic configuration as that of FIG. 2, but the control signal Vc is
The low-pass filter LPF, which is an active filter, is input instead of the phase comparator PD, and the low-pass filter L
The difference between the PF and the output of the charge pump CP is the addition. Then, during the normal PLL operation, the control signal Vc outputs the power-on reset signal or the reference voltage Vref of the operational amplifier OP.

First, there is a case where a power-on reset signal (or a signal obtained by level-converting this signal) is used as the control signal Vc (the invention of claim 6). In this case, when the power-on reset signal is active, the control signal Vc is controlled by either the maximum voltage V (H) or the minimum voltage V (L) that the charge pump CP can output. Output signal f of oscillator VCO
It is the voltage that reduces the out frequency.

The output of the charge pump CP thus obtained and the control signal Vc are added in the low pass filter LPF. In this case, the control signal Vc has a larger addition ratio. As a result, the frequency of the output signal fout of the voltage controlled oscillator VCO is fixed at a frequency lower than the target frequency. Therefore, similarly to the PLL circuit of the first aspect, it is possible to prevent a situation in which high-frequency noise is radiated due to the VCO generating an abnormal frequency in an unstable state when the power is turned on.

Also in the case of FIG. 3, the control signal V
c is a signal output from a port of the microcomputer (or a signal obtained by level-converting the signal)
Is used, the control signal Vc is controlled by the judgment of the microcomputer, and the frequency of the output signal fout of the voltage controlled oscillator VCO can be fixed near the target frequency (the invention of claim 7). According to this structure, as in the PLL circuit according to claim 2 or 4, in the mode in which the reference signal Vs disappears,
The inconvenience that the VCO generates an abnormal frequency and emits high frequency noise is prevented by the control of the microcomputer. In addition, since wasteful consumption of electric power is reduced, it is effective as a measure against heat generation.

Fourth Embodiment The fourth embodiment corresponds to the inventions of claims 8 to 11. The fourth embodiment is also a basic PL
The configuration of the L circuit is the same as that of the first embodiment shown in FIG. 1, but the control signal Vc is the phase comparator PD.
Is connected to the second control input of the voltage controlled oscillator VCO instead of. The control signal Vc applied to the second control input of the voltage controlled oscillator VCO is a power-on reset signal (invention of claim 8) or a control signal Vc from a microcomputer (invention of claim 9).
By controlling the (voltage controlled oscillator), the frequency of the output signal fout of the VCO is lowered.

Further, the control signal Vc is the power-on reset signal (the invention of claim 10) or the control signal Vc from the microcomputer (claim 1).
0 invention), the VCO (voltage controlled oscillator) is controlled to stop the oscillation operation of the VCO. PL
The configuration and operation of the L circuit will be described with reference to FIG.

FIG. 4 shows the PLL circuit of the present invention.
It is a functional block diagram which shows an example of 4th Embodiment.
The reference numerals in the figure are the same as those in FIG.

The PLL circuit shown in FIG. 4 has the same basic configuration as that of FIG. 1, but the control signal Vc is
The difference is that it is connected to the second control input of the voltage controlled oscillator VCO. Also in this case, the power-on reset signal (or a signal obtained by level-converting this signal) can be used as the control signal Vc to be applied to the second control input of the voltage controlled oscillator VCO (the invention of claim 8).

Using this power-on reset signal, the voltage-controlled oscillator VCO has two states, that is, a normal operation state and a state in which the frequency of the output signal fout is fixed to a low frequency, by the second control input. Switching is possible, and when the power-on reset signal is active, the frequency of the output signal fout of the voltage controlled oscillator VCO is set to be fixed at a low frequency. With this configuration, the frequency of the output signal fout of the VCO can be controlled to be lowered. Therefore, as in the PLL circuit according to the first or sixth aspect, it is possible to prevent the situation where the VCO generates an abnormal frequency and radiates high frequency noise in an unstable state when the power is turned on.

If a signal output from a port of a microcomputer (or a signal obtained by level-converting the signal) is used as the control signal Vc to be applied to the second control input of the voltage controlled oscillator VCO, the control signal Vc will be The frequency of the output signal fout of the voltage controlled oscillator VCO can be fixed near the target frequency under the control of the microcomputer's judgment (the invention of claim 9). Also in this case, the voltage controlled oscillator VCO has the same configuration as that when the power-on reset signal is used.

With this structure, it is possible to control the frequency of the output signal fout of the VCO to be lowered. Therefore, like the PLL circuits of claim 2, claim 4, and claim 7, the VCO generates an abnormal frequency in a mode in which the reference signal Vs disappears.
The inconvenience of emitting high frequency noise is prevented by the control of the microcomputer.
In addition, since wasteful consumption of electric power can be reduced, it is also effective against problems such as heat generation.

Further, as the control signal Vc given to the second control input of the voltage controlled oscillator VCO,
The power-on reset signal is used, and the VCO is controlled by this power-on reset signal to stop the oscillation operation of the VCO (the invention of claim 10). This configuration is a modification of the PLL circuit of claim 8 described above, and in the PLL circuit of claim 8, the voltage controlled oscillator VC
The first and second control inputs of O control switching between a normal operation state and a state in which the frequency of the output signal fout is fixed at a low frequency.
The 0 PLL circuit is different in that it switches between a normal operation state and an operation stop (oscillation stop).

In this configuration, the operation of the voltage controlled oscillator VCO may be stopped (oscillation stopped) when the power-on reset signal is active. Therefore, as a measure for preventing the situation in which high frequency noise is radiated due to the VCO generating an abnormal frequency in an unstable state when the power is turned on, it is stronger than the PLL circuit according to claim 8. The effect is more remarkable. In addition, since wasteful consumption of electric power can be reduced, it is also effective against problems such as heat generation.

Also in the PLL circuit of claim 10,
As the control signal Vc, a signal controlled by a microcomputer can be used instead of the power-on reset signal (the invention of claim 11). Also in this case, the voltage controlled oscillator VCO has the same configuration as that when the power-on reset signal is used. With this configuration, the operation of the voltage controlled oscillator VCO can be stopped (oscillation stopped) according to the judgment of the microcomputer.

Therefore, in a mode in which the reference signal Vs disappears, the VCO generates an abnormal frequency,
As a measure for preventing the situation of radiating high frequency noise, it is more powerful than the PLL circuits of claim 2, claim 4, claim 7, and claim 9, and the effect is more remarkable. Moreover, wasteful consumption of electric power is reduced, which is effective as a measure against heat generation.

[0048]

In the PLL circuit according to the first aspect of the present invention, the phase difference detector PD is controlled by the power-on reset signal to lower the frequency of the output signal fout of the VCO (voltage controlled oscillator) and other voltage / frequency conversion means. I have to. Therefore, radiation of high frequency noise is prevented even in an unstable state when the power is turned on.

In the PLL circuit of the second aspect, the phase difference detector PD is controlled by the control signal Vc from the microcomputer, and the VCO (voltage controlled oscillator) is used.
The frequency of the output signal fout of other voltage / frequency conversion means (hereinafter, simply referred to as VCO) is lowered. Therefore, in a mode in which the reference signal Vs disappears, the VCO generates an abnormal frequency, which causes a problem that high frequency noise is radiated.
Avoided by microcomputer control. Further, since wasteful consumption of electric power is reduced, it is also effective as a measure against heat generation.

In the PLL circuit of the third aspect, the phase difference detector PD is controlled by the power-on reset signal so that the free-running frequency of the output signal fout of the VCO is near the target frequency (target frequency). Therefore, in an unstable state when the power is turned on, high frequency noise is radiated by the VCO generating an abnormal frequency,
That inconvenience is avoided.

In the PLL circuit of the fourth aspect, the phase difference detector PD is controlled by the control signal Vc from the microcomputer so that the free-running frequency of the output signal fout of the VCO is near the target frequency.
Therefore, similar to the PLL circuit of claim 2, the disadvantage of the VCO generating an abnormal frequency and radiating high frequency noise in a mode in which the reference signal Vs disappears is controlled by the microcomputer. To be prevented. In addition, since wasteful consumption of electric power can be reduced, it is also effective against problems such as heat generation.

In the PLL circuit of the fifth aspect, the phase difference detector PD is controlled by the reference signal missing detection signal so that the free-running frequency of the output signal fout of the VCO is near the target frequency. Therefore, when the reference signal Vs is missing for some reason, VC
A situation in which O generates an abnormal frequency and radiates high frequency noise is prevented, and when the reference signal Vs is restored, the operation of the PLL can be quickly returned to a stable operation state.

In the PLL circuit of the sixth aspect, the power-on reset signal and the output of the charge pump CP are added in the low pass filter LPF to lower the frequency of the output signal fout of the VCO. . Therefore, similarly to the PLL circuit of the first aspect, it is possible to prevent a situation in which high-frequency noise is radiated due to the VCO generating an abnormal frequency in an unstable state when the power is turned on.

In the PLL circuit of the seventh aspect, the control signal Vc from the microcomputer and the output of the charge pump CP are added in the low pass filter LPF to lower the frequency of the output signal fout of the VCO. I am trying. Therefore, similar to the PLL circuits of claims 2 and 4, in the mode where the reference signal Vs disappears, the VCO generates an abnormal frequency and radiates high frequency noise.
Prevented by microcomputer control. In addition, since wasteful consumption of electric power is reduced, it is effective as a measure against heat generation.

In the PLL circuit of the eighth aspect, the VCO is controlled by the power-on reset signal and the frequency of the output signal fout of the VCO is lowered. Therefore, as in the PLL circuit according to the first or sixth aspect, it is possible to prevent the situation where the VCO generates an abnormal frequency and radiates high frequency noise in an unstable state when the power is turned on.

According to the ninth aspect of the PLL circuit, the VCO is controlled by the control signal Vc from the microcomputer and the frequency of the output signal fout of the VCO is lowered. Therefore, like the PLL circuits of claims 2, 4, and 7, the VCO generates an abnormal frequency and emits high-frequency noise in a mode in which the reference signal Vs disappears. The inconvenience is prevented by the control of the microcomputer. In addition, since wasteful consumption of electric power can be reduced, it is also effective against problems such as heat generation.

According to a tenth aspect of the PLL circuit, the VCO is controlled by the power-on reset signal,
The oscillation operation of is stopped. Therefore,
In order to avoid a situation in which high frequency noise is radiated due to the VCO generating an abnormal frequency in an unstable state when the power is turned on, the P of claim 1, claim 6, or claim 8 is used.
This is more effective than the case where the LL circuit is adopted. And since it is possible to reduce the wasteful consumption of power,
It is also effective against problems such as fever.

According to the eleventh aspect of the present invention, in the PLL circuit, the VCO is supplied by the control signal Vc from the microcomputer.
Is controlled to stop the oscillation operation of the VCO. Therefore, in a mode where the reference signal Vs disappears, the VCO generates an abnormal frequency,
In order to avoid the situation that high frequency noise is radiated, the PLL of claim 2, claim 4, claim 7, or claim 9 is used.
It is more effective than when a circuit is adopted. In addition, since wasteful consumption of electric power is reduced, it is effective as a measure against heat generation.

[Brief description of the drawings]

FIG. 1 is a functional block diagram showing an example of an embodiment of a main part configuration of a PLL circuit of the present invention.

FIG. 2 is a functional block diagram showing an example of a second embodiment of the PLL circuit of the present invention.

FIG. 3 is a functional block diagram showing an example of a third embodiment of a PLL circuit of the present invention.

FIG. 4 is a functional block diagram showing an example of a fourth embodiment of the PLL circuit of the present invention.

[Explanation of symbols]

 VCO Voltage controlled oscillator PD Phase comparator LPF Low pass filter CP Charge pump OP Op amp

Claims (11)

[Claims] 1. A VCO or other voltage / frequency conversion means in which a frequency of an output signal changes according to a voltage value of an input signal, and a reference which is a target of synchronization while the output signal is output to an external circuit. A phase difference detector which performs phase comparison with the signal Vs and outputs phase comparison signals Vn and Vp which can be controlled by an external control signal Vc, and a voltage value controlled by the phase comparison signals Vn and Vp. A charge pump having a function of outputting V (H) or V (L) or having a high impedance output, and a frequency characteristic for stabilizing a circuit loop, and a high frequency component of an output signal of the charge pump. To remove the voltage /
The control signal Vc is a power-on reset signal, and the frequency of the output signal of the voltage / frequency conversion means is low for a while after power-on. As described above, a PLL (phase locked loop) circuit which continues to output the phase comparison signal Vn or Vp. 2. The PLL circuit according to claim 1, wherein the control signal Vc is a signal controlled by a microcomputer instead of the power-on reset signal, and an external circuit outputs the output signal of the voltage / frequency conversion means. When not required, the control signal Vc is controlled by a microcomputer, and the phase comparison signal Vn or Vp is continuously output so that the frequency of the output signal of the voltage / frequency conversion means becomes low. PLL circuit to do. 3. The frequency of the output signal changes according to the voltage value of the input signal, and when the input voltage is the same as the reference voltage Vref, a signal adjusted to be near the target frequency is generated. A VCO or other voltage / frequency conversion means, and a phase comparison in which the output signal is output to an external circuit and a phase comparison is performed with a reference signal Vs to be synchronized, and control is also possible by an external control signal Vc. A phase difference detector that outputs signals Vn and Vp, and a function that outputs a certain voltage value V (H) or V (L) or has a high impedance output by being controlled by the phase comparison signals Vn and Vp. And a charge pump having a frequency characteristic for stabilizing a circuit loop, removing a high frequency component of an output signal of the charge pump,
The control signal Vc is a power-on reset signal, which is output as an input signal of the frequency conversion means and which is an active filter, and the control signal Vc is a power-on reset signal. Both the phase comparison signals Vn and Vp are deactivated so that the frequency of the output signal is near the target frequency, and the output of the charge pump becomes high impedance, so that the low-pass filter that is an active filter is A PLL circuit having an output equal to the reference voltage Vref. 4. The PLL circuit according to claim 3, wherein the control signal Vc is a signal controlled by a microcomputer instead of the power-on reset signal, and an external circuit outputs the output signal of the voltage / frequency conversion means. When not necessary, the control signal Vc is controlled by the microcomputer so that both the phase comparison signals Vn and Vp are inactive so that the frequency of the output signal of the voltage / frequency conversion means becomes close to the target frequency. And the charge
The output of the low-pass filter, which is an active filter, becomes
PL which is equal to the reference voltage Vref
L circuit. 5. The PLL circuit according to claim 3, wherein the control signal Vc is a reference signal missing detection signal from an external circuit instead of the power-on reset signal, and when the reference signal is missing, the voltage / voltage Both of the phase comparison signals Vn and Vp are deactivated so that the frequency of the output signal of the frequency conversion means is close to the target frequency, and the output of the charge pump becomes high impedance, thereby being an active filter. A PLL circuit in which the output of the low-pass filter is equal to the reference voltage Vref. 6. A VCO or other voltage / frequency conversion means in which a frequency of an output signal changes according to a voltage value of an input signal, and a reference which is a target of synchronization while the output signal is output to an external circuit. A phase difference detector that performs phase comparison with the signal Vs and outputs phase comparison signals Vn and Vp, and outputs a certain voltage value V (H) or V (L) controlled by the phase comparison signals Vn and Vp. , Or a charge pump having the function of making the output high impedance, and a frequency characteristic that stabilizes the circuit loop, the high frequency component of the output signal of the charge pump is removed, and the high frequency component is removed. Signal and external control signal Vc
The control signal Vc is a power-on reset signal, and the control signal Vc is a power-on reset signal. A PLL circuit characterized in that the output voltage of the low-pass filter is largely offset in a high direction or a low direction. 7. The PLL circuit according to claim 6, wherein the control signal Vc is a signal controlled by a microcomputer instead of the power-on reset signal, and an external circuit outputs the output signal of the voltage / frequency conversion means. When it is not necessary, the control signal Vc is controlled by the microcomputer so that the output voltage of the low-pass filter becomes higher or lower so that the frequency of the output signal of the voltage / frequency conversion means becomes close to the target frequency. A PLL circuit characterized by being largely offset in the direction. 8. A VCO or other voltage / frequency conversion means in which the frequency of the output signal changes according to the voltage value of the first input signal and the voltage value of the second input signal, and the output signal A phase difference detector that outputs a phase comparison signal Vn, Vp by performing a phase comparison with a reference signal Vs to be synchronized while being output to an external circuit; and being controlled by the phase comparison signal Vn, Vp, A charge pump having a function of outputting a voltage value V (H) or V (L) or having a high impedance output, and a frequency characteristic for stabilizing a circuit loop, and a high output signal of the charge pump. A low-pass filter that removes band components and outputs a signal from which high-band components have been removed as a first input signal of the voltage / frequency conversion means, As second input signal are input the control signal Vc from the outside, and the control signal Vc is a power-on reset signal, for a while after power-on, the voltage /
So that the frequency of the output signal of the frequency conversion means becomes low,
A PLL circuit for controlling the voltage / frequency conversion means. 9. The PLL circuit according to claim 8, wherein the control signal Vc is a signal controlled by a microcomputer instead of the power-on reset signal, and an external circuit outputs the output signal of the voltage / frequency conversion means. When not required, the control signal Vc is controlled by a microcomputer to control the voltage / frequency conversion means so that the frequency of the output signal of the voltage / frequency conversion means becomes low. circuit. 10. A VCO or other voltage / frequency having an oscillating function, comprising a first input for changing the frequency of an output signal according to a voltage value of an input signal and a second input for stopping oscillation. A conversion means; a phase difference detector that outputs the output signal to an external circuit and outputs phase comparison signals Vn and Vp by performing a phase comparison with a reference signal Vs to be synchronized; and the phase comparison signal Vn. , Vp, which outputs a certain voltage value V (H) or V (L), or has a function of making the output high impedance, and a frequency characteristic for stabilizing the circuit loop, A low-pass filter for removing a high-frequency component of the output signal of the charge pump and outputting it as a first input signal of the voltage / frequency conversion means, the voltage / frequency conversion means As a second input signal are input the control signal Vc from the outside, and the control signal Vc is a power-on reset signal, while after power-on, the voltage /
P characterized by stopping the oscillation of the frequency conversion means
LL circuit. 11. The PLL circuit according to claim 10, wherein the control signal Vc is a signal controlled by a microcomputer instead of the power-on reset signal, and an external circuit outputs the output signal of the voltage / frequency conversion means. A PLL circuit characterized in that when it is not necessary, the control signal Vc is controlled by a microcomputer to stop the oscillation of the voltage / frequency conversion means.