JPH09116424A - Frequency division circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a circuit by which plural frequencies can be obtained and which can be used for the speed control of a pulse motor and the like by inverting the logic value of an output signal when a frequency division counter value is matched with a setting value. SOLUTION: A reference clock signal Fc is frequency-divided by respective FF1-7 in a frequency divider 1 and respective outputs C0-6 are inputted to circuits AND1-7 in a selection part 20. The inputs are AND-operated with the respective outputs of a selector 2, all the outputs of AND1-7 are OR-operated in an OR circuit 5 and a basic clock signal Fb is obtained. The signal Fb is inputted to the counter 13 of a counter part 3 and an up-count operation is executed. When the value of the counter 13 is matched with the setting value of a setting part 50, a comparison circuit 14 resets the counter 13 and FF 15 inverts the logic value of an output signal Fout . Continuous pulse signals are outputted by permitting the counter 13 to repeat resetting and up-counting.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a frequency dividing circuit for dividing the frequency of a reference clock signal into an arbitrary frequency for controlling the speed of a pulse motor.

[0002]

2. Description of the Related Art Conventionally, as a frequency dividing circuit for dividing a reference clock signal having a constant period, there has been known a circuit including n stages (n is a natural number) of flip-flops. In such a frequency divider circuit, the reference clock signal (pulse input) applied to the first-stage flip-flop is divided into a frequency of half the reference clock signal every time it passes through the flip-flop. 1 / ⁿ if you pass
An output signal divided by is obtained. That is, the frequency division number (reciprocal of the frequency division ratio) of the frequency ^{dividing circuit} changes by 2 ^{n as} the number of stages (n) of the flip-flops (FF) increases, as shown in FIG.

[0003]

However, in the above frequency ^{dividing circuit,} only the frequency ^dividing number of 2 ⁿ of the reference clock signal (that is, the frequency of 1/2 ^{n of the} reference clock signal) can be obtained. As shown, as the number (n) of flip-flops (FF) increases, the change in the frequency division number increases.

Therefore, when the pulse motor is driven by using the output signal of the frequency ^{dividing circuit} as a drive pulse, the drive pulse is 2 ⁿ times the reference clock signal in response to the acceleration / deceleration operation instruction from the control unit of the pulse motor. Since there is a change in the output frequency, there is a problem that the frequency change due to frequency division is large, the pulse motor is out of synchronization (a phenomenon in which the motor rotation speed cannot keep up with the drive pulse frequency), and acceleration / deceleration cannot be performed.

An n-bit counter (n is a natural number) that realizes arbitrary frequency division is also known as another frequency dividing circuit. However, in order to obtain a large frequency division number, the n-bit counter needs a multi-bit number. Since it has to be provided, the circuit scale of the frequency dividing circuit becomes large, which is not practical. The present invention has been made in view of the above circumstances, and an object thereof is to provide a frequency dividing circuit that can easily obtain various frequency dividing numbers and can be used for speed control of a pulse motor or the like. .

[0006]

In order to achieve the above-mentioned object, the invention according to claim 1 divides a reference clock signal into an arbitrary frequency and a frequency divider which is connected to the frequency divider. A selection unit for selecting a signal divided into a desired frequency from a plurality of outputs of the container, an up counter connected to the selection unit and having a count value increased according to the signal selected by the selection unit, and an up counter A comparison circuit that resets the up counter when a count value and a preset setting value match, and a flip-flop connected to the output from the comparison circuit, wherein the flip-flop has the count value and the Since the logical value of the output signal is inverted by the output from the comparison circuit when the set values match, the signal selected by the selector and the setting Easily can be obtained a variety of frequency division number by changing the values, Thus, it can be used for speed control such as a pulse motor.

According to a second aspect of the present invention, there is provided a frequency divider comprising a flip-flop of a first stage which operates in synchronization with a rising edge of a clock signal of a constant cycle, and a plurality of flip-flops to which outputs of respective flip-flops of the preceding stages are inputted. , A plurality of AND circuits to which outputs of the respective flip-flops and outputs of selectors for selecting desired outputs of the flip-flops are connected, and one output to which the outputs of the plurality of AND circuits are input. An OR circuit, a counter connected to the output of the OR circuit, a setting unit that presets the count setting value of the counter, and the count value obtained by comparing the count value of the counter with the setting value. And a comparison circuit that resets the counter when the set values match, and a flip-flop connected to the output from the comparison circuit. The flip-flop is characterized by inverting the logical value of the output signal by the output from the comparison circuit when the count value and the set value match, so that the output of the selector and the set value are By changing it, various frequency division numbers can be easily obtained, and therefore, it can be used for speed control of pulse motors and the like.

According to a third aspect of the present invention, there is provided a frequency divider comprising a flip-flop of a first stage which operates in synchronization with a rising edge of a clock signal of a constant cycle and a plurality of flip-flops to which outputs of respective flip-flops of the preceding stages are inputted. , A plurality of AND circuits to which respective outputs of the respective flip-flops and outputs of a first selector for selecting a desired output of the flip-flops are connected, and outputs of the plurality of AND circuits are input. A logical OR circuit, a counter connected to the output of the logical OR circuit, a plurality of set value registers for presetting the set value of the count of the counter, and one of the plurality of set value registers. Second
Selector for comparing the count value of the counter with the set value selected by the second selector and resetting the counter when the count value and the set value match, and the comparator circuit A flip-flop connected to the output of the flip-flop, and the flip-flop inverts the logical value of the output signal by the output from the comparison circuit when the count value and the set value match. By changing the output of the first selector and the set value, it is possible to easily obtain various frequency division numbers, and thus it can be used for speed control of a pulse motor or the like.

According to a fourth aspect of the present invention, a frequency divider for dividing the reference clock signal into an arbitrary frequency, and a plurality of outputs of the frequency divider, which are connected to the frequency divider, are divided into a desired frequency. A selection unit that selects a signal, an up counter that is connected to the selection unit and whose count value increases according to the signal selected by the selection unit, and a data table in which a plurality of set values of the count of the up counter are written, A comparison circuit that resets the up counter when the count value and a set value read from the data table match, and a flip-flop connected to an output from the comparison circuit, wherein the flip-flop is the Since the logical value of the output signal is inverted by the output from the comparison circuit when the count value and the set value match, Serial easily can get different frequency division number by changing signal for selecting the with said set value by the selection unit, Thus, can be used for speed control such as a pulse motor.

According to a fifth aspect of the invention, the comparator circuit reads another set value from the data table each time the up counter is reset. Therefore, the comparator circuit depends on the set value each time the up counter is reset. Then, the frequency division number changes, and various frequency division numbers can be easily obtained. Therefore, it can be used for speed control of a pulse motor or the like. According to a sixth aspect of the present invention, there is provided a frequency divider comprising a first-stage flip-flop that operates in synchronization with a rising edge of a clock signal having a constant cycle and a plurality of flip-flops to which outputs of respective preceding flip-flops are input, and A plurality of AND circuits to which outputs of the flip-flops and outputs of selectors for selecting desired outputs of the flip-flops are connected, and one OR circuit to which outputs of the plurality of AND circuits are input A counter connected to the output of the OR circuit, a data table in which a plurality of setting values of the count value of the counter are set, a setting unit for receiving the setting value data from the data table, The count value of the counter and the first setting value of the setting unit are compared, and when the count value and the first setting value match, the counter is counted. A comparison circuit for writing the second set value to the setting unit from the reset and the data table,
A flip-flop connected to the output from the comparison circuit, wherein the flip-flop inverts the logical value of the output signal by the output from the comparison circuit when the count value and the set value match. Therefore, it is possible to easily obtain various frequency division numbers by changing the output of the selector and the set value in the setting unit, and thus it can be used for speed control of a pulse motor or the like.

[0011]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to embodiments. (Embodiment 1) This embodiment corresponds to the inventions of claims 1 and 2, and will be described below with reference to FIGS.
And FIG. 7 demonstrates.

The frequency dividing circuit of this embodiment is shown in FIG.
A frequency divider 1 for dividing the reference clock signal Fc,
Selector 2 for selecting the frequency of the desired (arbitrary) frequency division number
0, the counter unit 3 connected to the output of the selection unit 20,
Consisting of In the present embodiment, the frequency divider 1 has a fixed period base.
First to operate in synchronization with the rising of the quasi-clock signal Fc
Stage flip-flop FF₁And each front flip
Flip-flop FF to which the Q output of the flop is input_Two
~ FF₇Consisting of Flip-flop FF_Two~ FF₇
Is the rising edge of the Q output of the previous flip-flop
Invert. Here, each flip-flop FF₁~ FF₇
Q output of each c ₀~ C₆And

The selection unit 20 includes a flip-flop FF.₁~
FF₇Output c₀~ C₆Select the desired output of
Selector 2 for logical AND circuit AND₁~ AND₇Consisting of
You. Each output terminal of the selector 2 has a logical value "1" or a logical value
Output a signal of "0" and AND circuit AND₁~ AND₇
Output of selector 2 and each flip-flop FF ₁
~ FF₇Each output c₀~ C₆And the further discussion
A desired output is selected by the summing circuit 5 and the output signal Fb is selected.
Output as

The counter section 3 outputs the output signal Fb of the selecting section 20.
An n-bit counter 13 for up-counting the pulses of the input signal using the
The comparison circuit 14 compares the count value of the bit counter 13 and clears the n-bit counter 13 when the set value and the count value match, and a flip-flop 15 connected to the output of the comparison circuit 14. The output of the flip-flop 15 becomes the output signal F _out .

The operation of the frequency dividing circuit will be described in detail below. The reference clock signal Fc is divided by each of the flip-flops FF _{1 to} FF ₇ in the frequency divider 1 (the frequency becomes ½ each time one stage passes through the flip-flop), and the division number is the flip-flop. Output c of FF _1
0 is 2 ¹ = 2, and the output c ₁ of the flip-flop FF ₂ is 2
² = 4, ..., The output c ₆ of the flip-flop FF ₇ becomes 2 ⁷ = 128. That is, the output c ₀ is half the frequency of the reference clock Fc, and the output c _0
1 is one of two frequencies ² minutes of the frequency of the reference clock Fc, · · ·, output c ₆ is one of a frequency of 2 ⁷ minutes of the frequency of the reference clock Fc.

In the selection unit 20, each flip-flop FF
₁ Output c ₀ to c ₆ of each of the to ff ₇ are input to the AND circuit AND ₁ ~AND ₇ corresponding to the flip-flop of each, each of the AND circuits AND ₁ ~AND ₇ respectively connected selector 2 The outputs are logically ANDed, and the logical sum circuit 5 logically ORs the outputs of all the AND circuits AND _{1 to} AND ₇ to output the basic clock signal Fb.

The basic clock signal Fb output from the OR circuit 5 is input to the n-bit counter 13 in the counter section 3, and the n-bit counter 13 performs an up-count operation. Further, the comparison circuit 14 includes an n-bit counter 13
When the count value and the set value match, n is compared with the set value preset by the setting unit 50.
The reset signal Rs is output to the bit counter 13 to reset the n-bit counter 13, and the flip-flop 15 inverts the logical value of the output signal F _out (toggle operation). After that, the n-bit counter 13 performs the up-count operation again.

The n-bit counter 13 outputs the continuous pulse signal by repeating the above operation. For example, when the reference clock signal Fc as shown in FIG. 2A is input to the flip-flop FF ₁ , the selector 2 inputs the signal of the logical value “1” only to the AND circuit AND ₁ . When a signal of logical value "0" is input to the AND circuits AND _{2 to} AND ₇ ) and the output c ₀ of the flip-flop FF ₁ is selected, the basic clock signal Fb becomes as shown in FIG.
As shown in (b), a clock signal obtained by dividing the reference clock signal Fc by 2 is obtained, and the basic clock signal Fb is obtained.
Is input to the n-bit counter 13. Here, if the set value in the setting unit 50 is “3”, for example, the comparison circuit 14
When the count value of the n-bit counter 13 reaches 3 (t ₂ ) as shown in FIG. 2C, the n-bit counter 1
3 is reset, and the logical value of the output signal F _out is inverted by the flip-flop 15 as shown in FIG. Therefore, as shown in FIG. 2D, the output signal F
_out is a signal obtained by dividing the basic clock signal Fb by 6.
That is, the counter unit 3 operates as a 1/6 frequency divider. As a result, the output signal F _out is the reference clock signal F
The signal is divided into 1/12 of c.

That is, the frequency division number (the frequency division number in the preceding stage in FIG. 7) selected by the selector 2 of the selection unit 20 and the counter unit 3
The frequency division number as shown in FIG. 7 can be obtained by multiplying by the frequency division number (setting value × 2). Therefore, as is apparent from comparison between FIG. 7 and FIG. 9 (conventional example), this frequency dividing circuit can easily obtain various frequency dividing numbers as compared with the conventional frequency dividing circuit. Therefore, the acceleration / deceleration operation of the pulse motor can be easily performed by using the output signal of the frequency dividing circuit as the drive pulse of the pulse motor.

Note that the maximum frequency division number obtained by the frequency division circuit of the present embodiment is as shown in FIG. 7, in which the output c ₆ (frequency division number 128) of the flip-flop FF ₇ is selected by the selection unit 20 (that is, , The selector 2) selects the output c ₆ as the basic clock F
b, and the frequency division number of the counter unit 3 is 16 (that is,
It is 2048 obtained when the set value is "8").

(Embodiment 2) The present embodiment claims 3
The present invention corresponds to the invention of FIG. 3 and will be described below with reference to FIGS. The divider circuit of this embodiment is
As shown in FIG. 3, the basic configuration is almost the same as in FIG.
The configurations and operations of frequency divider 1 and selection unit 20 are the same as in the first embodiment. The characteristic of this frequency divider is
It is in the configuration and operation of the counter unit 6.

The counter section 6 of this frequency dividing circuit includes a selecting section 20.
N-bit counter 13 for up-counting the pulses of the input signal using output signal Fb of
8 compares the set value read from one of the set value registers 70 and 80 with the count value of the n-bit counter 13 and resets the n-bit counter 13 when the set value and the count value match. At the same time, it comprises a comparator circuit 17 for outputting a select signal to the selector 18 to select a set value from a set value register having a set value different from the set value, and a flip-flop 15 connected to the output of the comparator circuit 17. The output of the flip-flop 15 becomes the output signal F _out .

The operation of the frequency dividing circuit will be described below. However, the part of the same operation as in FIG. 1 will be briefly described. In this frequency dividing circuit, the reference clock signal Fc is divided by the frequency divider 1 and the basic clock signal Fb is selected by the selector 2 of the selecting section 20. The basic clock signal Fb is input to the n-bit counter 13 in the counter section 6,
The n-bit counter 13 performs an up-count operation.

Further, the comparison circuit 17 compares the count value of the n-bit counter 13 with the set value A of the setting section 70 selected by the selector 18, and when the count value and the set value A match, The reset signal Rs is output to the n-bit counter 13 to reset the n-bit counter 13, and the flip-flop 15 outputs the output signal Fs.
Inverts the logical value of _out . Further, the comparison circuit 17 outputs the select signal Ss to the select 18, and the set value register 8
The set value B of 0 is selected. And n-bit counter 1
3 performs the up-count operation again. By repeating the above operation, continuous pulses are generated.

For example, when the reference clock signal Fc as shown in FIG. 4A is input to the flip-flop FF ₁ , the selector 2 inputs the signal of the logical value "1" only to the AND circuit AND _1. When the output c ₀ of the flip-flop FF ₁ is selected by using the basic clock signal Fb shown in FIG.
As shown in (b), a clock signal obtained by dividing the reference clock signal Fc by 2 is obtained, and the basic clock signal Fb is obtained.
Is input to the n-bit counter 13. Here, if the set values A and B are, for example, “3” and “2”, respectively, the comparator circuit 17 determines that the count value of the n-bit counter 13 becomes 3 as shown in FIG. At t ₂ ), the n-bit counter 13 is reset, and the flip-flop 15 inverts the logical value of the output signal F _out as shown in FIG. Further, since the comparison circuit 17 selects the setting value B by the selector 18 at the time of t ₂ , the n-bit counter 13 is reset when the count value of the n-bit counter 13 becomes 2 (t ₃ ). As shown in FIG. 4D, the flip-flop 15 inverts the logical value of the output signal F _out . Therefore, as shown in FIG. 4D, the output signal F _out is a signal obtained by dividing the basic clock signal Fb by 5. That is, the counter unit 6 operates as a 1/5 frequency divider. As a result, the output signal F _out is a signal that is divided by 1/10 (frequency division number 10) with respect to the reference clock signal Fc.

That is, the frequency division number (the frequency division number in the preceding stage in FIG. 8) selected by the selector 2 of the selection unit 20 and the counter unit 6
It is possible to obtain a frequency division number as shown in FIG. 8 by multiplying the frequency division number with the maximum frequency division number of 2048. Therefore, the acceleration / deceleration operation of the pulse motor can be easily performed by using the output signal of the frequency dividing circuit as the drive pulse of the pulse motor.

(Embodiment 3) This embodiment is claim 4.
It corresponds to the invention of claim 6 to FIG.
And FIG. 6 will be described. As shown in FIG. 5, the frequency dividing circuit of the present embodiment has the same basic configuration as that of FIG. 1, and the configurations and operations of frequency divider 1 and selection unit 20 are the same as those of the first embodiment. A feature of this frequency dividing circuit is that a setting value table is connected to the counter section 11.

The counter section 11 of the frequency dividing circuit includes a selection section 2
An n-bit counter 13 that up-counts pulses of the input signal using the output signal Fb of 0 as an input signal is compared with the set value written from the table 12 and the count value of the n-bit counter 13, and the set value and the above-mentioned A comparator circuit 21 that resets the n-bit counter 13 when the count values match and outputs a write request signal Sr to the table 12 and the setting unit 60 to write the set value from the table 12 to the setting unit 60; 21 and the flip-flop 15 connected to the output of the flip-flop 15. The output of the flip-flop 15 becomes the output signal F _out .

The operation of the frequency dividing circuit will be described below. However, the part of the same operation as in FIG. 1 will be briefly described. In this frequency dividing circuit, the reference clock signal Fc is divided by the frequency divider 1 and the basic clock signal Fb is selected by the selector 2 of the selecting section 20. The basic clock signal Fb is input to the n-bit counter 13 in the counter section 11, and the n-bit counter 13 performs an up-count operation.

Further, the comparison circuit 21 compares the count value of the n-bit counter 13 with the set value written in the setting section 60 from the table 12, and when the count value and the set value match, n bits are set. The counter 13 is reset and the flip-flop 15 inverts the logical value of the output signal F _out . Further, the comparison circuit 21 outputs the write request signal Sr to the table 12 and the setting unit 60, and outputs the write data Sd from the table 12 to the setting unit 60 to write the set value different from the set value. Then, the n-bit counter 13 performs the up-count operation again. By repeating the above operation, continuous pulses are generated.

For example, when the reference clock signal Fc as shown in FIG. 6A is input to the flip-flop FF ₁ , the selector 2 inputs the signal of the logical value “1” only to the AND circuit AND _1. When the output c ₀ of the flip-flop FF ₁ is selected by using the basic clock signal Fb shown in FIG.
As shown in (b), a clock signal obtained by dividing the reference clock signal Fc by 2 is obtained, and the basic clock signal Fb is obtained.
Is input to the n-bit counter 13. For example, setting values to be written from the table 12 to the setting unit are “5”, “4”,
If you set it like "3", "2", "1",
As shown in (c) and (d), the output signal F _out is inverted every time the count value of the n-bit counter 13 matches the set value (t _{1 to} t ₅ ), and the frequency division number is also equal to the set value. .

Therefore, if the output signal of such a frequency dividing circuit is used as the drive pulse of the pulse motor, the acceleration / deceleration operation (speed control) of the pulse motor can be easily performed.

[0033]

According to the invention of claim 1, a selector connected to the frequency divider for selecting a frequency-divided signal from a plurality of outputs of the frequency divider, and a selector connected to the selector. An up-counter whose count value increases according to the signal selected by the selection unit; a comparator circuit which resets the up-counter when the count value of the up-counter matches a preset setting value; A flip-flop connected to the output of the flip-flop, and the flip-flop inverts the logical value of the output signal by the output from the comparison circuit when the count value and the set value match each other. By changing the signal to be selected and the set value, it is possible to easily obtain various frequency division numbers. Therefore, it can be used for speed control of pulse motors, etc. There is an effect that that.

According to a second aspect of the present invention, a plurality of logical product circuits to which the respective outputs of the respective flip-flops and the output of the selector for selecting a desired output of the flip-flop are connected, and the plurality of logical product circuits. Input of the output of 1
One OR circuit, a counter connected to the output of the OR circuit, a setting unit that presets the set value of the count of the counter, and the count value obtained by comparing the count value of the counter with the set value. A comparison circuit that resets the counter when the value and the set value match, and a flip-flop connected to the output from the comparison circuit, and the flip-flop has the count value and the set value matched. Since the logical value of the output signal is sometimes inverted by the output from the comparison circuit, various frequency division numbers can be easily obtained by changing the output of the selector and the set value. There is an effect that it can be used for speed control of.

According to a third aspect of the present invention, a plurality of AND circuits to which the respective outputs of the flip-flops and the output of the first selector for selecting a desired output of the flip-flop are connected, and the plurality of AND circuits. One logical sum circuit to which the output of the logical product circuit is input, a counter connected to the output of the logical sum circuit, a plurality of setting value registers for presetting the setting value of the count of the counter, and a plurality of the plurality of setting value registers. A second selector that selects one of the set value registers is compared with the count value of the counter and the set value selected by the second selector, and when the count value and the set value match, A comparison circuit for resetting a counter and a flip-flop connected to an output from the comparison circuit are provided, and the flip-flop has the count value and the set value equal to each other. At this time, the logical value of the output signal is inverted by the output from the comparison circuit, so that it is possible to easily obtain various frequency division numbers by changing the output of the first selector and the set value. For,
It has an effect that it can be used for speed control of a pulse motor.

According to a fourth aspect of the present invention, there is provided a selecting section connected to the frequency divider for selecting a signal divided into a desired frequency from a plurality of outputs of the frequency divider, and the selecting section connected to the selecting section. The up counter whose count value increases in accordance with the signal selected by, the data table in which a plurality of setting values of the count of the up counter are written, and the count value and the setting value read from the data table match. And a flip-flop connected to an output from the comparison circuit, the flip-flop being connected to the output from the comparison circuit when the count value and the set value match. Since the logical value of the output signal is inverted by the output, it is easy to change the signal selected by the selection unit and the set value. It is possible to obtain a Roiro divider number,
Therefore, there is an effect that it can be used for speed control of the pulse motor.

According to the fifth aspect of the present invention, the comparator circuit reads another set value from the data table every time the up counter is reset. Therefore, the frequency division number depends on the set value each time the up counter is reset. Changes, and various frequency division numbers can be easily obtained. Therefore, there is an effect that it can be used for speed control of a pulse motor. Claim 6
In the invention, a plurality of logical product circuits to which the respective outputs of the respective flip-flops and the output of the selector for selecting a desired output of the flip-flop are connected, and the outputs of the plurality of logical product circuits are input. One logical sum circuit, a counter connected to the output of the logical sum circuit, a data table in which a plurality of set values of the count value of the counter are set, and data of the set values from the data table are received. The setting unit compares the count value of the counter with the first setting value of the setting unit, resets the counter when the count value and the first setting value match, and stores the counter from the data table. A comparator circuit for writing the second set value to the setting unit and a flip-flop connected to the output from the comparator circuit are provided, and the flip-flop is the capacitor. Since the logical value of the output signal is inverted by the output from the comparison circuit when the input value and the set value match, it is possible to easily change various values by changing the output of the selector and the set value in the setting section. It is possible to obtain the number of revolutions, and therefore, it is possible to use it for speed control of the pulse motor.

[Brief description of the drawings]

FIG. 1 is a circuit configuration diagram showing a first embodiment.

FIG. 2 is an operation explanatory diagram of the first embodiment.

FIG. 3 is a circuit configuration diagram showing a second embodiment.

FIG. 4 is an operation explanatory diagram of the second embodiment.

FIG. 5 is a circuit configuration diagram showing a third embodiment.

FIG. 6 is an operation explanatory diagram of the third embodiment.

FIG. 7 is an explanatory diagram of frequency division numbers obtained by the frequency division circuit according to the first embodiment.

FIG. 8 is an explanatory diagram of frequency division numbers obtained by the frequency dividing circuit according to the second embodiment.

FIG. 9 is an explanatory diagram of a relationship between the number of stages of a flip-flop and a frequency division number of a conventional example.

[Explanation of symbols]

1 frequency divider 2 selector 3 counter section 5 OR circuit 13 n-bit counter 14 comparison circuit 15 flip-flop 20 selection section 50 setting section AND _{1 to} AND ₇ AND circuit Fb basic clock signal Fc reference clock signal FF _{1 to} FF ₇ Flip-flop F _out output signal

Claims (6)

[Claims] 1. A frequency divider that divides a reference clock signal to an arbitrary frequency, and a selection that is connected to the frequency divider and that selects a signal divided to a desired frequency from a plurality of outputs of the frequency divider. Section, an up-counter connected to the selection section and having a count value increased according to the signal selected by the selection section, and the up-counter when the count value of the up-counter and a preset setting value match. A comparator circuit for resetting and a flip-flop connected to the output from the comparator circuit are provided, and the flip-flop outputs the logic of the output signal by the output from the comparator circuit when the count value and the set value match. A frequency divider circuit that inverts a value. 2. A frequency divider comprising a first-stage flip-flop that operates in synchronization with a rising edge of a clock signal of a constant cycle and a plurality of flip-flops to which outputs of respective front-stage flip-flops are input, and the respective flip-flops. A plurality of logical product circuits to which the respective outputs of the above and the output of the selector for selecting the desired output of the flip-flop are connected, and one logical sum circuit to which the outputs of the plurality of logical product circuits are input, A counter connected to the output of the OR circuit, a setting unit that presets a count setting value of the counter, and a count value and the setting value by comparing the count value and the setting value of the counter. And a flip-flop connected to the output from the comparison circuit. A frequency divider circuit, wherein the flip-flop inverts the logical value of the output signal by the output from the comparison circuit when the count value and the set value match. 3. A frequency divider comprising a flip-flop at a first stage and a plurality of flip-flops to which outputs of flip-flops at respective preceding stages which operate in synchronization with rising edges of a clock signal having a constant cycle are input, and each of the flip-flops. And a plurality of logical product circuits to which outputs of the first selector for selecting a desired output of the flip-flop are connected, and one logical sum to which outputs of the plurality of logical product circuits are input. Circuit, a counter connected to the output of the OR circuit, a plurality of set value registers for presetting the set value of the count of the counter, and a second selector for selecting one of the plurality of set value registers And comparing the count value of the counter with the set value selected by the second selector, and when the count value and the set value match. A comparator circuit for resetting the counter and a flip-flop connected to the output from the comparator circuit are provided, and the flip-flop outputs an output signal from the output from the comparator circuit when the count value and the set value match. A frequency divider circuit characterized by inverting the logical value of. 4. A frequency divider that divides a reference clock signal into an arbitrary frequency, and a selection that is connected to the frequency divider and that selects a signal divided into a desired frequency from a plurality of outputs of the frequency divider. Section, an up counter connected to the selection section and having a count value increased according to a signal selected by the selection section, a data table in which a plurality of setting values of the count of the up counter are written, the count value and the A comparison circuit that resets the up counter when the set values read from the data table match, and a flip-flop connected to an output from the comparison circuit, the flip-flop being provided with the count value and the setting A frequency divider circuit which inverts a logical value of an output signal by an output from the comparison circuit when the values coincide with each other. 5. The frequency divider circuit according to claim 4, wherein the comparator circuit reads another set value from the data table each time the up counter is reset. 6. A frequency divider comprising a first-stage flip-flop that operates in synchronization with a rising edge of a clock signal having a constant cycle and a plurality of flip-flops to which outputs of respective preceding flip-flops are input, and each of the flip-flops. And a plurality of logical product circuits to which outputs of the first selector for selecting a desired output of the flip-flop are connected, and one logical sum to which outputs of the plurality of logical product circuits are input. A circuit, a counter connected to the output of the OR circuit, a data table in which a plurality of setting values of the count value of the counter are set, and a setting unit which receives the setting value data from the data table, When the count value of the counter and the first set value of the setting unit are compared and the count value and the first set value match, the count And a flip-flop connected to an output from the comparison circuit, the flip-flop connected to the output from the comparison circuit, and the flip-flop connected to the output from the comparison circuit. A frequency divider circuit, wherein a logical value of an output signal is inverted by an output from the comparison circuit when the set values match.