JPH09116120A - Nonvolatile semiconductor storage device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To realize highly reliable novel electrical rewriting with high density by connecting well areas in a memory cell on the same array with each other through a well line and providing a means for supplying voltage to the well area individually every column. SOLUTION: Memory cells for three bits are formed on a silicon oxide film 102. Every memory cell is electrically isolated from each other through a silicon oxide film 104. In addition, a drain area 107 and a source area 108 are formed with a well area 103 in between, and every area has a depth of 0.1 to 0.3μm. A p-type impurity area 112 reduces the breakdown voltage of a joint part between the areas 108 and 103 and eases writing operation thereof. A word line functions as a control gate to delete/write/read data for respective memory cells.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a non-volatile semiconductor memory device having an electric rewriting function, and more particularly to a non-volatile semiconductor memory device suitable for application in the case of being constituted by a large scale integrated circuit.

[0002]

2. Description of the Related Art A non-volatile semiconductor device having an electric rewriting function is composed of a plurality of memory cells arranged in a matrix. The memory cell is composed of a MOS field effect transistor (hereinafter referred to as “MOS transistor”) having a source region, a drain region, a well region, a floating gate and a control gate. A typical structure of a non-volatile semiconductor device is a parallel type in which memory cells are connected in parallel. In the parallel type, the drain regions of a plurality of memory cells continuous in the column direction are connected by data lines and the source regions are connected by a source line, and the control gates of a plurality of memory cells continuous in the row direction are connected. Are connected by word lines. All the well regions of these memory cells are electrically connected to each other, and a predetermined voltage is supplied to all the well regions through a connection line or a substrate.

Writing and erasing operations of a memory cell will be described by taking the device disclosed in Japanese Patent Laid-Open No. 14871/1992 as an example. The data write operation to the memory cell is performed by emitting electrons from the floating gate. As a result, the threshold voltage for programming the memory cell is set to about 1V. In the write operation, tunnel emission of electrons due to the FN (Fowler-Nordheim) phenomenon of the gate insulating film via the end of the drain region is used. In order to perform the tunnel emission, a voltage that is negative with respect to the voltage applied to the well region is applied to the word line, and a voltage that is positive with respect to the voltage applied to the well region is applied to the drain region.

The data erasing operation of the memory cell is performed by injecting electrons into the floating gate. As a result, the threshold voltage for erasing the memory cell is set to approximately 3 V or higher. In the erase operation, the F-N via the entire gate insulating film of the MOS transistor that constitutes the memory cell
Tunneling injection of electrons by a phenomenon is used. In order to perform tunnel injection, a voltage that is positive with respect to the voltage applied to the well region is applied to the word line.

In such a conventional nonvolatile semiconductor memory device, it is necessary to provide a portion where the floating gate and the drain region overlap in order to realize the tunnel emission in the erase operation. Since this overlap portion is at most 1/3 of the gate area, it is necessary to increase the current density in order to obtain a desired tunnel current. Therefore, it is necessary to apply a high electric field to the overlapping portion of the gate insulating film. When the rewriting operation is performed by applying a high electric field, the deterioration of the gate insulating film progresses and
There is a problem that writing time and erasing time increase.

On the other hand, there is a limit to reducing the size of the drain region because the overlap portion is required. Therefore, it is difficult to shorten the gate length of the MOS transistor, and there is a problem that the overlapping portion becomes an obstacle in promoting miniaturization of the cell.

Further, memory cells on the same word line are collectively erased, and it is impossible to mix memory cells that are not selected for erase (hereinafter referred to as "non-erased").

[0008]

SUMMARY OF THE INVENTION An object of the present invention is to solve the above-mentioned problems and provide a novel electrically rewritable nonvolatile memory device having high reliability and extremely high density. Especially.

[0009]

The object of the present invention is to form an insulating layer region for electrically separating well regions of memory cells on adjacent columns from each other between the memory cells, and The problem can be solved by connecting the well regions of the memory cells on the same column to each other by a well line and providing a means for individually supplying a voltage to the well region for each column. Since it is possible to individually apply a predetermined voltage to the well region of each memory cell on the same word line, a tunnel phenomenon using the entire surface of the gate insulating film can be generated at the time of erasing and writing. Unselected memory cells can be mixed on the same word line.

The means for supplying the voltage can be realized by providing a voltage supply circuit for each column and connecting the circuit to each well line. However, in this case, the memory device becomes complicated by the addition of the voltage supply circuit. Another second means is a means that functions to supply a voltage to the well region via the junction between the well region and the drain region, and a voltage to the well region via the junction between the well region and the source region. And means that serve to supply In this case, the well region of each column is set as a floating region which is not connected to the other, and the data line is connected to the latch circuit for supplying the drain voltage via the switch element composed of the MOS transistor,
Further, the source line is connected to the common source line via another switch element composed of a MOS transistor. Note that the source region and the drain region are each formed of an n-type impurity layer, the well region is formed of a p-type impurity layer, and the source region and the well region are formed in order to facilitate voltage supply from the source region. It is desirable that the boron impurity concentration in the well region is 5 × 10 ¹⁷ cm ⁻³ or more in the junction between them.

Still another third means is connected between the well line and the source line, and a means functioning to supply a voltage to the well region through a junction between the well region and the drain region. Means for supplying a voltage to the well region through the electrodes.
In this case, in order to separate the source line for each column, the source line is connected to a common source line for all memory cells via a switching element composed of a MOS transistor. Also,
The data line is connected to a latch circuit for supplying a drain voltage via another switch element composed of a MOS transistor.

In any of the means, the semiconductor substrate forming the memory cell has an SOI (Silicon On Insul)
ator) substrate is desirable. Electrical isolation between the well regions of adjacent memory cells can be ensured.

[0013]

BEST MODE FOR CARRYING OUT THE INVENTION The nonvolatile semiconductor memory device according to the present invention will now be described in more detail with reference to the embodiments and examples of the invention shown in the drawings. The same symbols in FIGS. 1 to 9 represent the same or similar items.

The erase operation of the memory cell employing the second voltage supply means will be described with reference to FIG. Although the write operation will be described later with reference to FIG. 4, in both figures, four memory cells M1-1, M1-2, M2 are used to avoid complication.
-1 and M2-2 are shown. The control gates of the memory cells M1-1 and M1-2 are connected to the word line W1 to form one row, and the memory cells M2-1 and M2-1 are connected to the word line W2.
The control gates of M2-2 are connected to form another row.

The memory cells M1-1 and M2 are connected to the data line D1.
The drain of -1 is connected, and the source of the same memory cell is connected to the source line S1 to form one column. Wells in the same row are connected to each other by a well line WE1,
There is no connection with others. The memory cell M1- is connected to the data line D2.
2, the drains of M2-2 are connected, and the source of the same memory cell is connected to the source line S2 to form another column. Wells in the same row are connected to each other by a well line WE2, but are not connected to others. An actual nonvolatile semiconductor memory device is composed of an extremely large number of memory cells, but the following description can be extended to such a large number of memory cells.

In data erasing, among a plurality of memory cells connected to one word line, memory cells selected for erasing (hereinafter referred to as “erasing selected”) are collectively erased. Each word line is connected to a word decoder. The word decoder applies a predetermined voltage to each word line. For example, when the word line W1 is erase-selected, a voltage of 12 V is applied to the word line W1. Also, the word line W2
Is erase-unselected, 0 V is applied to the same word line. Further, a latch circuit is connected to each data line, and each latch circuit applies a voltage of −5 V to the data line D1 of the memory cell M1-1 selected for erasure to erase the data of the memory cell M1-2 not selected for erasure. A voltage of 2V is applied to the line D2.

Under the above voltage condition, in the column in which the memory cell M1-1 for erase selection is present, the pn junction existing between the drain region and the well region is in the forward direction. As a result, the well region, which is a p-type impurity layer, is charged to approximately −4V obtained by adding −5V of the data line D1 to the diffusion potential difference (about 0.7V) of the pn junction. The potential of the well region before being charged does not fall below approximately -4V. In addition, since the channel is formed on the upper surface of the well region, the upper surface of the well region, the drain region, and the source region have the same potential.

On the other hand, in the column of the memory cells M1-2 which are not erase-selected, the pn junction between the drain region and the well region is in the reverse bias state. In this case, the voltage in the well region rises due to capacitive coupling. In this way, different voltages are applied to the well region of the column in which the memory cell M1-1 selected for erasing is located and the well region of the column of the memory cell M1-2 in which erasing is not selected. Such a difference in voltage is realized because the memory cells are electrically isolated for each column.

In the memory cell M1-1 selected to be erased, a voltage difference of about 17V is generated between the 12V word line W1 and the well. Therefore, the voltage of the floating gate rises due to the capacitive coupling ratio of the memory cell [ratio of the capacitance between the floating gate and the control gate (word line) to the total capacitance of the periphery viewed from the floating gate], and the gate insulating film has a voltage of about 10 MV. / C
A high electric field of m or more is applied. As a result, electrons are injected from the well region to the floating gate by the FN tunnel phenomenon,
The threshold voltage of the memory cell M1-1 rises to about 4V.

Further, in the non-selected memory cells M1-2,
A voltage difference of about 10 V is generated between the word line W1 and the well region, and an electric field of about 7 MV / cm is applied to the gate insulating film. In this case, the amount of electrons injected by the FN tunnel phenomenon is
It is about 1/1000 of the selected memory cell M1-1, and the threshold voltage does not increase. In this way, it becomes possible to control the erasing of data for each memory cell by applying different voltages to the wells electrically isolated for each column.

Next, writing of data to the memory cell will be described. Writing is generally performed after the erase operation is performed, and is performed in two steps. Writing is sequentially performed on the next word line after the completion of one word line. As shown in FIG. 4, writing (1), which is the first stage
Then, 4V is applied to each source line. At this time, each data line is opened. The open state can be realized by connecting the data line to the latch circuit via the switch element and controlling the switch element to be non-conductive.

As described above, since the well region in the pn junction between the source region and the well region has a high boron impurity concentration, the breakdown voltage of the pn junction is approximately 3 V or less. . Therefore, a current accompanying the breakdown flows from the source region to the well region, and the voltage of the well region rises to about 4V. The potential of the well region before writing does not exceed 0V.

In the second stage of writing (2), the source line is opened. The open state is achieved by connecting the source line to a common source line (common to all memory cells) via a switch element and controlling the switch element to be non-conductive. By controlling the switch element on the data line side to be in the conductive state and further controlling the latch circuit, 4V is applied to the data line D1 of the memory cell M1-1 selected for writing (hereinafter referred to as "writing selected"), 0 is not applied to the data line D2 of the memory cell M1-2 in which writing is not selected (hereinafter referred to as “writing unselected”).
Add V. In addition, -12V is applied to the word line W1 selected for writing.
Add.

As a result of the above, the memory cell M1- for writing is selected.
The voltage of the well region having 1 is kept at 4V. As a result, the well region, the drain region and the source region are all 4
It becomes the electric potential of V. On the other hand, write-unselected memory cell M1
At -2, since the PN junction between the drain region and the well region is in the forward direction, current flows from the drain region to the well region. Therefore, the voltage of the well region is approximately 0V.

In the memory cell M1-1 selected for writing, a voltage difference of about 16 V is generated between the word line W1 and the well region, so that the voltage of the floating gate becomes a negative voltage having a large absolute value. As a result, a high electric field of about 10 MV / cm or more is applied to the gate insulating film in the direction opposite to that at the time of erasing. As a result, electrons from the floating gate toward the well region are FN.
It is emitted by the tunnel phenomenon and the threshold voltage of the memory cell drops to about 1V. On the other hand, unselected memory cells M1-2
Then, a voltage difference of about 12 V in absolute value occurs between the word line W1 and the well region, and an electric field of about 8 MV / cm is applied to the gate insulating film. However, the amount of electrons emitted by the FN tunnel phenomenon is 1/100 of that of the selected memory cell M1-1.
However, the decrease in the threshold voltage is suppressed. In this way, by supplying different voltages to the well regions that are electrically isolated for each column, it becomes possible to control the writing of data for each memory cell.

In the above-described memory cell structure and its rewriting method of the present invention, electrons are injected / released by using the entire surface of the gate insulating film of the memory cell, so that the gate insulating film for obtaining a desired tunnel current is used. It is possible to keep the applied electric field strength low. Therefore, deterioration of the gate insulating film can be suppressed. Furthermore, it is not necessary to provide an overlapping portion, and the gate length of the MOS transistor that constitutes the memory cell can be shortened. For this reason, a large degree of integration can be achieved, and a nonvolatile semiconductor memory device of 256 megabits or more can be realized. Also,
It is possible to mix erase-unselected and write-unselected memory cells on the erase-selected and write-selected word lines, respectively.

[0027]

【Example】

<Embodiment 1> A first embodiment of the present invention will be described with reference to FIGS. FIG. 1 shows the structure of a memory cell viewed from a cross section parallel to the word line. In FIG.
Is a semiconductor substrate, 102 is a silicon oxide film formed on the substrate 101, 103 is a silicon semiconductor layer into which a p-type impurity has been introduced, which will be a well region (hereinafter referred to as “well region”).
, 104 is a silicon oxide film to be an isolation region,
Reference numeral 105 denotes a gate insulating film, 106 denotes a gate insulating film 105.
A conductive layer serving as an upper floating gate, 107 is a drain region into which an n-type impurity is introduced, 108 is a source region into which an n-type impurity is introduced, 109 is an insulating film, and 110 is
An insulating film formed on the floating gate 106 and the insulating film 109, 111 is a word line which also serves as a control gate, 112
Indicates a high-concentration p-type impurity region formed in the well region 103 at the junction between the source region 108 and the well region 103.

In FIG. 1, a memory cell for 3 bits is formed on the silicon oxide film 102. Each memory cell is electrically isolated by the silicon oxide film 104. The drain region 1 is sandwiched by the well regions 103.
07 and the source region 108 are formed, and each region is 0.1
To 0.3 μm in depth. p-type impurity region 1
Reference numeral 12 lowers the breakdown voltage at the junction between the source region 108 and the well region 103 to facilitate the writing operation.

The gate insulation 105 has a drain region 107.
To the source region 108 are formed with a film thickness of about 7 nm. Each of the conductor layers 106 is formed with a thickness of about 0.1 μm. Word line 111 functions as a control gate for erasing / writing / reading data for each memory cell.

FIG. 2 shows a perspective view of FIG. 2 here
An example of a memory array having word lines 111 for the number of lines is shown. An insulating film is formed between the two word lines 111, but the illustration is omitted to avoid complexity. The silicon oxide film 102 is formed on the semiconductor substrate 101. The silicon oxide film 102 allows the drain region 107, the well region 103, the source region 108, and the p-type impurity region 1 to be formed.
12 is electrically separated from the semiconductor substrate 101. Further, each of these regions and the silicon oxide film 104 are formed so as to penetrate vertically below the word line 111.

Further, each of these regions and the silicon oxide film 10
Reference numeral 4 denotes a drain region 107, a well region 103, and a source region 1 which are continuously formed in the column direction.
08 is a data line, a well line, and a source line, respectively.

The voltage conditions for the erase operation and the write operation of the memory array having the above structure are shown in FIGS. 3 and 4, respectively. Since both figures have already been described, supplementary items will be described while avoiding duplication of description.

At the time of erasing, a high voltage of 12 V is applied to the word W1 line, but the threshold voltage of the memory cell is 1.
Since it is V (write) and 4 V (erase), the memory cell M
1-1 is turned on. As a result, on the upper surface of the well region just below the gate insulating film of the same memory cell, the impurity polarity p
The mold becomes an inverted n-type and a channel is formed. Therefore, the drain voltage of -5V appears on the source side, and the voltage of the source line S1 becomes about -5V. A channel is similarly formed in the non-selected memory cells M1-2, and a drain voltage of about 2 V appears on the source side. However, since the pn junction between the drain region and the well region is reverse biased, the voltage in the well region does not change.

In this way, the selected memory cell M
In 1-1, the drain, the channel (the upper surface of the well), and the source all become -5V, and the 12V word line W1
There is a voltage difference of about 17V between the and. The capacitive coupling ratio of the memory cell is 0.5 in this embodiment. Therefore, a voltage of about 8.5 V is applied to the gate insulating film. As a result, 7
An electric field of about 12 MV / cm is applied to the gate insulating film of nm, and electrons are injected into the floating gate by the FN phenomenon.
The high voltage of 12 V is supplied to the word line W1 by time division supply which is intermittently made in small steps. Each time the switch is interrupted, the sense amplifier connected to the data line detects the threshold voltage, and the erase operation is continued until the threshold voltage of the memory cell exceeds 3V. The reason for adopting such a supply method is to suppress variations in threshold voltage.

Further, even at the time of writing, in order to suppress variations in threshold voltage, a low voltage of -12 V applied to the word line W1.
Was time-shared. The writing operation is repeated until the threshold voltage becomes 1V and the writing of data is completed.

To realize the above operation, the peripheral circuit shown in FIG. 5 is adopted. In FIG. 5, MBL is a memory cell block (here, the case of two bits of the memory cells M1 and M2 is shown, but not limited to this), MXD is a decoder for applying a voltage to the word lines W1 and W2, and MXD.
P is an internal voltage control circuit for generating a positive high voltage, MXDN
Is an internal voltage control circuit for generating a negative high voltage, SGSC
Is a decoder for controlling the switch element on the source side, SG
DC is a decoder for controlling the switch element on the drain side, SAB detects the voltage of the data line D, and
2 shows a sense amplifier including a latch circuit that supplies a voltage to the.

The word line decoder MXD is a CMOS type pass transistor selector circuit IW1, IW2, an AND circuit for selecting an address input signal XAD, and an EX-NOR (exclusive NOR) circuit for setting an erase / write state. Consists of. In the decoder MXD having such a configuration, the control signal EBWR sets whether the erase / write is selected or not selected for each word line. Internal voltage control circuit M
The XDP converts the power supply voltage Vcc of 3.3V into 12V for erasing and 0V for writing. The internal voltage control circuit MXDN converts the power supply voltage Vcc of 3.3 V into a voltage and outputs 0 V during erasing and -12 V during writing.

At the time of erasing, in the decoder MXD, when the selected word line is the word line W1, the output voltage 12V of the control circuit MXDP is transmitted to the word line W1 via the selector circuit IW1. On the other hand, unselected word line W
The output voltage 0V of the control circuit MXDN is transmitted to 2 via the selector circuit IW2.

In the decoder MXD at the time of writing, when the selected word line is the word line W1, the output voltage of the control circuit MXDN is -12V via the selector circuit IW1.
Are transmitted to the word line W1. On the other hand, the unselected word line W2 is connected to the control circuit MXDP via the selector circuit IW2.
Output voltage of 0V is transmitted.

The decoder SGSC applies a predetermined voltage to the gate line SG2 of the switch element on the source side to control the on / off state of the switch element. By this control, the source line of the memory block MBL is opened at the time of erasing and the writing of the second stage, and is connected to a predetermined voltage supply circuit at the time of the writing of the first stage. Also, the decoder SGDC
Applies a predetermined voltage to the gate line of the switch element SG1 on the drain side to control the on / off state of the switch element SG1. By this control, the data line D of the memory block MBL is connected to the sense amplifier SAB at the time of erasing and the writing of the second stage, and is opened at the time of the writing of the first stage.

As described above, the control circuits MXDP, MXD
N and the decoders SGSC and SGDC generate various voltages according to the respective operating states of erasing / writing / reading (reading operation is not described).
Control signals EEN, EBR, WRBE, EW, WEN, W
BR, ERBW. Although not shown, a well voltage control circuit WCON is prepared, and the switch element and the sense amplifier S of the memory cell block MBL are provided.
A predetermined voltage is applied to the well region of the nMOS transistor used for AB. With the present configuration including the above peripheral circuits, the erase / write operation described above is achieved.

Next, the manufacturing process of the memory cell will be described with reference to FIG. A memory cell is an SOI substrate (Silicon On Ins
formed on the emulator). A silicon oxide film 102 was formed on a semiconductor substrate 101 by an oxygen ion implantation method to form an insulating layer of an SOI substrate. Since the oxygen ion implantation is performed deeply when the silicon oxide film 102 is formed, a thin silicon semiconductor layer remains on the surface of the silicon oxide film 102. The thickness was set to the range of 0.1 to 0.3 μm. Subsequently, boron or boron fluoride ions were implanted into the same layer to make the impurity concentration about 1 × 10 ¹⁷ cm ⁻³ of p-type, and the silicon semiconductor layer 113 was formed (FIG. 6A).

In addition to the above-mentioned ion implantation method, a method of bonding another silicon substrate on a silicon substrate having a silicon oxide film formed on its surface can be adopted. In the same method, after bonding, another silicon substrate is etched and scraped from the surface opposite to the bonding surface to form the silicon semiconductor layer 113.

Subsequently, by selectively performing oxidation,
A silicon oxide film 104 was formed, and a transistor region was separated for each memory cell in different columns. About 7 nm on it
The gate insulating film 105 having the film thickness of was formed using the thermal oxidation method. Further deposit a polycrystalline silicon layer on it,
The floating gate 106 was formed by patterning in parallel with the silicon oxide film 104 (FIG. 6B).

As another method of forming the silicon oxide film 104, the floating gate 106 is formed on the silicon semiconductor layer 113 before forming the same film, and then the nitriding film which is an oxidation resistant film is formed. A method of covering the floating gate 106 with a film and then selectively forming an oxide film by the thermal oxidation method to form the silicon oxide film 104 can be adopted.

After forming the floating gate 106, 1 × 10 5 of arsenic ion is applied to the drain side using the floating gate as a mask.
Implant with a dose of ¹⁵ cm ^-2 , implant boron fluoride with a dose of 1 x 10 ¹⁴ cm ^-2 on the source side, and then implant arsenic ions with a dose of 1 x 10 ¹⁵ cm ^-2 . It was injected at a dose. After the implantation, heat treatment was performed at a temperature of 850 ° C. to form the drain region 107, the high-concentration p-type impurity region 112, and the source region 108. The well region 103 is a remaining portion of the silicon semiconductor layer 113 other than the regions 107, 112, 108 and the silicon oxide film 104. After forming each region, a silicon oxide film 109 was deposited, and the silicon oxide film 109 was removed by an etch-back method until the floating gate 106 appeared (FIG. 6C).

Subsequently, a nitride film and an oxide film were deposited to form an insulating film 110 having a laminated structure, and an n-type impurity-introduced polycrystalline silicon layer was deposited thereon. Then, the polycrystalline silicon layer was patterned in the direction perpendicular to the silicon oxide film 104 to form the word line 111 (FIG. 6).
d). Further, the insulating film 110 and the floating gate 106 are patterned in the same manner as the word line 111, thereby completing the memory cell.

<Embodiment 2> The structure shown in FIG. 1 in which the high-concentration p-type impurity region 112 is omitted is implemented. As shown in FIG. 7, the n-type diffusion layer on the source side and the n-type diffusion layer on the drain side were formed symmetrically. As a result, the breakdown voltage when the reverse voltage is applied to the pn junction between the source region and the well region becomes as high as 6 V or higher, and first, the writing as seen in the case where the source-well breakdown voltage of the embodiment is low. No charge to the well area occurs when plugging. Therefore, as shown in FIG. 8, the well line WE and the source line S corresponding to the data line D on the same column are electrically connected, and then connected to the common source line via the switch element on the source side. did.

The data line D is connected to the main data line D'through the drain side switching element. FIG. 9 is a perspective view of the memory cell cross-sectional structure of the circuit configuration shown in FIG. The configuration between the word line on the common source line side and the switch element is shown. After the silicon oxide film 104 that electrically separates the memory cells of different columns intersects the word line 111 on the common source line side, the n-type diffusion layer 107 region that is the drain region is oxidized to be formed thick. , A silicon oxide film 131. In this region, the electrode 141 is used to electrically connect the source region 108 and the well region 103.

The source region 108 extends to the gate line 133 for the switch element. This region becomes the drain region of the switch element. A gate oxide film 135 is formed immediately below the gate line 133. A well region is formed below it. The well region is electrically isolated from the well region of the memory cell. Further, the source region 132 of the switch element is formed by the n-type diffusion layer.

By using this structure, data can be written in the memory cell without changing the voltage condition at the time of writing shown in FIG. That is, in the first stage write (1), all word lines W
Set the voltage of 1 and W2 to 0V and 4V to the source lines S1 and S2.
Add. Because of the circuit configuration shown in FIG. 8, 4V is also applied to the well lines WE1 and WE2 of each memory cell.
Here, 0 V is supplied to the gate line SG1 of the drain side switching element to turn off the element, and the data line D1,
Open D2.

In the writing (2) in the second stage, 0 V is supplied to the gate line SG2 of the switch element on the source side to turn off the element and the source lines S1 and S2 are opened. Then, voltages of 4V and 0V are applied to the data lines D1 and D2 according to write selection / non-selection. The voltage of the source line S1 and the well line WE1 corresponding to the memory cell M1-1 selected for writing is held at 4V. On the other hand, in the memory cell M1-2 in which writing is not selected, electric charges are extracted via the data line D1, and the source line S2 and the well line WE2 are extracted.
Becomes 0V. In this way, by changing the circuit configuration, the diffusion layer structure of the memory cell can be simplified, and the number of steps can be reduced.

[0053]

According to the present invention, it is possible to use the FN tunnel phenomenon using the entire surface of the gate insulating film for erasing / writing data, so that tunnel emission occurs between the drain and the floating gate. It is not necessary to provide an overlapping part of the. As a result, the drain region can be made almost the same size as the source region, and a memory cell having a gate length of 0.25 μm or less can be formed.

Further, at the time of writing, it is possible to apply a predetermined voltage to each data line, so that the writing operation can be controlled for each memory cell. Therefore, it is possible to keep the variation of the low threshold voltage 1V in the written state within the range of ± 0.25V. As a result, it is possible to prevent the occurrence of read failure due to depletion of the memory cell (a state in which the threshold voltage is in the range of the negative voltage), which is a problem in the electrically rewritable nonvolatile semiconductor memory device.

Further, by the rewriting method using the entire surface of the gate insulating film, it is possible to suppress the injection of holes, which are easily generated at the edge of the diffusion layer, into the gate insulating film. As a result, deterioration of the film can be avoided, and the number of rewritings can be increased.

[Brief description of the drawings]

FIG. 1 is a sectional structural view for explaining a first embodiment of a nonvolatile semiconductor memory device according to the present invention.

FIG. 2 is a perspective view for explaining the structure of the nonvolatile semiconductor memory device described in FIG.

FIG. 3 is a diagram for explaining an erase voltage condition of the nonvolatile semiconductor memory device of the present invention.

FIG. 4 is a diagram for explaining a write voltage condition of the nonvolatile semiconductor memory device of the present invention.

5 is a circuit configuration diagram for explaining a peripheral circuit of the nonvolatile semiconductor memory device described in FIG.

6A to 6C are process diagrams for explaining a method of manufacturing the nonvolatile semiconductor memory device described in FIG.

FIG. 7 is a sectional structural view for explaining a second embodiment of the nonvolatile semiconductor memory device according to the present invention.

FIG. 8 is a circuit diagram illustrating a configuration of a memory cell of the nonvolatile semiconductor memory device described in FIG. 7.

9 is a perspective view for explaining the structure of the nonvolatile semiconductor memory device described in FIG.

[Explanation of symbols]

 101 ... Semiconductor substrate 102, 104, 131 ... Silicon oxide film 103 ... Well region 105 ... Gate insulating film 106 ... Conductor layer 106 107 ... Drain region 108 ... Source region 108 109, 110 ... Insulating film 111 ... Word line 112 ... P-type impurity region 113 ... Silicon semiconductor layer 132 ... N-type diffusion layer region 133 ... Gate line 135 ... Gate Oxide film 141 ... Electrode D ... Data line M ... Memory cell S ... Source line SG ... Gate line W ... Word line WE ... Well line

Claims (8)

[Claims] 1. A control gate, a floating gate, a gate insulating film,
A plurality of memory cells each including a MOS field effect transistor having at least a well region, a drain region and a source region are arranged in a matrix on a semiconductor substrate,
Control gates are connected to each other by individual word lines for each row, drain regions are connected to each other by individual data lines for each column, and source regions are connected to each other by individual source lines for each column. In a semiconductor memory device composed of parallel-connected memory arrays configured by connecting, an insulating layer region for electrically isolating well regions of memory cells on adjacent columns from each other is formed between the memory cells. Further, the well regions of the memory cells on the same column are connected to each other by a well line, and means for individually supplying a voltage to the well region is provided for each column. Nonvolatile semiconductor memory device. 2. The semiconductor substrate is an SOI (Silicon On I)
2. The non-volatile semiconductor memory device according to claim 1, wherein the non-volatile semiconductor memory device is formed of a semiconductor substrate. 3. The means for supplying the voltage serves to supply a voltage to the well region via the junction between the well region and the drain region, and the junction between the well region and the drain region. Means for functioning to supply a voltage to the well region through the well region, and the well region of the memory cells on the same column constitutes a floating region which is not connected to the other, and the source The line is connected to a common source line for all memory cells via a switch element composed of a MOS transistor, and the data line is
3. The non-volatile semiconductor memory device according to claim 1 or 2, wherein the latch circuit for supplying a predetermined voltage to a drain region is connected via another switch element composed of a MOS transistor. 4. The nonvolatile semiconductor memory device according to claim 3, wherein an electric breakdown voltage between the source region and the well region is approximately 3 V or less. 5. The nonvolatile semiconductor memory device according to claim 4, wherein the boron impurity concentration of the well region at the junction between the source region and the well region is 5 × 10 ¹⁷ cm ⁻³ or more. 6. In the case of data erasing, a voltage that is positive to the voltage of the well region supplied from the drain region is applied to the word line, and in the case of data writing, the well region supplied from the source region is supplied. A voltage that is negative with respect to the voltage is applied to the word line, the same voltage as the well region voltage is applied to the data line of the write selected memory cell, and the well region is applied to the data line of the write unselected memory cell. 4. The non-volatile semiconductor memory device according to claim 3, further comprising means for applying a negative voltage to the voltage of. 7. The means for supplying the voltage is provided between the well line and the source line, and the means for supplying the voltage to the well region via the junction between the well region and the drain region. Means for supplying a voltage to the well region through the connected electrodes, and the source line is connected to a common source line for all memory cells via a switching element composed of a MOS transistor. 3. The data line according to claim 1 or 2, wherein the data line is connected to a latch circuit for supplying a predetermined voltage to a drain region via another switch element formed of a MOS transistor. Nonvolatile semiconductor memory device. 8. In the case of data erasing, a voltage which is positive with respect to the voltage of the well region supplied from the drain region is applied to the word line, and in the case of data writing, a predetermined voltage is applied to the well region via the source line. Is applied in advance to the word line and a voltage that is negative with respect to the same voltage is applied to the word line, and the same voltage as that of the well line is applied to the data line of the memory cell selected for writing, and the memory cell not selected for writing. 8. The non-volatile semiconductor memory device according to claim 7, further comprising means for applying a voltage that is negative to the voltage of the well line to the data line.