JPH09116022A - Cmos integrated circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To detect the occurrence of a latch-up by providing a contact region between an N-channel MOSFET and a P-well contact, and providing an electrode terminal connected to this contact region, and a resistance component between a P-well contact and the contact region. SOLUTION: This CMOS integrated circuit is composed of a P-channel MOSFET 100 and an N-channel MOSFET 200. Between the N-channel MOSFET 200 and a P-well contact 12 connected to GND a contact region 18 being a P-type heating doped region is provided. An electrode is formed in this contact region 18 to make it a latch-up monitor terminal 16. And in the P-well region 3 between the contact region 18 and a P-well contact 12, a resistance component R4 is provided as a diffusion resistor R17.

Description

Detailed Description of the Invention

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a CMOS integrated circuit, and more particularly to a CMOS integrated circuit having a latch-up detection function.

[0001]

2. Description of the Related Art Conventionally, in this type of technology, a P-channel MOSFET and an N-channel MOSFE are formed on the same semiconductor substrate.
T and T are integrated to form a CMOS integrated circuit.

Referring to FIG. 3, in a conventional CMOS integrated circuit, an N well region 2 and a P well region 3 are formed on a semiconductor substrate 1. A source 4 and a drain 5 are formed in the N well region 2 by implanting P type impurities such as boron. A gate electrode 6 is formed on the substrate surface between the source 4 and the drain 5 via an oxide film to form a P-channel MOSF.
Configure ET100. Into the P well region 3, N type impurities such as arsenic are implanted to form the source 7 and the drain 8. A gate electrode 9 is formed on the surface of the substrate between the source 7 and the drain 8 via an oxide film to form an N-channel MOS.
The FET 200 is configured. The N well region 2 is connected to the power supply VDD via the N well high concentration impurity layer 11. P
The well region 3 is G through the P well high concentration impurity layer 12
Connected to ND.

A CMOS integrated circuit is a P channel MOSFE.
A pair of T100 and N-channel MOSFET 200,
Since it is formed in the adjacent area on the same substrate, parasitic PN
A P transistor and an NPN transistor are formed. That is, a PNP transistor Q1 having the source 4 of the P-channel MOSFET as the emitter, the N-well region 2 as the base, and the semiconductor substrate 1 as the collector is formed. A PNP transistor Q2 having the drain 5 of the P-channel MOSFET as the emitter, the N-well region 2 as the base, and the semiconductor substrate 1 as the collector is formed. N
An NPN transistor Q3 having the source 7 of the channel MOSFET as the emitter, the P well region 3 as the base, and the N well region 2 as the collector is formed. An N-channel MOSFET having a drain 8 as an emitter, a P-well region 3 as a base, and an N-well region 2 as a collector N
A PN transistor Q4 is formed. Further, a parasitic resistance R2 is formed between the N well region 2 and VDD, and P
A parasitic resistance R3 is formed between the well region 3 and GND.

Referring to FIG. 4, latch-up of a CMOS integrated circuit is triggered by noise applied to an output terminal voltage VOUT. Latch-up of the CMOS integrated circuit is also caused by noise applied to the power supply voltage, a substrate current flowing from the N-channel MOS or electron-hole pairs generated by radiation. When the output terminal voltage VOUT becomes higher than VDD, a trigger current is injected from the emitter of the PNP transistor Q2. A voltage drop occurs due to this current flowing through the parasitic resistance R3. This voltage drop causes the transistor Q
The base potential of 4 rises and the transistor Q4 is turned on. When the transistor Q4 is turned on, the collector current of Q4 flows through the parasitic resistance R2 and the voltage drop causes the base potential of the transistor Q1 to drop, turning on the transistor Q1. When both the transistors Q1 and Q4 are turned on, the transistor is stably turned on even if the trigger from the output terminal is removed. As described above, when latch-up occurs, a large current continues to flow between VDD and GND, and finally the CMOS integrated circuit itself is thermally damaged.

For example, Japanese Patent Laid-Open No. 5-335500 discloses a technique of reducing a latch-up due to a trigger voltage applied to an output terminal of a CMOS integrated circuit by adding a resistance component in series to the source side of a MOS transistor. Is listed.

[0006]

In the above-mentioned prior art,
There was no way to detect the occurrence of latchup. Therefore, after the CMOS integrated circuit was destroyed, it was only necessary to infer whether or not the cause was latch-up.

It is an object of the present invention to provide a device structure for detecting latchup in CMOS integrated circuits. Another object of the present invention is to provide means for preventing latch-up using this device structure.

[0008]

In order to solve the above problems, a CMOS integrated circuit of the present invention has an N channel MOSFET and a P well contact region on a semiconductor substrate,
C in which the P-well contact region is connected to a power source
A MOS integrated circuit, comprising the N-channel MOSFET
A contact region provided between the P-well contact region and the P-well contact region, an electrode terminal connected to the contact region, and a resistance component between the P-well contact region and the contact region. To do.

Another CMOS integrated circuit of the present application is a CMOS integrated circuit having a P-channel MOSFET and an N well contact region on a semiconductor substrate, and the N well contact region is connected to a power source. It includes a contact region provided between the P-channel MOSFET and the N well contact region, an electrode terminal connected to the contact region, and a resistance component between the N well contact region and the contact region. It is characterized by

In another CMOS integrated circuit of the present invention, the resistance component is a diffusion resistance.

Another CMOS integrated circuit of the present invention is an N-channel MOSFET and a P-channel MOSFET.
Is a CMOS integrated circuit formed on the same substrate, wherein the latch-up detection means for detecting the occurrence of latch-up, and the signal output from the latch-up detection means supply power to the CMOS integrated circuit. And means for stopping.

Further, in another CMOS integrated circuit of the present invention, a latch-up detecting means for detecting occurrence of latch-up by an input from the electrode terminal, and a signal output from the latch-up detecting means, And a means for stopping the power supply.

[0013]

BEST MODE FOR CARRYING OUT THE INVENTION Next, an embodiment of a CMOS integrated circuit of the present invention will be described in detail with reference to the drawings.

Referring to FIG. 1, a CMOS integrated circuit according to an embodiment of the present invention includes a P-channel MOSFET 100.
And an N-channel MOSFET 200. Elements common to those of the conventional CMOS integrated circuit shown in FIG. 3 are designated by common reference numerals.

In the N well region 2, an N well contact 11 which is an N type high concentration impurity region is provided. The N well contact 11 fixes the N well region 2 to the VDD potential by electrically connecting to the VDD. N well contact 11 and P channel MOSFE
A contact region 15, which is an N-type high-concentration impurity region, is provided between T100 and T100, and an electrode is formed there to serve as a latch-up detection terminal 13. A resistance component R1 is formed as a diffusion resistance 14 in the N well region between the N well contact 11 and the contact region 15.

Next, the operation of the embodiment of the present invention will be described in detail with reference to the drawings.

Referring to FIG. 2, the output terminal voltage VOUT
When 10 becomes higher than VDD, a trigger current is injected from the emitter of PNP transistor Q2. A voltage drop occurs due to this current flowing through the parasitic resistance R3. This voltage drop raises the base potential of the transistor Q4 and turns on the transistor Q4. When the transistor Q4 is turned on, the collector current IC of Q4 flows through the resistance component R1 and the parasitic resistance R2. At this time, a voltage drop of R1 × IC appears at the latch-up detection terminal 13. Since the collector current of Q4 flows only when latch-up occurs, the occurrence of latch-up can be detected by the voltage drop of R1 × IC.

As described above, in the embodiment of the present invention, the N-well contact 11 and the latch-up detection terminal 13 are provided in the N-well region 2, and the diffusion between the N-well contact 11 and the latch-up detection terminal 13 is performed. By providing the resistor 14, it is possible to detect the occurrence of latch-up.

The above discussion is based on the N-channel MOSFET 2
00 and a P-well contact 12 connected to GND, a contact region 18 which is a P-type high-concentration impurity region is provided, and an electrode is formed in this contact region 18 to serve as a latch-up monitor terminal 16. The same applies when the resistance component R4 is provided as the diffusion resistance 17 in the P well region between the P well contact 12.

Next, an embodiment of the latch-up prevention circuit by the CMOS integrated circuit of the present invention will be described with reference to the drawings.

Referring to FIG. 5, the latch-up prevention circuit 50 of the second embodiment detects a minute voltage fluctuation,
It comprises a sense amplifier circuit 51 for amplification and a power supply control circuit 52 capable of cutting off the power supply by a latch-up detection signal 53 from the sense amplifier circuit 51. The sense amplifier circuit 51 receives the output of the latch-up detection terminal 13 of the CMOS integrated circuit as an input. VREF is a reference potential, and is amplified when the input potential from the latch-up detection terminal 13 of the CMOS integrated circuit falls below this reference potential. The power supply control circuit 52 includes a latch circuit 55 and a power supply control MOSFET 56.

When latch-up occurs, the resistance component R1
Current begins to flow. When the value of this current is I, a voltage drop of R1 × I occurs in the resistance component R1. When this voltage drop is input to the sense amplifier circuit 51, the sense amplifier circuit 51 amplifies a minute change in voltage generated in the resistance component R1 and the latch-up detection signal 5 which is a logical signal.
Convert to 3. The latch-up detection signal 53 is input to the latch circuit 55 in the power supply control circuit 52. When the latch-up detection signal 53 becomes 1, the latch circuit 55 turns off the MOSFET 56 for power supply control, and the CMO
The power supply VDD of the S integrated circuit is lowered to 0V to stop the latch-up.

As described above, in the embodiment of the latch-up prevention circuit by the CMOS integrated circuit of the present invention, the sense amplifier circuit 51 which detects the voltage drop of the resistance component R1 and outputs the latch-up detection signal 53 and the power supply are cut off. The provision of the power supply control circuit 52 that can prevent the latch-up can be prevented before the destruction of the CMOS integrated circuit occurs.

[0024]

As is apparent from the above description, according to the present invention, the N-well contact and the latch-up detection terminal are provided in the N-well region, and the resistance component is provided between the N-well contact and the latch-up detection terminal. By providing the above, it is possible to detect the occurrence of latch-up.

Further, by detecting the latch-up and stopping the voltage applied to the CMOS integrated circuit, the latch-up can be prevented before the destruction of the CMOS integrated circuit occurs.

[Brief description of the drawings]

FIG. 1 is a sectional view showing an embodiment of a CMOS integrated circuit of the present invention.

FIG. 2 is a diagram showing an equivalent circuit of a CMOS integrated circuit according to an embodiment of the present invention.

FIG. 3 is a sectional view showing an example of a conventional CMOS integrated circuit.

FIG. 4 is a diagram showing an example of an equivalent circuit of a conventional CMOS integrated circuit.

FIG. 5 is a diagram showing a latch-up prevention circuit according to a second embodiment of the present invention.

[Explanation of symbols]

 100 P-channel MOSFET 200 N-channel MOSFET 1 Semiconductor substrate 2 N-well region 3 P-well region 4 Source 5 Drain 6 Gate electrode 7 Source 8 Drain 9 Gate electrode 10 VOUT 11 N-well contact 12 P-well contact 13, 16 Latch-up detection terminal 14, 17 Diffusion resistance 15, 18 Contact area 50 Latch-up prevention circuit 51 Sense amplifier circuit 52 Power supply control circuit 53 Latch-up detection signal 55 Latch circuit 56 MOSFET for power supply control

Claims (5)

[Claims] 1. An N-channel MOSFET on a semiconductor substrate
And a P-well contact region, wherein the P-well contact region is connected to a power source, a contact region provided between the N-channel MOSFET and the P-well contact region, A CMOS integrated circuit comprising: an electrode terminal connected to a region; and a resistance component between the P well contact region and the contact region. 2. A P-channel MOSFET on a semiconductor substrate
And a N-well contact region, wherein the N-well contact region is connected to a power supply, and a contact region provided between the P-channel MOSFET and the N-well contact region, A CMOS integrated circuit comprising: an electrode terminal connected to a region; and a resistance component between the N well contact region and the contact region. 3. The CMOS integrated circuit according to claim 1, wherein the resistance component is a diffusion resistance. 4. An N-channel MOSFET and a P-channel M
CMO formed by forming OSFET and the same substrate
In the S integrated circuit, the latch-up detecting means for detecting the occurrence of latch-up, and the signal output from the latch-up detecting means are used for C
A CMOS integrated circuit comprising means for stopping power supply to a MOS integrated circuit. 5. A latch-up detecting means for detecting the occurrence of latch-up by an input from the electrode terminal, and a signal output from the latch-up detecting means for C
3. The CM according to claim 1, further comprising means for stopping power supply to the MOS integrated circuit.
OS integrated circuit.