JPH09115284A - Semiconductor memory - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent the reliability in a high integration from being lowered and to speed up the access and word line resetting by respectively providing a word line driving circuit and a word line resetting circuit at one end and at the other end of a word line. SOLUTION: A word line driving circuit 30 consisting of a P channel field effect transistor 59 and a word line resetting circuit 37 consisting of an N channel field effect transistor 46 are respectively provided at one end and the other end of a word line WLOO. When a word line selection signal SELOX is inputted, the word line is raised by a driving signal WDOZ and reliability is enhanced by suppressing that a junction, in which a voltage exceeding a boosted voltage is impressed, is formed. Moreover, the access and word line resetting can be speeded up by making the raising and the falling of the word line faster while arranging the P channel FET 59 near a cell array 18 and arranging the N channel FET farther from the cell array and while making the wiring resistance between the FET and the word line smaller.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device having a structure for raising a word line by using a P-channel field effect transistor.

[0002]

2. Description of the Related Art Conventionally, as an example of a semiconductor memory device, a part of a dynamic random memory having a structure as shown in FIG.
An access memory (hereinafter referred to as DRAM) has been proposed. This portion includes a cell array region 1 in which memory cells are arranged, a word line 2 for selecting a memory cell, a word line driving circuit 3 for driving the word line 2, and an inverter 4 connected as shown in FIG. And nMOS transistors 5 to 7.

In FIG. 5, WDZ represents a word line drive signal and SELX represents a word line selection signal. In the word line drive signal WDZ, the low potential is the ground voltage Vss, and the high potential is the voltage Vpp obtained by boosting the power supply voltage Vcc.
It is. On the other hand, in the word line selection signal SELX, the low potential is the ground voltage Vss and the high potential is the power supply voltage Vcc. Further, VSRZ indicates a fixed voltage of Vcc + Vth or less, where Vth is the threshold voltage of the nMOS transistor 5.

FIG. 6 shows the word line 2 in the DRAM.
5 is a waveform diagram for explaining the selection operation of FIG. In the figure,
The voltage waveform of the word line selection signal SELX, the voltage waveform of the word line drive signal WDZ, the voltage waveform of the node 8 and the voltage waveform of the word line 2 are shown.

That is, in the above DRAM, when the word line 2 is not selected, the level of the word line selection signal SELX is Vc.
c, the level of the word line drive signal WDZ is Vss, the output level of the inverter 4 is Vss, and the level of the node 8 is Vs.
The s, nMOS transistor 6 is non-conductive, the nMOS transistor 7 is conductive, and the level of the word line 2 is Vss.
It has been.

When the word line 2 is selected from this state, the level of the word line selection signal SELX is lowered to Vss, the nMOS transistor 7 is turned off, and the output level of the inverter 4 rises to Vcc. Is
The nMOS transistor 5 precharges the node 8 to the level of Vcc-α.

Next, the level of the word line drive signal WDZ is raised to Vpp. In this case, since the channel is formed in the nMOS transistor 6, the voltage of the node 8 is between the channel and gate of the nMOS transistor 6. It is self-boosted by the capacity of and rises to the level of Vpp + α. As a result, the voltage of the word line 2 rises to the level of Vpp following the word line drive signal WDZ.

After that, when the word line 2 is reset, the level of the word line drive signal WDZ falls toward Vss, and the charges accumulated in the word line 2 are nMOS.
It is pulled out to the word line drive signal line side through the transistor 6. As a result, the voltage of the word line 2 starts to fall following the word line drive signal WDZ.

Further, the level of the word line drive signal WDZ is V
When ss is reached, the level of the word line selection signal SELX is raised to Vcc next. As a result, the output level of the inverter 4 becomes Vss, and the charge accumulated in the node 8 is extracted to the ground side via the nMOS transistor 5 and the inverter 4. As a result, the level of the node 8 is set to Vss and the nMOS transistor 6 is turned off.

In this case, the nMOS transistor 7 is rendered conductive, and the charge remaining on the word line 2 is nM.
Since it is pulled out to the ground side through the OS transistor 7, the level of the word line 2 is set to Vss. However, in the above DRAM, the N-type diffusion layer and the P-type diffusion layer forming the drain or the source of the nMOS transistor 5 on the node 8 side are formed.
Since a voltage exceeding Vpp is applied to the junction with the well, there is a problem that the reliability of the DRAM decreases as the DRAM becomes highly integrated.

Therefore, in order to solve this problem, a DRAM having a structure partially shown in FIG. 7 has been conventionally proposed. This portion includes a cell array region 10 in which memory cells are arranged, a word line 11, and a word line drive circuit 12 for driving the word line 11, which are connected as shown in FIG.
A pMOS transistor 13, nMOS transistors 14 and 15, and a wiring resistance 16 between the word line 11 and the drain of the nMOS transistor 14.

FIG. 8 is a waveform diagram for explaining the operation of selecting word line 11 in the DRAM shown in FIG. In FIG. 8, the voltage waveform of the word line selection signal SELX and the voltage waveform of the word line 11 are shown. DRA shown in FIG.
In M, when the word line 11 is not selected, the level of the word line selection signal SELX is Vpp, the pMOS transistor 13 is non-conductive, the nMOS transistor 15 is conductive, and the level of the word line 11 is Vss. When the word line 11 is selected from this state, the level of the word line selection signal SELX is lowered to Vss,
The pMOS transistor 13 is turned on, and the nMOS
The transistor 15 is turned off. Further, the voltage level of the word line 11 is raised to Vpp via the pMOS transistor 13.

After that, when the word line 11 is reset,
The level of the word line selection signal SELX is raised to Vpp, the pMOS transistor 13 is turned off,
The nMOS transistor 15 is rendered conductive. Further, the charges accumulated in the word line 11 are extracted to the ground side via the nMOS transistors 14 and 15, and the word line 1
The voltage level of 1 is lowered to Vss.

As described above, in the DRAM shown in FIG.
Since there is no junction that raises the potential level to pp or higher, reliability can be ensured even when the DRAM is highly integrated.

[0015]

However, D shown in FIG.
In the RAM, when the access speed is to be increased, p is important in order to emphasize the rising speed of the word line 11.
It is necessary to arrange the MOS transistor 13 near the cell array region 10. Therefore, the nMOS transistors 14 and 15 have to be arranged at positions far from the word line 11 with the pMOS transistor 13 interposed therebetween.

However, if the above arrangement is adopted,
The length of the wiring connecting between the word line 11 and the drain of the nMOS transistor 14 becomes long, and the wiring resistance 16 becomes large. Therefore, the fall of the word line 11 is extremely delayed due to the wiring resistance 16, which causes a new problem that the reset speed of the word line 11 cannot be increased.

On the other hand, when the nMOS transistors 14 and 15 are arranged near the cell array region 10 and the pMOS transistor 13 is arranged far from the cell array region 10 with the nMOS transistors 14 and 15 interposed therebetween, the word line 11 is reset. However, the rise of the word line 11 is extremely delayed, and the access cannot be speeded up.

In view of the above problems, therefore, the present invention does not form a junction to which a voltage exceeding the boosted voltage is applied, and does not reduce reliability even when high integration is achieved without decreasing reliability of access and word lines. An object of the present invention is to provide a semiconductor memory device that can be reset at high speed.

[0019]

SUMMARY OF THE INVENTION The above-mentioned problems are solved by the word line drive circuit for raising the word line by using a P-channel field effect transistor on one end side of the word line, and the other end side of the word line. Can be achieved by a semiconductor memory device having a word line reset circuit for lowering the word line using an N-channel field effect transistor.

According to the present invention, since the word line is activated by using the P-channel field effect transistor, it is possible to prevent the formation of a junction to which a voltage exceeding the boosted voltage is applied. When the word line drive circuit is provided on one end side of the word line and the word line reset circuit is provided on the other end side of the word line, the P-channel field effect transistor for raising the word line and the word line and the word line Since it is possible to prevent a large wiring resistance from existing between the N-channel field-effect transistor that causes the line to fall and the word line, it is possible to speed up the rise and fall of the word line.

[0021]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below.
A description will be given together with the embodiments shown in FIGS.

[0022]

1 is a circuit diagram showing a partial configuration of an embodiment of a semiconductor memory device according to the present invention. In this embodiment, the present invention is applied to DRAM. D shown in FIG.
A part of the RAM is connected as shown in the drawing, the cell array region 18, redundant word lines RWL0 and RWL1, and regular word lines (hereinafter simply referred to as word lines) WL00 and W.
L01, WL02, WL03, WL10 and bit line B
LX and BLZ, redundant memory cells 19 and 20, and regular memory cells (hereinafter,
Memory cells) 21 to 25. In addition, the redundant word line drive circuits 26 and 27 are operated by the redundant word line RWL0.
The redundant word line drive circuits 28 and 29 drive the redundant word line RWL1. The word line drive circuit 30 drives the word line WL00, the word line drive circuit 31 drives the word line WL01, the word line drive circuit 32 drives the word line WL02, and the word line drive circuit 33 drives the word line W.
L03 is driven, and the word line drive circuit 34 drives the word line WL.
Drive ten.

The redundant word line reset circuit 35 resets the redundant word line RWL0, and the redundant word line reset circuit 36 resets the redundant word line RWL1.
The word line reset circuit 37 resets the word line WL00, and the word line reset circuit 38 resets the word line W.
The word line reset circuit 39 resets the word line WL02, the word line reset circuit 40 resets the word line WL03, and the word line reset circuit 41 resets the word line WL10. The reset circuits 35 to 41 are composed of two corresponding nMOS transistors of the nMOS transistors 42 to 55, respectively.

In FIG. 1, WD0Z to WD3Z are word line drive signals, SEL0X and SEL1X are word line selection signals, SELR0X is a redundant word line selection signal, and RE.
S0Z to RES3Z represent word line reset signals. Word line drive signals WD0Z to WD3Z, word line selection signals SEL0X, SEL1X and redundant word line selection signal SE.
LR0X has a low potential as the ground voltage Vss and a high potential as the boosted voltage Vpp obtained by boosting the power supply voltage Vcc. In addition, word line reset signals RES0Z to RES3
Z has a low potential as the ground voltage Vss and a high potential as the power supply voltage Vcc.

FIG. 2 shows redundant word line drive circuits 26 and 27.
3 is a circuit diagram showing an example of a configuration of a circuit portion including a word line drive circuit 30 and a word line drive circuit 30. FIG. The circuit portion shown in FIG. 2 has pMOS transistors 57 to 59 connected as shown.
And nMOS transistors 60 to 62.

Other redundant word line drive circuits 28, 29
Also, the word line drive circuits 31 to 34 have the same configuration as the corresponding portion of the circuit portion shown in FIG. Although FIGS. 1 and 2 are circuit diagrams, they also show a schematic layout on a plan view of the DRAM, as will be described later.

For example, the word line WL00 has a row address R
A0 to RA4 are set to "00000" and the word line WL0
1, the row addresses RA0 to RA4 are set to "10000". In addition, the word line WL02 has row addresses RA0-R.
A4 is set to "01000", and the word line WL03 has row addresses RA0 to RA4 set to "11000".
That is, n is an integer and i = 0, 1 ,. . . , N, the row address RA0 differs between the word line WLi0 and the word line WLi1, but the row addresses RA1 to RA4 are the same. Although the row address RA0 differs between the word line WLi2 and the word line WLi3, the row addresses RA1 to RA1
RA4 is the same.

In this embodiment, when the memory cells including the memory cells 21 to 25 have no defect and the redundant memory cells including the redundant memory cells 19 and 20 are not used, the row addresses RA0 and RA1 are used. As "0
When "0" is designated, first, the word line reset signal RE
S0Z falls, then word line drive signal WD0Z
Stand up.

The row addresses RA0 and RA1 are "1".
When "0" is designated, first, the word line reset signal RE
S1Z falls, then word line drive signal WD1Z
Stand up. The row address RA0, RA1 is "0.
When "1" is designated, first, the word line reset signal RE
S2Z falls, then word line drive signal WD2Z
Stand up.

Further, when "11" is designated as the row address RA0, RA1, the word line reset signal RES3Z first falls and then the word line drive signal WD.
3Z stands up. On the other hand, in this embodiment, when the redundant memory cell is used, the word lines WLi0 and WLi1 or the word lines WLi2 and WLi3 are set to the redundant word line RWL.
0, replace with RWL1. Therefore, in the case of using the redundant memory cell, when "00" is designated as the row addresses RA0 and RA1, the word line reset signal RES0Z first falls, and then the word line drive signal W
D0Z and WD2Z rise.

The row addresses RA0 and RA1 are "1".
When "0" is designated, first, the word line reset signal RE
S1Z falls, then word line drive signal WD1
Z and WD3Z start up. Row address RA0, RA1
When "01" is designated as, the word line reset signal RES2Z first falls, and then the word line drive signals WD0Z and WD2Z rise.

Further, when "11" is designated as the row address RA0, RA1, the word line reset signal RES3Z first falls and then the word line drive signal WD.
1Z and WD3Z start up. FIG. 3 is a waveform diagram for explaining the operation of the DRAM when the word line WL00 is selected when the redundant memory cell is not used.
In the figure, word line reset signals RES0Z to RES3
Z, word line selection signals SEL0X, SEL1X, word line drive signal WD0Z, redundant word line selection signal SELR0
The voltage waveforms of X and the word line WL00 are shown.

In this case, when the word line WL00 is not selected, the levels of the word line selection signals SEL0X and SEL1X and the redundant word line selection signal SELR0X are Vpp, and the levels of the word line reset signals RES0Z to RES3Z are V.
The level of the cc and word line drive signal WD0Z is Vss. Therefore, the redundant word line drive circuits 26 to 29 are provided.
In the word line drive circuits 30 to 34, the pMOS
The transistor becomes non-conductive and the nMOS transistor becomes conductive. In addition, the redundant word line reset circuit 3
5, 36 and the word line reset circuits 37 to 41, the nMOS transistors 42 to 55 are turned on, and the redundant word lines RWL0, RWL1 and the word line WL.
The levels of 00 to WL03 and WL10 are set to Vss.

From this state, when the word line WL00 is selected, the row addresses RA0 and RA1 are set to "0".
"0" is designated, and the level of the word line reset signal RES0Z falls to Vss. As a result, the nMOS transistor 42 of the redundant word line reset circuit 35 and the nMOS transistors 47 and 55 of the word line reset circuits 37 and 41 are turned off.

Then, the level of the word line selection signal SEL0X is lowered to Vss and the level of the word line drive signal WD0Z is raised to Vpp. As a result, in the word line drive circuit 30, the pMOS transistor 59 is rendered conductive, the nMOS transistor 62 is rendered non-conductive, and the level of the word line WL00 rises to Vpp following the word line drive signal WD0Z.

When the word line WL00 is reset, the level of the word line reset signal RES0Z rises to Vcc and the level of the word line drive signal WD0Z rises to Vcc.
You can drop to ss. As a result, the charges accumulated in the word line WL00 are pMO of the word line drive circuit 30.
NMO of the word line reset circuit 37 while being pulled out to the word line drive signal line side through the S transistor 59.
It is pulled out to the ground side through the S transistors 46 and 47. Therefore, the level of the word line WL00 falls toward Vss.

When the level of the word line WL00 becomes Vcc or less, the level of the word line selection signal SEL0X becomes Vpp.
To pM in the word line drive circuit 30.
The OS transistor 59 is turned off and the nMOS transistor 62 is turned on. As a result, the electric charge remaining on the word line WL00 is transferred to the word line drive circuit 3
It is pulled out to the ground side through the nMOS transistor 62 of 0 and the nMOS transistors 46 and 47 of the word line reset circuit 37, and the level of the word line WL00 is lowered to Vss and clamped to Vss.

FIG. 4 shows DR when word line WL00 is selected when word lines WL00 and WL01 are replaced by redundant word lines RWL0 and RWL1.
It is a waveform diagram for explaining the operation of the AM. In the figure, word line reset signals RES0Z to RES3Z, word line selection signals SEL0X and SEL1X, word line drive signal W
D0Z to WD3Z, redundant word line selection signal SELR0X
And the voltage waveform of the redundant word line RWL0 is shown.

Also in this case, when the word line WL00 is not selected, the word line selection signals SEL0X and SEL1X are selected.
And the level of the redundant word line selection signal SELR0X is Vp
p, the level of the word line reset signals RES0Z to RES3Z is Vcc, and the level of the word line drive signals WD0Z to WD3Z is Vss. Therefore, in the redundant word line drive circuits 26 to 29 and the word line drive circuits 30 to 34, the pMOS transistors are turned off,
The nMOS transistor is rendered conductive. In the redundant word line reset circuits 35 and 36 and the word line reset circuits 37 to 41, the nMOS transistors 42 to
55 is rendered conductive and redundant word lines RWL0, RWL
The level of 1 and the word lines WL00 to WL03, WL10 is set to Vss.

From this state, when the word line WL00 is selected, the row addresses RA0 and RA1 are set to "0".
"0" is designated, and the level of the word line reset signal RES0Z falls to Vss. As a result, the nMOS transistor 42 of the redundant word line reset circuit 35 and the nMOS transistors 47 and 55 of the word line reset circuits 37 and 41 are turned off.

Then, the redundant word line selection signal SELR0 is selected.
The level of X is lowered to Vss and the levels of the word line drive signals WD0Z and WD2Z are raised to Vpp. Therefore, the redundant word line selection circuits 26 and 27
, The pMOS transistors 57 and 58 are rendered conductive, and the nMOS transistors 60 and 61 are rendered non-conductive. The level of the redundant word line RWL0 rises to Vpp following the word line drive signals WD0Z and WD2Z.

When the word line WL00 is reset, the level of the word line reset signal RES0Z is Vcc.
And the word line drive signal WD0Z,
The level of WD2Z is lowered toward Vss.
As a result, the charges accumulated in the redundant word line RWL0 are extracted to the word line drive signal line side through the pMOS transistors 57 and 58 of the redundant word line drive circuits 26 and 27, and the redundant word line reset circuit 35 is also discharged. nM
It is pulled out to the ground side through the OS transistors 42 and 43. Further, the level of the redundant word line RWL0 is lowered toward Vss.

When the level of the redundant word line RWL0 becomes Vcc or less, the level of the redundant word line selection signal SELR0X is raised to Vpp. In the redundant word line drive circuits 26 and 27, the pMOS transistors 57,
58 is turned off, and the nMOS transistor 60,
61 is made conductive. Therefore, the redundant word line RW
The electric charge remaining in L0 is due to the redundant word line drive circuit 2
6, 27 nMOS transistors 60, 61 and the redundant word line reset circuit 35 nMOS transistors 42,
It is pulled out to the ground side via 43. Further, the level of the redundant word line RWL0 is lowered to Vss and clamped to Vss.

When the word lines WL02 and WL03 are replaced with the redundant word lines RWL0 and RWL1, when the word line WL02 is selected, the row address RA is selected.
"01" is designated as 0 and RA1, and the level of the word line reset signal RES2Z falls to Vss.
As a result, the nMOS transistor 43 of the redundant word line reset circuit 35 and the nMO transistor of the word line reset circuit 39.
The S transistor 51 is turned off.

Then, the redundant word line selection signal SELR0 is selected.
The level of X is lowered to Vss and the levels of the word line drive signals WD0Z and WD2Z are raised to Vpp. Therefore, the redundant word line drive circuits 26 and 27
, The pMOS transistors 57 and 58 are rendered conductive, and the nMOS transistors 60 and 61 are rendered non-conductive. The level of the redundant word line RWL0 rises to Vpp following the word line drive signals WD0Z and WD2Z.

When the word line WL00 is reset, the level of the word line reset signal RES2Z is Vcc.
And the word line drive signal WD0Z,
The level of WD2Z is lowered toward Vss.
As a result, the charges accumulated in the redundant word line RWL0 are extracted to the word line drive signal line side through the pMOS transistors 57 and 58 of the redundant word line drive circuits 26 and 27, and the redundant word line reset circuit 35 is also discharged. nM
It is pulled out to the ground side through the OS transistors 42 and 43. Further, the level of the redundant word line RWL0 is lowered toward Vss.

When the level of redundant word line RWL0 becomes Vcc or lower, the level of redundant word line selection signal SELR0X is raised to Vpp. In the redundant word line drive circuits 26 and 27, the pMOS transistors 57,
58 becomes non-conductive, and the nMOS transistor 60,
61 becomes conductive. Therefore, the redundant word line RWL
The charges remaining in 0 are stored in the redundant word line drive circuit 26,
27 nMOS transistors 60 and 61 and redundant word line reset circuit 35 nMOS transistors 42 and 43.
Is pulled out to the ground side via. Also, word line WL00
Is lowered to Vss and clamped to Vss.

As described above, according to this embodiment, the pMOS
Since the word line or the redundant word line is activated by using a transistor, a junction to which a voltage exceeding the boosted voltage Vpp is applied is not formed, and reliability is prevented from being lowered even when the DRAM is highly integrated. can do.

By the way, in this embodiment, the pMOS transistors of the redundant word line drive circuits 26 to 29 and the word line drive circuits 30 to 34 in FIG. 1 and FIG. 2 are arranged near the cell array region 18, and the nMOS transistors are formed. Cell array region 1 with a pMOS transistor in between
It can be arranged at a position far from 8. Such a p
If the arrangement of the MOS transistor and the nMOS transistor is adopted, a large wiring resistance is generated between the pMOS transistor for raising the redundant word line and the redundant word line and between the pMOS transistor for raising the word line and the word line. You can avoid it. Therefore, it is possible to speed up the activation of the redundant word line and the word line and speed up the access.

Further, in this embodiment, as shown in FIGS. 1 and 2, the redundant word line reset circuits 35 and 36 and the word are provided on the right end side of the redundant word lines RWL0 and RWL1 and the word lines WL00 to WL03 and WL10. Line reset circuits 37 to 41 are provided and redundant word lines RWL0,
RWL1 and word lines WL00 to WL03, WL10 are reset mainly by redundant word line reset circuits 35, 3
6 and the word line reset circuits 37 to 41. Therefore, the redundant word lines RWL0, RWL1
And word lines WL00 to WL03, WL10 and nMO
S transistors 42, 44, 46, 48, 50, 52,
It is possible to prevent a large wiring resistance from being generated between the drain of 54. As a result, the redundant word line RWL
0, RWL1 and word lines WL00 to WL03, WL1
It is possible to accelerate the fall of 0 and to accelerate the resetting of the redundant word line and the resetting of the word line.

That is, in the present embodiment, in FIG. 1 and FIG. 2, the redundant word line RWL is added to the cell array region 18.
0, RWL1 and word lines WL00 to WL03, WL1
On the left end side of 0, the redundant word line drive circuits 26 to 29 and the word line drive circuit 3 for raising these word lines are provided.
0 to 34 P-channel field effect transistors are arranged. In addition, for the cell array region 18, a redundant word line R
WL0, RWL1 and word lines WL00-WL03, W
N channel field effect transistors of the redundant word line reset circuits 35 and 36 and the word line reset circuits 37 to 41 for terminating these word lines are arranged on the right end side of L10. Although FIG. 1 and FIG. 2 are circuit diagrams, a schematic layout of the DRAM on a plan view is also shown for convenience of description. Therefore, it is possible to prevent the formation of a junction in which a voltage exceeding the boosted voltage Vpp is applied,
Even when the DRAM is highly integrated, it is possible to prevent the reliability of the DRAM from decreasing. Further, by adopting the above arrangement, between the P-channel field effect transistor for raising the word line and the word line, and between the N-channel field effect transistor for raising the word line and the word line. It is also possible to prevent a large wiring resistance from occurring, and as a result, it is possible to speed up the rise and fall of the word line and the access and word line reset.

The present invention has been described with reference to the embodiments.
The present invention is not limited to the above embodiments, and it goes without saying that various modifications and improvements can be made within the scope of the present invention.

[0053]

According to the present invention, P is provided on one end side of the word line.
A word line drive circuit for raising a word line using a channel field effect transistor is provided, and a word line reset circuit for lowering a word line using an N channel field effect transistor on the other end side of the word line. By providing the above, it is possible to prevent the formation of a junction in which a voltage exceeding the boosted voltage is applied and to prevent the deterioration of the reliability even when the semiconductor memory device is highly integrated, and the word line It is also possible to prevent a large wiring resistance from occurring between the P-channel field effect transistor for starting up and the word line and between the N-channel field effect transistor for starting up the word line and the word line. It is possible to speed up the rise and fall of lines, and speed up access and word line reset. , Practically it is very useful.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a partial configuration of an embodiment of a semiconductor memory device according to the present invention.

FIG. 2 is a circuit diagram showing an example of a configuration of a circuit portion including a redundant word line drive circuit and a word line drive circuit.

FIG. 3 shows a case where a redundant memory cell is not used,
FIG. 7 is a waveform diagram illustrating an operation of the embodiment when a word line is selected.

FIG. 4 is a waveform diagram for explaining the operation of the embodiment when a word line is selected when the word line is replaced with a redundant word line.

FIG. 5 is a circuit diagram showing an example of a configuration of part of a conventional DRAM.

FIG. 6 is a waveform diagram for explaining a word line selecting operation in a conventional DRAM.

FIG. 7 is a circuit diagram showing another example of the configuration of part of a conventional DRAM.

FIG. 8 is a waveform diagram for explaining a word line selecting operation in the DRAM shown in FIG.

[Explanation of symbols]

 18 cell array region 19, 20 redundant memory cell 21-25 memory cell 26-29 redundant word line drive circuit 30-34 word line drive circuit 35, 36 redundant word line reset circuit 37-41 word line reset circuit 42-45 nMOS transistor RWL0 , RWL1 redundant word line WL00 to WL03, WL10 word line WD0Z to WD3Z word line drive signal SEL0X, SEL1X word line selection signal RES0Z to RES3Z word line reset signal

Claims (7)

[Claims] 1. A word line drive circuit for raising the word line by using a P-channel field effect transistor on one end side of the word line, and an N-channel field effect transistor on the other end side of the word line. And a word line reset circuit for lowering the word line. 2. The P-channel field effect transistor has a drain connected to the word line and a source connected to the first line.
2. The semiconductor memory device according to claim 1, wherein a predetermined word line selection signal of the word line selection signal group is applied, and a predetermined word line selection signal of the second word line selection signal group is applied to the gate. 3. The word line drive circuit has a drain connected to the word line, a source grounded, and a gate to which a predetermined word line selection signal applied to the gate of the P-channel field effect transistor is applied. The semiconductor memory device according to claim 2, further comprising an N-channel field effect transistor. 4. The word line reset circuit has a first N-channel field effect transistor having a drain connected to the word line and having a gate to which a power supply voltage is applied, and a drain having the first N-channel field effect transistor. A second N-channel field effect transistor connected to the source of the same, the source of which is grounded, and the gate of which is applied with a predetermined word line reset signal of the word line reset signal group. 2. A semiconductor memory device according to item 1. 5. A drain is connected to the redundant word line at one end side of the redundant word line, and a first predetermined word line selection signal of the first word line selection signal group is applied to the source of the redundant word line, and a gate is provided. A first redundant word line drive circuit having a first redundant P-channel field effect transistor to which a redundant word line selection signal is applied, and a drain connected to the redundant word line and a source selected from the first word line A second redundant word line drive circuit having a second redundant P-channel field effect transistor to which a second predetermined word line selection signal of the signal group is applied and the redundant word line selection signal is applied to the gate. Furthermore, a drain is connected to the redundant word line on the other end side of the redundant word line, and a first predetermined word line reset signal of the word line reset signal group is connected to the gate. Is applied to the first redundant N-channel field effect transistor, the drain is connected to the source of the first redundant N-channel field effect transistor, the source is grounded, and the gate is the second of the word line reset signal groups. 5. The semiconductor memory device according to claim 2, further comprising a redundant word line reset circuit including a second redundant N-channel field effect transistor to which the predetermined word line reset signal is applied. 6. The redundant N-channel electric field in which the first and second redundant word line driving circuits have drains connected to the redundant word lines, sources grounded, and gates to which the redundant word line selection signal is applied. With effect transistor,
The semiconductor memory device according to claim 5. 7. The semiconductor memory device according to claim 1, wherein one end side and the other end side of the word line correspond to both sides of a cell array region in which memory cells are arranged, respectively. .