JP3625238B2 - Semiconductor memory device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device having a configuration in which a word line is raised using a P-channel field effect transistor.
[0002]
[Prior art]
Conventionally, as an example of a semiconductor memory device, a dynamic random access memory (hereinafter referred to as DRAM) having a configuration partially shown in FIG. 5 has been proposed. This portion includes a cell array region 1 in which memory cells are arranged, a word line 2 for selecting a memory cell, a word line driving circuit 3 for driving the word line 2, and an inverter 4 connected as shown in FIG. And nMOS transistors 5 to 7.
[0003]
In FIG. 5, WDZ indicates a word line drive signal, and SELX indicates a word line selection signal. In the word line drive signal WDZ, the low potential is the ground voltage Vss, and the high potential is the voltage Vpp obtained by boosting the power supply voltage Vcc. On the other hand, the word line selection signal SELX has a low potential of the ground voltage Vss and a high potential of the power supply voltage Vcc. VSRZ indicates a fixed voltage equal to or lower than Vcc + Vth, where the threshold voltage of the nMOS transistor 5 is Vth.
[0004]
FIG. 6 is a waveform diagram for explaining the selection operation of the word line 2 in the DRAM. In the figure, the voltage waveform of the word line selection signal SELX, the voltage waveform of the word line drive signal WDZ, the voltage waveform of the node 8, and the voltage waveform of the word line 2 are shown.
[0005]
That is, in the DRAM, when the word line 2 is not selected, the level of the word line selection signal SELX is Vcc, the level of the word line drive signal WDZ is Vss, the output level of the inverter 4 is Vss, and the level of the node 8 is Vss, nMOS. The transistor 6 is non-conductive, the nMOS transistor 7 is conductive, and the level of the word line 2 is Vss.
[0006]
When the word line 2 is selected from this state, the level of the word line selection signal SELX is lowered to Vss, the nMOS transistor 7 is turned off, the output level of the inverter 4 is raised to Vcc, and the nMOS Transistor 8 precharges node 8 to the level of Vcc-α.
[0007]
Next, the level of the word line drive signal WDZ rises to Vpp. In this case, since a channel is formed in the nMOS transistor 6, the voltage at the node 8 is determined by the capacitance between the channel and gate of the nMOS transistor 6. Self-boosted and rises to the level of Vpp + α. As a result, the voltage of word line 2 rises to the level of Vpp following the word line drive signal WDZ.
[0008]
Thereafter, when the word line 2 is reset, the level of the word line drive signal WDZ falls toward Vss, and the charge accumulated in the word line 2 is extracted to the word line drive signal line side via the nMOS transistor 6. . Thereby, the voltage of the word line 2 starts to fall following the word line drive signal WDZ.
[0009]
When the level of the word line drive signal WDZ becomes Vss, the level of the word line selection signal SELX is then raised to Vcc. As a result, the output level of the inverter 4 becomes Vss, and the charge accumulated in the node 8 is drawn to the ground side via the nMOS transistor 5 and the inverter 4. As a result, the level of the node 8 is set to Vss, and the nMOS transistor 6 is turned off.
[0010]
In this case, the nMOS transistor 7 is turned on, and the charge remaining on the word line 2 is drawn to the ground side through the nMOS transistor 7, so that the level of the word line 2 is set to Vss.
However, in the DRAM, a voltage exceeding the level of Vpp is applied to the junction between the N-type diffusion layer constituting the drain or source on the node 8 side of the nMOS transistor 5 and the P well. There is a problem that the reliability of the DRAM is lowered with the high integration of the semiconductor memory.
[0011]
In order to solve this problem, a DRAM having a configuration partially shown in FIG. 7 has been proposed. This portion includes a cell array region 10 in which memory cells are arranged, a word line 11, a word line driving circuit 12 for driving the word line 11, a pMOS transistor 13, and an nMOS transistor 14 connected as shown in FIG. , 15 and a wiring resistance 16 between the word line 11 and the drain of the nMOS transistor 14.
[0012]
FIG. 8 is a waveform diagram for explaining the operation of selecting the word line 11 in the DRAM shown in FIG. In FIG. 8, the voltage waveform of the word line selection signal SELX and the voltage waveform of the word line 11 are shown.
In the DRAM shown in FIG. 7, when the word line 11 is not selected, the level of the word line selection signal SELX is Vpp, the pMOS transistor 13 is non-conductive, the nMOS transistor 15 is conductive, and the level of the word line 11 is Vss. Yes. When the word line 11 is selected from this state, the level of the word line selection signal SELX is lowered to Vss, the pMOS transistor 13 is turned on, and the nMOS transistor 15 is turned off. The voltage level of the word line 11 is raised to Vpp through the pMOS transistor 13.
[0013]
Thereafter, when the word line 11 is reset, the level of the word line selection signal SELX is raised to Vpp, the pMOS transistor 13 is turned off, and the nMOS transistor 15 is turned on. Further, the charge accumulated in the word line 11 is drawn to the ground side through the nMOS transistors 14 and 15, and the voltage level of the word line 11 is lowered to Vss.
[0014]
As described above, in the DRAM shown in FIG. 7, there is no junction that rises to a potential level equal to or higher than Vpp. Therefore, reliability can be ensured even when the DRAM is highly integrated.
[0015]
[Problems to be solved by the invention]
However, in the DRAM shown in FIG. 7, in order to increase the access speed, the pMOS transistor 13 needs to be arranged near the cell array region 10 in order to emphasize the rising speed of the word line 11. . For this reason, the nMOS transistors 14 and 15 must be arranged at positions far from the word line 11 with the pMOS transistor 13 interposed therebetween.
[0016]
However, when the above arrangement is adopted, the length of the wiring connecting the word line 11 and the drain of the nMOS transistor 14 becomes long, and the wiring resistance 16 becomes large. For this reason, the fall of the word line 11 is extremely slow due to the wiring resistance 16, which causes a new problem that the reset of the word line 11 cannot be speeded up.
[0017]
On the other hand, when the nMOS transistors 14 and 15 are arranged close to the cell array region 10 and the pMOS transistor 13 is arranged far from the cell array region 10 with the nMOS transistors 14 and 15 interposed therebetween, the reset of the word line 11 is speeded up. However, the start-up of the word line 11 becomes extremely slow, and the access speed cannot be increased.
[0018]
Therefore, in view of the above problems, the present invention does not form a junction where a voltage exceeding the boosted voltage is applied, and does not reduce reliability even when high integration is achieved. It is an object of the present invention to provide a semiconductor memory device that can be performed in the same manner.
[0019]
[Means for Solving the Problems]
The above problem is that a word line driving circuit for starting up the word line using a P-channel field effect transistor on one end side of the word line and an N-channel field effect transistor on the other end side of the word line are used. This can be achieved by a semiconductor memory device provided with a word line reset circuit for lowering the word line.
[0020]
According to the present invention, since the word line is raised using the P-channel field effect transistor, a junction to which a voltage exceeding the boosted voltage is applied can be prevented from being formed.
When the word line driving circuit is provided on one end side of the word line and the word line reset circuit is provided on the other end side of the word line, the word line is raised between the P channel field effect transistor and the word line and the word line. Since it is possible to prevent a large wiring resistance from existing between the N-channel field-effect transistor that performs line falling and the word line, it is possible to increase the speed of rising and falling of the word line.
[0021]
DETAILED DESCRIPTION OF THE INVENTION
Embodiments of the present invention will be described below together with the examples shown in FIGS.
[0022]
【Example】
FIG. 1 is a circuit diagram showing a partial configuration of an embodiment of a semiconductor memory device according to the present invention. In this embodiment, the present invention is applied to a DRAM.
1 includes a cell array region 18, redundant word lines RWL0 and RWL1, and normal word lines (hereinafter simply referred to as word lines) WL00, WL01, WL02, WL03, which are connected as illustrated. WL 10, bit lines BLX and BLZ, redundant memory cells 19 and 20, and regular memory cells (hereinafter simply referred to as memory cells) 21 to 25 arranged in the cell array region 18. The redundant word line driving circuits 26 and 27 drive the redundant word line RWL0, and the redundant word line driving circuits 28 and 29 drive the redundant word line RWL1. The word line driving circuit 30 drives the word line WL00, the word line driving circuit 31 drives the word line WL01, the word line driving circuit 32 drives the word line WL02, and the word line driving circuit 33 drives the word line WL03. Then, the word line driving circuit 34 drives the word line WL10.
[0023]
The redundant word line reset circuit 35 resets the redundant word line RWL0, and the redundant word line reset circuit 36 resets the redundant word line RWL1. The word line reset circuit 37 resets the word line WL00, the word line reset circuit 38 resets the word line WL01, the word line reset circuit 39 resets the word line WL02, and the word line reset circuit 40 The word line WL03 is reset, and the word line reset circuit 41 resets the word line WL10. The reset circuits 35 to 41 are each constituted by two corresponding nMOS transistors of the nMOS transistors 42 to 55.
[0024]
In FIG. 1, WD0Z to WD3Z are word line drive signals, SEL0X and SEL1X are word line selection signals, SELR0X is a redundant word line selection signal, and RES0Z to RES3Z are word line reset signals.
The word line drive signals WD0Z to WD3Z, the word line selection signals SEL0X and SEL1X, and the redundant word line selection signal SELR0X have the low potential set to the ground voltage Vss and the high potential set to the boosted voltage Vpp obtained by boosting the power supply voltage Vcc. ing. The word line reset signals RES0Z to RES3Z have a low potential as the ground voltage Vss and a high potential as the power supply voltage Vcc.
[0025]
FIG. 2 is a circuit diagram showing one embodiment of a configuration of a circuit portion including the redundant word line driving circuits 26 and 27 and the word line driving circuit 30. In FIG. The circuit portion shown in FIG. 2 includes pMOS transistors 57 to 59 and nMOS transistors 60 to 62 connected as shown.
[0026]
The other redundant word line drive circuits 28 and 29 and the word line drive circuits 31 to 34 also have the same configuration as the corresponding parts of the circuit part shown in FIG. FIGS. 1 and 2 are circuit diagrams, and also show a schematic arrangement on a plan view of a DRAM, as will be described later.
[0027]
For example, the word line WL00 has a row address RA0 to RA4 of “00000”, and the word line WL01 has a row address RA0 to RA4 of “10000”. The word line WL02 has a row address RA0 to RA4 of “01000”, and the word line WL03 has a row address RA0 to RA4 of “11000”. That is, n is an integer and i = 0, 1,. . . , N, the word line WLi0 and the word line WLi1 have the same row address RA0 although the row address RA0 is different. Also, the row address RA0 is different between the word line WLi2 and the word line WLi3, but the row addresses RA1 to RA4 are the same.
[0028]
In this embodiment, when there is no defect in the memory cells including the memory cells 21 to 25 and the redundant memory cells including the redundant memory cells 19 and 20 are not used, “00” is set as the row addresses RA0 and RA1. Is first designated, the word line reset signal RES0Z falls, and then the word line drive signal WD0Z rises.
[0029]
When “10” is designated as the row addresses RA0 and RA1, first, the word line reset signal RES1Z falls, and then the word line drive signal WD1Z rises.
When “01” is designated as the row addresses RA0 and RA1, first, the word line reset signal RES2Z falls, and then the word line drive signal WD2Z rises.
[0030]
Further, when “11” is designated as the row addresses RA0 and RA1, first, the word line reset signal RES3Z falls, and then the word line drive signal WD3Z rises.
On the other hand, in this embodiment, when redundant memory cells are used, the word lines WLi0 and WLi1 or the word lines WLi2 and WLi3 are replaced with redundant word lines RWL0 and RWL1. Therefore, when redundant memory cells are used and “00” is designated as the row addresses RA0 and RA1, first, the word line reset signal RES0Z falls, and then the word line drive signals WD0Z and WD2Z rise.
[0031]
When “10” is designated as the row addresses RA0 and RA1, first, the word line reset signal RES1Z falls, and then the word line drive signals WD1Z and WD3Z rise.
When “01” is designated as the row addresses RA0 and RA1, first, the word line reset signal RES2Z falls, and then the word line drive signals WD0Z and WD2Z rise.
[0032]
Further, when “11” is designated as the row addresses RA0 and RA1, first, the word line reset signal RES3Z falls, and then the word line drive signals WD1Z and WD3Z rise.
FIG. 3 is a waveform diagram for explaining the operation of the DRAM when the word line WL00 is selected when no redundant memory cell is used. In the figure, voltage waveforms of word line reset signals RES0Z to RES3Z, word line selection signals SEL0X and SEL1X, word line drive signal WD0Z, redundant word line selection signal SELR0X, and word line WL00 are shown.
[0033]
In this case, when the word line WL00 is not selected, the levels of the word line selection signals SEL0X and SEL1X and the redundant word line selection signal SELR0X are Vpp, the levels of the word line reset signals RES0Z to RES3Z are Vcc, and the levels of the word line drive signal WD0Z are Vss. For this reason, in the redundant word line drive circuits 26 to 29 and the word line drive circuits 30 to 34, the pMOS transistors are turned off and the nMOS transistors are turned on. In the redundant word line reset circuits 35 and 36 and the word line reset circuits 37 to 41, the nMOS transistors 42 to 55 are turned on, and the levels of the redundant word lines RWL0 and RWL1 and the word lines WL00 to WL03 and WL10 are Vss. Is done.
[0034]
When the word line WL00 is selected from this state, “00” is designated as the row addresses RA0 and RA1, and the level of the word line reset signal RES0Z is lowered to Vss. As a result, the nMOS transistor 42 of the redundant word line reset circuit 35 and the nMOS transistors 47 and 55 of the word line reset circuits 37 and 41 are turned off.
[0035]
Subsequently, the level of the word line selection signal SEL0X is lowered to Vss, and the level of the word line drive signal WD0Z is raised to Vpp. Thereby, in word line drive circuit 30, pMOS transistor 59 is turned on and nMOS transistor 62 is turned off, and the level of word line WL00 rises to Vpp following word line drive signal WD0Z.
[0036]
When the word line WL00 is reset, the level of the word line reset signal RES0Z is raised to Vcc, and the level of the word line drive signal WD0Z is lowered to Vss. As a result, the electric charge accumulated in the word line WL00 is drawn out to the word line drive signal line side through the pMOS transistor 59 of the word line drive circuit 30, and through the nMOS transistors 46 and 47 of the word line reset circuit 37. Pulled out to the ground side. Accordingly, the level of the word line WL00 falls toward Vss.
[0037]
When the level of the word line WL00 becomes Vcc or lower, the level of the word line selection signal SEL0X is raised to Vpp, the pMOS transistor 59 is turned off and the nMOS transistor 62 is turned on in the word line drive circuit 30. As a result, the charge remaining on the word line WL00 is extracted to the ground side via the nMOS transistor 62 of the word line driving circuit 30 and the nMOS transistors 46 and 47 of the word line reset circuit 37, and the level of the word line WL00 is It falls to Vss and is clamped to Vss.
[0038]
FIG. 4 is a waveform diagram for explaining the operation of the DRAM when the word line WL00 is selected when the word lines WL00 and WL01 are replaced with the redundant word lines RWL0 and RWL1. The figure shows voltage waveforms of word line reset signals RES0Z to RES3Z, word line selection signals SEL0X and SEL1X, word line drive signals WD0Z to WD3Z, redundant word line selection signal SELR0X, and redundant word line RWL0.
[0039]
Even in this case, when the word line WL00 is not selected, the levels of the word line selection signals SEL0X and SEL1X and the redundant word line selection signal SELR0X are Vpp, the levels of the word line reset signals RES0Z to RES3Z are Vcc, and the word line drive signals WD0Z to WD3Z The level of Vss is Vss. For this reason, in the redundant word line drive circuits 26 to 29 and the word line drive circuits 30 to 34, the pMOS transistors are turned off and the nMOS transistors are turned on. In the redundant word line reset circuits 35 and 36 and the word line reset circuits 37 to 41, the nMOS transistors 42 to 55 are turned on, and the levels of the redundant word lines RWL0 and RWL1 and the word lines WL00 to WL03 and WL10 are set to Vss. It is said.
[0040]
When the word line WL00 is selected from this state, “00” is designated as the row addresses RA0 and RA1, and the level of the word line reset signal RES0Z is lowered to Vss. As a result, the nMOS transistor 42 of the redundant word line reset circuit 35 and the nMOS transistors 47 and 55 of the word line reset circuits 37 and 41 are turned off.
[0041]
Subsequently, the level of the redundant word line selection signal SELR0X is lowered to Vss, and the levels of the word line drive signals WD0Z and WD2Z are raised to Vpp. For this reason, in the redundant word line selection circuits 26 and 27, the pMOS transistors 57 and 58 are turned on, and the nMOS transistors 60 and 61 are turned off. The level of the redundant word line RWL0 rises to Vpp following the word line drive signals WD0Z and WD2Z.
[0042]
When the word line WL00 is reset, the level of the word line reset signal RES0Z is raised to Vcc, and the levels of the word line drive signals WD0Z and WD2Z are lowered toward Vss. As a result, the charges accumulated in the redundant word line RWL0 are extracted to the word line driving signal line side through the pMOS transistors 57 and 58 of the redundant word line driving circuits 26 and 27, and the redundant word line reset circuit 35 It is pulled out to the ground side through the nMOS transistors 42 and 43. Further, the level of the redundant word line RWL0 is lowered toward Vss.
[0043]
When the level of redundant word line RWL0 becomes Vcc or lower, the level of redundant word line selection signal SELR0X is raised to Vpp. In the redundant word line driving circuits 26 and 27, the pMOS transistors 57 and 58 are turned off and the nMOS transistors 60 and 61 are turned on. Therefore, the charge remaining on the redundant word line RWL0 is drawn to the ground side through the nMOS transistors 60 and 61 of the redundant word line drive circuits 26 and 27 and the nMOS transistors 42 and 43 of the redundant word line reset circuit 35. . Further, the level of the redundant word line RWL0 is lowered to Vss and clamped to Vss.
[0044]
When the word lines WL02 and WL03 are replaced with the redundant word lines RWL0 and RWL1, when the word line WL02 is selected, “01” is designated as the row addresses RA0 and RA1, and the level of the word line reset signal RES2Z is set. Falled to Vss. As a result, the nMOS transistor 43 of the redundant word line reset circuit 35 and the nMOS transistor 51 of the word line reset circuit 39 are turned off.
[0045]
Subsequently, the level of the redundant word line selection signal SELR0X is lowered to Vss, and the levels of the word line drive signals WD0Z and WD2Z are raised to Vpp. For this reason, in the redundant word line drive circuits 26 and 27, the pMOS transistors 57 and 58 are turned on, and the nMOS transistors 60 and 61 are turned off. Further, the level of the redundant word line RWL0 rises to Vpp following the word line drive signals WD0Z and WD2Z.
[0046]
When the word line WL00 is reset, the level of the word line reset signal RES2Z is raised to Vcc, and the levels of the word line drive signals WD0Z and WD2Z are lowered toward Vss. As a result, the charges accumulated in the redundant word line RWL0 are extracted to the word line driving signal line side through the pMOS transistors 57 and 58 of the redundant word line driving circuits 26 and 27, and the redundant word line reset circuit 35 It is pulled out to the ground side through the nMOS transistors 42 and 43. Further, the level of the redundant word line RWL0 is lowered toward Vss.
[0047]
When the level of redundant word line RWL0 becomes Vcc or lower, the level of redundant word line selection signal SELR0X is raised to Vpp. In the redundant word line drive circuits 26 and 27, the pMOS transistors 57 and 58 are turned off and the nMOS transistors 60 and 61 are turned on. Therefore, the charge remaining on the redundant word line RWL0 is drawn to the ground side through the nMOS transistors 60 and 61 of the redundant word line drive circuits 26 and 27 and the nMOS transistors 42 and 43 of the redundant word line reset circuit 35. . Further, the level of the word line WL00 is lowered to Vss and clamped to Vss.
[0048]
As described above, according to this embodiment, since the word line or the redundant word line is raised using the pMOS transistor, a junction to which a voltage exceeding the boosted voltage Vpp is not formed, and the DRAM is highly integrated. Even in the case of achieving the reduction, it is possible to prevent a decrease in reliability.
[0049]
By the way, in this embodiment, in FIG. 1 and FIG. 2, the pMOS transistors of the redundant word line driving circuits 26 to 29 and the word line driving circuits 30 to 34 are arranged near the cell array region 18, and the nMOS transistors are replaced with pMOS transistors. It can be arranged at a position far from the cell array region 18 with the sandwich. When such an arrangement of the pMOS transistor and the nMOS transistor is adopted, a large wiring is provided between the pMOS transistor for starting up the redundant word line and the redundant word line and between the pMOS transistor for starting up the word line and the word line. Resistance can be avoided. Therefore, it is possible to increase the speed of the redundant word line and the rise of the word line and to increase the access speed.
[0050]
Further, in this embodiment, as shown in FIGS. 1 and 2, redundant word line reset circuits 35 and 36 and a word line reset circuit are provided on the right end side of the redundant word lines RWL0 and RWL1 and the word lines WL00 to WL03 and WL10. 37 to 41 are provided, and the redundant word lines RWL0 and RWL1 and the word lines WL00 to WL03 and WL10 are reset mainly by the redundant word line reset circuits 35 and 36 and the word line reset circuits 37 to 41. . Therefore, a large wiring resistance should not be generated between the redundant word lines RWL0, RWL1 and the word lines WL00 to WL03, WL10 and the drains of the nMOS transistors 42, 44, 46, 48, 50, 52, 54. Can do. As a result, it is possible to speed up the fall of the redundant word lines RWL0, RWL1 and the word lines WL00 to WL03, WL10, and to speed up the reset of the redundant word line and the reset of the word line.
[0051]
In other words, in this embodiment, in FIG. 1 and FIG. 2, the redundant word lines RWL0 and RWL1 and the word lines WL00 to WL03 and WL10 are left on the left end side of the redundant word lines RWL0 and RWL1 with respect to the cell array region 18. P channel field effect transistors of the word line driving circuits 26 to 29 and the word line driving circuits 30 to 34 are arranged. Further, on the right end side of the redundant word lines RWL0 and RWL1 and the word lines WL00 to WL03 and WL10 with respect to the cell array region 18, redundant word line reset circuits 35 and 36 and a word line reset circuit for lowering these word lines. 37 to 41 N-channel field effect transistors are arranged. 1 and 2 are circuit diagrams, for the sake of convenience of description, a schematic arrangement on a plan view of the DRAM is also shown. Therefore, it is possible to prevent the formation of a junction where a voltage exceeding the boosted voltage Vpp is applied, and it is possible to prevent a decrease in the reliability of the DRAM even when the DRAM is highly integrated. Further, by adopting the arrangement as described above, between the P-channel field effect transistor and the word line for raising the word line, and between the N-channel field effect transistor and the word line for lowering the word line. As a result, the rise and fall of the word line can be speeded up, and the access and the reset of the word line can be speeded up.
[0052]
While the present invention has been described with reference to the embodiments, it is needless to say that the present invention is not limited to the above-described embodiments, and various modifications and improvements can be made within the scope of the present invention.
[0053]
【The invention's effect】
According to the present invention, a word line drive circuit for starting up a word line using a P-channel field effect transistor is provided on one end side of the word line, and an N-channel field effect transistor is used on the other end side of the word line. By providing a word line reset circuit that lowers the word line, it is possible to prevent the formation of a junction to which a voltage exceeding the boosted voltage is applied and to achieve high integration of the semiconductor memory device. In addition, a large wiring can be provided between the P-channel field effect transistor for raising the word line and the word line and between the N-channel field effect transistor for raising the word line and the word line. Since it is possible to prevent resistance from occurring, the rise and fall of the word line can be accelerated, and the access and word line It is possible to increase the speed of set, practically it is very useful.
[Brief description of the drawings]
FIG. 1 is a circuit diagram showing a partial configuration of an embodiment of a semiconductor memory device according to the present invention;
FIG. 2 is a circuit diagram showing one embodiment of a configuration of a circuit portion including a redundant word line driving circuit and a word line driving circuit.
FIG. 3 is a waveform diagram for explaining the operation of the embodiment when a word line is selected when a redundant memory cell is not used;
FIG. 4 is a waveform diagram for explaining the operation of the embodiment when a word line is selected when the word line is replaced with a redundant word line.
FIG. 5 is a circuit diagram showing an example of a configuration of a part of a conventional DRAM.
FIG. 6 is a waveform diagram for explaining a word line selection operation in a conventional DRAM.
FIG. 7 is a circuit diagram showing another example of the configuration of a part of a conventional DRAM.
FIG. 8 is a waveform diagram for explaining a word line selection operation in the DRAM shown in FIG. 7;
[Explanation of symbols]
18 Cell array area
19, 20 Redundant memory cell
21-25 memory cells
26-29 Redundant word line drive circuit
30-34 Word line drive circuit
35, 36 Redundant word line reset circuit
37-41 Word line reset circuit
42-45 nMOS transistor
RWL0, RWL1 Redundant word line
WL00 to WL03, WL10 Word line
WD0Z to WD3Z Word line drive signal
SEL0X, SEL1X Word line selection signal
RES0Z to RES3Z Word line reset signal

Claims (5)

One end of the word line has a drain connected to the word line, a first word line drive signal in the word line drive signal group is applied to the source, and one word line selection in the word line selection signal group is applied to the gate A word line driving circuit for starting up the word line using a P-channel field effect transistor to which a signal is applied;
  A word line reset circuit for lowering the word line using an N-channel field effect transistor on the other end side of the word line;
  A first redundant P-channel electric field in which a drain is connected to the redundant word line on one end side of the redundant word line, the first word line driving signal is applied to the source, and a redundant word line selection signal is applied to the gate. A first redundant word line driving circuit having an effect transistor;
  The drain is connected to the redundant word line on the one end side of the word line, the second word line driving signal of the word line driving signal group is applied to the source, and the redundant word line selection signal is applied to the gate. A second redundant word line drive circuit having a second redundant P-channel field effect transistor,
  A first redundant N-channel field effect transistor having a drain connected to the redundant word line on the other end side of the redundant word line, and a first word line reset signal of the word line reset signal group applied to the gate; , The drain is connected to the source of the first redundant N-channel field effect transistor, the source is grounded, and a second word line reset signal of the word line reset signal group is applied to the gate. A semiconductor memory device comprising a redundant word line reset circuit comprising a channel field effect transistor. The word line driving circuit has an N channel field effect in which a drain is connected to the word line, a source is grounded, and the one word line selection signal applied to the gate of the P channel field effect transistor is applied to the gate. The semiconductor memory device according to claim 1, comprising a transistor. The word line reset circuit
  A first N-channel field effect transistor having a drain connected to the word line and a power supply voltage applied to the gate;
  2. A second N-channel field effect transistor having a drain connected to a source of the first N-channel field effect transistor, a source grounded, and a gate to which the first word line reset signal is applied. 3. The semiconductor memory device according to 1 or 2. The first and second redundant word line driving circuits include redundant N-channel field effect transistors having drains connected to the redundant word lines, sources connected to ground, and gates to which the redundant word line selection signal is applied. Any one of claims 1-3 1 A semiconductor memory device according to item. 5. The semiconductor memory device according to claim 1, wherein one end side and the other end side of the word line respectively correspond to both sides of a cell array region in which memory cells are arranged.

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