JPH09107492A - Digital picture processing circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To normally perform the digital processing of a video signal even in the case of unstable synchronization of a video signal source. SOLUTION: The video signal is inputted to a delay circuit 1 and a synchronizing signal separation circuit 2. In the delay circuit, the input video signal is sampled in an A/D conversion part 11 by the clock from an oscillator 11 and is digitally converted and is written in a memory 12 and is read out after the delay of a required time by the clock and is analogically converted by a D/A conversion part 13 and is inputted to a digital processing circuit 4 with the delay of 1H. A signal HD separated by the synchronizing signal separation circuit is applied to a PLL circuit 3, and the clock digitally oscillated by a VCO 17 has the frequency divided to the frequency of the signal HD by a frequency divider 18 and is fed back to a phase comparator 15 and has the phase compared with that of the signal HD, and an unnecessary frequency component of the signal outputted in accordance with the phase difference is eliminated by an LPF 16, and this signal is applied to the VCO 17 to generate a clock whose phase coincides with that of the signal HD of 1H before, and this clock is used for processing in the digital processing circuit 4.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital image processing circuit, and more particularly to a circuit for delaying a video signal to match the timing of a clock used for digital processing of the video signal.

[0002]

2. Description of the Related Art As a circuit for processing a video signal into a digital signal, there is, for example, a circuit configured as shown in FIG. This circuit inputs an analog video signal to the digital processing circuit 4 and the sync separation circuit 2, and the sync separation circuit 2
HD (horizontal sync signal) is separated by and this HD is PLL
(Phase-locked loop) Applied to circuit 3 and H
This circuit generates a clock whose phase matches that of D and supplies it to the digital processing circuit 4 to perform digital processing of the video signal. The PLL circuit 3 divides the clock oscillated by the VCO (voltage controlled oscillator) 17 into the HD frequency of the video signal by the frequency divider 18, feeds it back to the phase comparator 15, and outputs it to the HD and the phase from the sync separation circuit 4. And the signal output according to the phase difference is input to the LPF (low pass filter) 16 to be a DC component, which is applied to the VCO 17 to control the oscillation frequency and input from the sync separation circuit 2. A clock whose phase matches that of HD is output. Therefore, the clock from the PLL circuit 3 is 1H.
(H is in the horizontal scanning period) The phase is the same as that of the previous HD, and when the video signal source is a broadcast signal or the like, the synchronization stability of the signal source is high, so the HD separated by the sync separation circuit 2 has no phase. There is almost no change, and the HD before 1H (1 horizontal scanning period)
There is no phase difference between the next HD and the next HD.
In the case of a video signal source such as (video tape recorder) that does not always have good synchronization stability, the HD before 1H
There may be a phase difference between the next HD and the next HD. The digital processing circuit 4 is a PLL whose phase matches that of the HD before 1H.
Since the next H video signal is processed by the clock from the circuit 3, when the phase varies between HDs as described above, the phase of the video signal and the clock do not match and correct digital conversion is performed. There is the problem of not having it.

[0003]

In view of the above, the present invention delays the video signal by 1H and inputs it to the digital processing circuit to process the video signal with a clock from a PLL circuit synchronized with HD of the same H. Is to do.

[0004]

In order to solve the above-mentioned problems, the present invention is a digital image processing of an analog video signal by a digital processing circuit, wherein a delay 1 circuit delays the video signal by 1H and the video signal. P that generates the first clock that is in phase with HD separated from the signal
An LL circuit is provided, and the delay circuit includes an oscillator that oscillates a second clock, an A / D converter that samples the video signal with a clock from the oscillator and converts the video signal into a digital signal, and an A / D converter. Memory for inputting the video data of the above, and writing and reading by the second clock from the oscillator, and a D / A converter for converting the data read from the memory into an analog signal using the second clock from the oscillator. And a video signal delayed by a delay circuit is input to a digital processing circuit, and digital image processing is performed using the first clock from the PLL circuit.

[0005]

With the above arrangement, in the digital image processing circuit according to the present invention, the input video signal is delayed by 1H by the digital delay circuit or the analog delay line,
The signal is input to the digital processing circuit with a delay of 1H with respect to the input signal, and digital processing is performed by a clock whose phase is synchronized with HD 1H before the PLL circuit.

[0006]

Embodiments of the digital image processing circuit according to the present invention will be described in detail below with reference to the drawings. FIG. 1 is a block diagram of essential parts of an embodiment of a digital image processing circuit according to the present invention. In the figure, reference numeral 1 is a delay circuit, which delays the input video signal by 1H. Reference numeral 2 denotes a sync signal separation circuit, which separates HD from an input video signal. Reference numeral 3 denotes a PLL circuit, which generates a clock whose phase is synchronized with HD from the sync signal separation circuit 2.

The delay circuit 1 includes an A / D converter 11, a memory 1
2, D / A converter 13 and oscillator 14. Since the oscillator 14 oscillates a clock having a stable frequency, it is composed of, for example, a crystal oscillator using a crystal oscillator. The clock from the oscillator 14 is supplied to each unit, and the A / D converter 11
The input video signal is sampled at, converted into digital data, and the memory 12 is written and read by the clock from the oscillator 14, and the read video data is D / A.
The converter 13 converts the analog signal and outputs it to the digital processing circuit 4. To read the memory data of the memory 12, use A
The output of the D / A converter 13 is 1 with respect to the input of the / D converter 11.
With a delay of H, that is, the timing of reading from the writing of the memory 12 is set to the A / D conversion unit 11 and the memory 12
It is set so that the total time required for the writing / reading of the data and the processing of the D / A converter 13 is delayed by the time obtained by subtracting 1H.

The PLL circuit 3 includes a phase comparator 15, an LPF 16,
It is composed of a VCO 17 and a frequency divider 18, and the clock oscillated by the VCO 17 is input to the frequency divider 18 to output the HD of the input video signal.
The frequency is divided into frequencies, fed back to the phase comparator 15, the phase is compared with the HD from the sync separation circuit 2, and the signal (voltage) output according to the phase difference is input to the LPF 16 to extract the DC component. , VCO17, and oscillates a clock whose phase matches that of the HD 1H before.

FIG. 2 is a block diagram of a main part of another embodiment of the digital image processing circuit according to the present invention. In the figure, reference numeral 21 is a delay line, for example, a glass delay line, and an input video signal is 1
It is delayed by H and input to the digital processing circuit 4. The other reference numerals are the same as those in FIG.

Next, the operation of the digital image processing circuit according to the present invention will be described. First, in the case of FIG. 1, a video signal from the outside is input to the delay circuit 1, sampled by the A / D conversion unit 11 using the clock from the oscillator 14, converted into a digital signal, and input to the memory 12. Writing is performed by the clock from the oscillator 14. Then, the video data is read out after a required time delay, input to the D / A converter 13, converted into an analog video signal, and input to the digital processing circuit 4. The reading timing with respect to the writing of the memory 12 is appropriately set so that the output of the D / A converting unit 13 is delayed by 1H with respect to the input of the A / D converting unit 11.

On the other hand, the video signal is input to the sync separation circuit 2, the HD is separated, and the HD is input to the PLL circuit 3. The PLL circuit 3 inputs a clock oscillated by the VCO 17, for example, 28.6 MHz to the frequency divider 18, frequency-divides it by, for example, 910, returns it to the phase comparator 15, and outputs the HD from the sync separation circuit 2.
And the phase are compared, the signal (voltage) output according to the phase difference is input to the LPF 16 to extract the DC component, and this signal is applied to the VCO 17 to generate a clock whose phase matches that of HD, and to perform digital processing. Supply to the circuit 4.

In the case of FIG. 2, the video signal is input to the delay line 21 having a delay time of 1H, which is composed of, for example, a glass delay line,
It is delayed by 1H and input to the digital processing circuit 4. The sync separation circuit 2 and the PLL circuit 3 are the same as those in FIG.

As described above, in the digital processing circuit 4, the video signal delayed by 1H by the delay circuit 1 or the delay line 21 and the clock whose phase is matched with the HD of 1H before by the PLL circuit 3, that is, the video signal A clock having the same H and a phase-matched HD is input. Thus, for example, a VTR
As described above, even when the synchronization stability of the video signal source is not necessarily good, the timing of the video signal and the clock are not deviated, and the normal digital processing of the video signal is performed.

[0014]

As described above, according to the digital image processing circuit of the present invention, the video signal is input to the digital processing circuit with a delay of 1H, and is digitalized by the clock synchronized with HD 1H before the PLL circuit. Since the processing is performed, normal digital processing is performed even when processing a video signal from a signal source whose synchronization stability is not good because the video signal to be processed and the clock have the same phase.

[Brief description of the drawings]

FIG. 1 is a block diagram of essential parts of an embodiment of a digital image processing circuit according to the present invention.

FIG. 2 is a block diagram of a main part of another embodiment of the digital image processing circuit according to the present invention.

FIG. 3 is a principal block diagram of an example of a conventional digital image processing circuit.

[Explanation of symbols]

 1 Delay Circuit 2 Sync Separation Circuit 3 PLL Circuit 4 Digital Processing Circuit 11 A / D Converter 12 Memory 13 D / A Converter 14 Oscillator 21 Delay Line

Claims (4)

[Claims] 1. In the image processing of an analog video signal by a digital processing circuit, the video signal is 1
A delay circuit for delaying a horizontal scanning period and a PLL circuit for generating a first clock in phase with a horizontal synchronizing signal separated from the video signal are provided, and the video signal from the delay circuit is input to a digital processing circuit. A digital image processing circuit adapted to perform digital image processing using the first clock from the PLL circuit. 2. The delay circuit comprises an oscillator that oscillates a second clock, an A / D converter that samples the video signal with a clock from the oscillator and converts the video signal into a digital signal, and an A / D converter. A memory which inputs video data and writes and reads by a second clock from the oscillator, and converts the data read from the memory into an analog signal by using the second clock from the oscillator and outputs the analog signal to the digital processing circuit. The digital image processing circuit according to claim 1, wherein the digital image processing circuit comprises an input D / A converter. 3. The digital image processing circuit according to claim 2, wherein the oscillator is a crystal oscillator using a crystal oscillator. 4. The digital image processing circuit according to claim 1, wherein the delay circuit is a delay line that delays a video signal for one horizontal scanning period.