JPH09107253A - Amplification circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To save the power furthermore by suppressing the power consumption in an operational amplifier in the standby state. SOLUTION: An operational amplifier 10 which amplifies an input signal, a control means which turns off the output transistor TR of the operational amplifier 10 or a TR driving this output TR at the time of giving one logical state to a specific terminal 15, and a resistance element 17 interposed between a voltage source 18 having a potential corresponding to one logical state and the specific terminal 15 are provided. Since the specific terminal 15 is pulled up or down by the voltage source 18 having the potential corresponding to one logical state, the output TR of the operation amplifier 10 (or the TR driving this output TR) is kept turned off as long as a signal in the other logical state is applied to the specific terminal 15, and not only the current flowing to a speaker is eliminated but also the internal current of the operational amplifier is suppressed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an amplifier circuit used in a voice sound amplification section of a telephone or the like, and more particularly to an amplifier circuit suitable for use in a small communication device such as a cordless telephone, a mobile telephone or a handy transceiver. In general, this type of small communication device operates on a battery and has the advantage of being highly portable, but on the other hand, the battery occupies most of the volume and weight, so a very large battery cannot be installed, Those that consume as little power as possible are required.

[0002]

2. Description of the Related Art A portion of a small-sized communication device that consumes the most power is a voice loudspeaker for driving a speaker, and power consumption of an amplifier circuit in the speaker is not negligible.
Therefore, conventionally, in a no-call state (standby state), the amplifier circuit and the speaker are disconnected.
So-called mute state control was performed.

FIG. 5 is a conceptual diagram thereof, and an amplifier circuit 1 includes an operational amplifier 4 which constitutes a known inverting amplifier by an input resistor 2 and a feedback resistor 3, and a switch is provided between an output of the operational amplifier 4 and a speaker 5. The element 6 is put in, and the on / off of the switch element 6 is controlled by the mute detection circuit 7. In the standby state, since the speaker 5 is disconnected, the driving current i of the speaker 5 becomes zero, and the power consumption can be suppressed accordingly.

[0004]

However, in such a conventional amplifier circuit, although the drive current i of the speaker 5 can be reduced to zero, the current consumed inside the operational amplifier 4 remains unchanged. There was a technical problem to be solved in terms of power saving.

[0005]

According to the present invention, in order to suppress power consumption inside an operational amplifier in a standby state and to further save power, an operational amplifier for amplifying an input signal and one for a specific terminal are provided. Control means for turning off the output transistor of the operational amplifier or the transistor driving the output transistor when a logic state is given;
It is characterized by including a voltage source having a potential corresponding to one logic state and a resistance element interposed between the specific terminal.

Alternatively, in addition to each of these items, a switch element for turning on / off the connection between the specific terminal and the external terminal, and the switch for a predetermined time after the power is turned on or the standby state is restored. Holding means for holding the element in an off state. In the present invention, a particular terminal is pulled up or down to a voltage source having a potential corresponding to one logic state. Therefore, the output transistor of the operational amplifier (or the transistor which drives the output transistor) continues to be turned off unless a signal of another logic state is applied to the specific terminal. As a result, not only the current flowing through the speaker can be reduced to zero, but also the internal current of the operational amplifier can be suppressed. Alternatively, if a specific terminal is connected to an external terminal (terminal for inputting a signal in another logic state) after a predetermined time (time required for stable operation of the operational amplifier) after returning from the standby state, the speaker It is preferable because noise can be prevented from occurring.

[0007]

Embodiments of the present invention will be described below with reference to the drawings. 1 and 2 are diagrams showing a first embodiment of an amplifier circuit according to the present invention. In FIG. 1, reference numeral 10 denotes an operational amplifier, which has an input resistor 12 connected between a negative phase input (−) and an input terminal 11 and a feedback resistor connected between a negative phase input and an output terminal 13. 14 is connected to form a known inverting amplifier having an amplification degree A (A = −R _f / R _s ; where R _s is the resistance value of the input resistor 12 and R _f is the resistance value of the feedback resistor 14).

Reference numeral 15 denotes a power-down terminal of the operational amplifier 10 (corresponding to a specific terminal described in the gist of the invention; hereinafter abbreviated as "PD terminal"), and the operational amplifier 10 has the PD terminal 15 in the L logic state. When it becomes (corresponding to one logic state described in the gist of the invention), the internal operation is stopped. Reference numeral 16 denotes an external terminal connected to the PD terminal 15. A control signal (for example, a standby signal) of L logic active is applied to the external terminal 16 and a resistance element (corresponding to the resistance element described in the gist of the invention). It is pulled down to a ground (voltage source having a potential corresponding to one logic state) 18 via 17.

Although the positive-phase input (+) of the operational amplifier 10 is connected to the ground in the figure, it is not limited to this.
It may be connected to any reference voltage. Although not particularly limited, FIG. 2 is an internal configuration diagram showing an example of an operational amplifier with a PD terminal. In this figure, 20 is a VB (bias) terminal, 21 is a negative phase input terminal, 22 is a positive phase input terminal,
23 is a PD terminal, 24 is a high potential side power supply terminal (VDD terminal), 25 is a low potential side power supply terminal (GND terminal), and 26 is an output terminal.

The VB terminal 20 is connected to the gate electrodes of the first p-channel MOS transistor T _P1 and the second p-channel MOS transistor T _P2 , and the negative phase input terminal 21 is the gate of the third p-channel MOS transistor T _P3 . Connected to the electrodes. The positive phase input terminal 22 is connected to the gate electrode of the fourth p-channel MOS transistor T _P4 , and PD
The terminal 23 is connected to the gate electrode of the first n-channel MOS transistor T _N1 . The VDD terminal 24 is a source electrode of T _P1 and T _P2 (referred to as an upper electrode in the drawing for convenience;
The same applies to the following) and the substrate of T _{P1 to} T _P4 , and the GND terminal 25 is connected to the drain electrodes and substrates of T _N1 and the second to fourth n-channel MOS transistors T _{N2 to} T _N4. There is. The output terminal 26 is connected to the drain electrode of T _P1 , the source electrode of T _N4 , and one terminal of the phase compensating capacitor C.

T _{P1 to} T _P4 and T _N2 and T _N3 constitute a first amplification stage 27 for differentially amplifying the potential difference between the negative phase input terminal 21 and the positive phase input terminal 22, and T _P2 and T _{P2 N4} and C ₁ are first
A final amplification stage 28 is constructed, in which the output of the amplification stage 27 is phase-compensated and output from the output terminal 27 to the outside. Here, T _N1 is turned on when the PD terminal 23 is in the H logic state. T
When _N1 is turned on, since the gate electrode of T _N4 is connected to the GND terminal 25 through the T _N1, T _N4 is forced off, substantial operation as the operational amplifier is stopped. Therefore, T _N1 has a function as a control means for turning off T _N4 as the output transistor of the operational amplifier when one logic state is given to the PD terminal 23. Although FIG. 2 shows an operational amplifier having two amplification stages, the configuration is not limited to this. For example, there may be a third amplification stage after the second amplification stage 28, in which case T _N4 may be considered as a transistor driving an output transistor (not shown) of the third amplification stage.

Again, in FIG. 1, the control signal is in the L logic state ... In addition, in FIG. 2, one logic state is the H logic state, and in order to match this logic state, the resistance element 17 is not the ground 18 but the ground element 18. The control signal may be set to H logic active while being connected to a voltage source (for example, VDD) having a potential corresponding to the H logic state. When set to ..., the substantial operation of the operational amplifier 10 is stopped. For this reason,
Speaker connected to the output terminal 13 (see reference numeral 5 in FIG. 5)
Current becomes zero, and the current consumed inside the operational amplifier 10 is also suppressed. That is, power consumption can be significantly reduced only by activating the control signal. However, in the present embodiment, since the PD terminal 15 is pulled down to the ground 18 via the resistance element 17, for example, when returning from the standby state, Even if the logic determination of the control signal is delayed, the operation of the operational amplifier 10 can be stopped by the pull-down potential of the PD terminal 15 (potential corresponding to one logic state), and the power saving effect at the time of standby recovery can be obtained without any trouble. The advantageous effect that it is possible is obtained.

FIGS. 3 and 4 are diagrams showing a second embodiment of the amplifier circuit according to the present invention. The same components as those in the first embodiment are designated by the same reference numerals and the description thereof will be omitted. In FIG. 3, 30 is a PD terminal 15 (specific terminal)
A switch element for turning on / off the connection between the external terminal 16 and the external terminal 16 is a holding means for holding the switch element 30 in the off state until a predetermined time elapses after the power is turned on or the standby state is restored.

FIG. 4 is a block diagram showing an example of the switch element 30 and the holding means 31, although not particularly limited thereto. In this figure, the switch element 30 is composed of a transfer gate, and the number of holding means 31 is n (three in the figure).
A power supply voltage level detection circuit 36 including the series MOS transistors 32 to 34 and one resistance element 35,
Pre-stage inverter gate group 39 configured by connecting an even number (two in the figure) of inverter gates 37 and 38 in series
And an odd number (three in the figure) of inverter gates 40 to 4
Rear-stage inverter gate group 4 configured by connecting 2 in series
And 3. According to this configuration, the power supply voltage VDD
Is detected by the power supply voltage detection circuit 36, the output of the preceding-stage inverter group 39 becomes the H logic state after a delay of two stages of inverter gates from that point, and the output of the preceding-stage inverter group 39 is further delayed by three stages of the inverter gate. The output of 43 goes to the L logic state. Therefore, the switch element 30 does not turn on until after a delay time of at least 5 stages of inverter gates has elapsed, and therefore a predetermined time (in the configuration of FIG. 4, the inverter gates are restored from the return of the standby state (return of the power supply voltage VDD)). Advantageously, the pull-down potential can be continuously applied to the PD terminal 15 of the operational amplifier 10 for a delay time of 5 stages, and the operation of the operational amplifier 10 can be stopped to prevent abnormal noise from being generated from the speaker. The effect is obtained.

Although the predetermined time is set using the delay of the inverter gate in FIG. 4, the present invention is not limited to this.
For example, periodic signals such as clock signals may be counted. In short, it suffices that the switch element 30 can be turned on after the operation of the operational amplifier 10 is stabilized.

[0016]

According to the present invention, since a specific terminal is pulled up or pulled down to a voltage source having a potential corresponding to one logic state, unless a signal of another logic state is applied to the particular terminal. The output transistor of the operational amplifier (or the transistor driving the output transistor) continues to be turned off, and as a result, the current flowing through the speaker can be reduced to zero, and the internal current of the operational amplifier can be suppressed.

Alternatively, it is possible to connect a specific terminal and an external terminal (a terminal for inputting a signal in another logic state) after a predetermined time (time required for stabilizing the operation of the operational amplifier) after returning from the standby state. This is preferable because it can prevent noise from being generated from the speaker.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of a first embodiment.

FIG. 2 is a configuration diagram of an example of an operational amplifier having a PD (power down) terminal.

FIG. 3 is a configuration diagram of a second embodiment.

FIG. 4 is a block diagram showing an example of a switch element and a holding means of a second embodiment.

FIG. 5 is a configuration diagram of a conventional example.

[Description of _{Reference Signs} ] T _N4 : Fourth n-channel MOS transistor (output transistor) T _N1 : First n-channel MOS transistor (control means) 10: Operational amplifier 15: PD terminal (specific terminal) 16: External terminal 17 : Resistive element (resistive element) 18: ground (voltage source) 30: switch element 31: holding means

Claims (2)

[Claims] 1. An operational amplifier for amplifying an input signal, and a control means for turning off an output transistor of the operational amplifier or a transistor driving the output transistor when one logic state is given to a specific terminal, An amplifier circuit comprising: a voltage source having a potential corresponding to a logic state; and a resistance element interposed between the specific terminal. 2. A switch element for turning on / off a connection between the specific terminal and an external terminal, and a holding element for holding the switch element in an off state until a predetermined time elapses after the power is turned on or the standby state is restored. An amplifier circuit according to claim 1, further comprising: