JP3528725B2 - Power amplifier circuit - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a power amplifier circuit, and more particularly to a push-pull amplifier circuit having a CMOS transistor and operating in class AB. The present invention relates to a power amplifier circuit suitable for use in, for example, a power-saving device such as a mobile phone device or a portable game machine that needs to ensure battery life.

[0002]

2. Description of the Related Art Conventionally, push-pull type power amplifier circuits having CMOS transistors have been widely used.
FIG. 3 shows the configuration of a conventional power amplifier circuit of this type. In the figure, the power amplifier circuit includes a bias circuit 20, a differential amplifier circuit 22, a level shift circuit 24, and an output circuit 2.
It has 6. The differential amplifier circuit 22 includes PMOS transistors T2 and T5 that form a current mirror circuit, and +
A differential input circuit including an NMOS transistor T6 having a gate terminal to which the side input signal IN is input, an NMOS transistor T3 having a − side input signal IN to the gate terminal, and an NMOS transistor T4 forming a constant current source. have.

The sources of the PMOS transistors T2 and T5 forming the current mirror circuit are connected to the positive voltage power source VDD. The bias circuit 20 has an operating bias point setting resistor R1 and a bias voltage generating NMOS transistor T1, and is inserted between the positive voltage power supply VDD and the negative voltage power supply VSS. The operating point of the NMOS transistor transistor T4 forming the differential amplifier circuit 22 is set in the saturation region by the bias circuit 20, and it functions as a constant current source. The level shift circuit 24 has N
The output circuit 26 has MOS transistors T9 and T10, and the output circuit 26 is complementarily connected to the PMOS transistor T.
7, has an NMOS transistor T8, and has a PMOS
The output terminal out is connected to the commonly connected drains of the transistor T7 and the NMOS transistor T8.

In the power amplifier circuit configured as described above, the bias circuit 20 adds a voltage obtained by subtracting the voltage drop at the transistor T1 from the difference voltage between the positive power supply voltage VDD and the negative power supply voltage VSS to the resistor R1, and NB Resistance R1 at the node
A current flows through the DC circuit to which the NMOS transistor T1 is connected. The magnitude of this current is supplied to each element through the NB node in the form of a bias voltage, and the operating point of each element is determined. In the differential amplifier circuit 22, the NMOS transistors T3 and T6, and the PMOS transistors T2 and T6.
Those having the same characteristics as 5 are used. The N3 node is a common connection point of the PMOS transistor T5 and the NMOS transistor T6, and the N3 node voltage V _N3 is a difference voltage (V _{+ IN)} between the + side input signal voltage V _{+ IN} and the − side input signal voltage V _−IN.
It greatly fluctuates according to the change of −V _−IN ). That is, PM
Using the load resistance due to the OS transistor T5, NMOS transistors T6 drain current I _D and the drain-source voltage V _DS, to enhance the voltage gain by an active load.

The output circuit 26 includes an NMOS transistor T
8 is an active load that operates as the load of the PMOS transistor T7, and a signal is applied to the NMOS transistor T8 through the NMOS transistor T9 to operate. The PMOS transistor T7 is N3
The current of the PMOS transistor T7 changes according to the node voltage V _N3 . The capacitor Cc lowers the gain at high frequencies and prevents oscillation. This change in current is converted into a large-amplitude signal by the active load and output terminal out
Is output from. Level shift circuit 24 converts the voltage level of the differential voltage supplied from the differential amplifier circuit _{22 (V + IN -V -IN)} , are supplied to the output circuit 26.

When the class A operation for linearly amplifying the signal is performed, the bias current is always supplied regardless of the presence or absence of the input signal. On the other hand, in the case of a high power amplifier circuit, B
In order to perform the class operation, the bias voltage is set to zero voltage to prevent the bias current from flowing when there is no signal. But,
In class B operation, crossover distortion occurs due to the nonlinearity of the characteristics near zero current. Therefore, in order to prevent crossover distortion, a small amount of bias current is always applied A
Class B operation is used.

[0007]

However, in the conventional power amplifier circuit of this type, the power consumption is large because an idling current is supplied to the output circuit to some extent even when no signal is input. was there.
Particularly in portable electronic devices such as mobile phone devices, the reduction of power consumption has been a major issue because the electronic circuits are powered by batteries. Further, since it is necessary to mount a circuit in a limited space in a portable device, a low-voltage drive circuit suitable for an IC is desired.

The present invention has been made in view of the above circumstances, and an object thereof is to provide a power amplifier circuit which can be driven at a low voltage, has high bias stability, and has high linearity.

[0009]

To achieve the above object, according to the Invention The, the invention according to claim 1, + side input signal and - a differential amplifier circuit for amplifying a difference voltage signal between the negative input signal, the An amplifier circuit for amplifying an output signal of the differential amplifier circuit, a first PMOS transistor and a first NMO which are complementarily connected to each other.
It consists of an S transistor, and the PMOS transistor and N
An output circuit in which a connection point of the MOS transistor is connected to a load, and a first PMOS transistor that constitutes the output circuit.
The transistor and the first NMOS transistor
Second PMOS transistor forming a mirror circuit
And the second NMOS transistor, and
A second PMOS transistor and a second NMOS transistor
Bias setting means for setting the current flowing through the transistor
And a current boost circuit that supplies a current obtained by multiplying the output signal current of the amplifier circuit to a predetermined multiplication factor to the load via the output circuit, and the current boost circuit is usually
Is the second PMOS transistor and the second NMOS
The bias is applied so that a minute current flows through the transistor.
The bias is set by the setting means, and the differential amplification is performed.
Amplifies when a signal is input to the circuit
Current that is a superposition of the generated signal current and the minute current flows.
It is characterized in that it is configured to be .

The invention described in claim 2 is the same as claim 1.
In the power amplifier circuit described in the paragraph 1,
The first PMOS transistor forming the rent mirror circuit
The transistor and the first NMOS transistor and the second P
Of the MOS transistor and the second NMOS transistor
Characterized by being set by the transistor size ratio
It

[0011]

According to the present invention , the differential amplifier circuit for amplifying the differential voltage signal between the + side input signal and the-side input signal, and the amplifier circuit for amplifying the output signal of the differential amplifier circuit are complementarily provided. Connected first PMOS transistor and first NMO
It consists of an S transistor, and the PMOS transistor and N
An output circuit in which a connection point of the MOS transistor is connected to a load, and a current boost circuit for supplying a current obtained by multiplying the output signal current of the amplifier circuit to a predetermined multiplication factor to the load via the output circuit Therefore, low voltage driving is possible, and the idle current can be suppressed to an extremely small current value, and therefore the bias stability can be increased. Further, since the ratio of the current supplied to the current boost circuit and the current supplied to the output circuit can be set accurately in the process, a power amplification circuit having high linearity can be obtained.

[0013]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 shows the configuration of a power amplifier circuit according to an embodiment of the present invention. In the figure, the power amplifier circuit according to an embodiment of the present invention, the positive side input signal and - a differential amplifier circuit 10 for amplifying a difference voltage signal between the positive input signal,
Amplifier circuit 12 for amplifying the output signal of the differential amplifier circuit 10.
And a complementary connected PMOS transistor MP6 and NMOS transistor MN7. The drain of the PMOS transistor MP6 and the NMOS transistor M
The output circuit 16 in which the connection point to which the drain of N7 is connected is connected to the load RL via the output terminal OUT, The current boost circuit 14 supplies the load RL via the current boost circuit 14. The load RL is a speaker used in a portable electronic device such as a mobile phone device in this embodiment.

The differential amplifier circuit 10 has a + side input signal (+ I
N) is input to the PMOS transistor MP1, and the source of the PMOS transistor MP2 to which the − side input signal (−IN) is input are commonly connected, and a differential input circuit is connected to the power supply VDD via the current source 11. , NM connected to the drain side of the PMOS transistors MP1 and MP2
The current mirror circuit includes OS transistors MN1 and MN2. Further, the amplifier circuit 12 is
It is composed of an NMOS transistor NM3 for amplifying the output signal of the differential amplifier circuit 10, and a constant current source 13 connected between the drain of the NMOS transistor NM3 and the power supply VDD. The source of the NMOS transistor NM3 is the power supply VS
It is connected to S.

The current boost circuit 14 has a PMOS transistor MP6 and an NMOS transistor MN7 forming an output circuit 16, and a PMOS transistor MP3 and an NMOS transistor NM5 forming a current mirror circuit, respectively. Furthermore, the PMOS transistor M
NMOS in series with P3 and NMOS transistor NM5
The transistor MN4 and the PMOS transistor MP4 are connected. The drain of the PMOS transistor MP3 is connected to the drain of the NMOS transistor MN4,
The source of the NMOS transistor MN4 is connected to the source of the PMOS transistor MP4. Also, PMO
The drain of the S transistor MP4 is connected to the drain of the NMOS transistor MN5, and the source of the NMOS transistor MN5 is connected to the power supply VSS.

The current boost circuit 14 is an NMOS.
The sources of the transistor MN4 and the PMOS transistor MP4 and the NMOS transistor MN6 and the PMOS transistor MP5 that form the current mirror circuit are connected in common, and the drain of the NMOS transistor MN6 is connected to the power supply VDD via the resistor R2 and the source of the PMOS transistor MP5. The drain is the power supply VS through the resistor R3.
S is connected to each. The resistors R2 and R3 are bias resistors, and the resistance values of the resistors R2 and R3 set the currents flowing through the NMOS transistor MN6 and the PMOS transistor MP5 when no signal is input.

Normally, that is, when no signal is input, the PMO forming a current mirror circuit together with the PMOS transistor MP6 and the NMOS transistor MN7 of the output circuit 16.
S transistor MP3, NMOS transistor MN5
And resistors R2, R3 and NMOS transistor MN6,
The bias is set by MP5 so that a minute current (for example, 1 μA) flows, and when a signal is input to the differential amplifier circuit 10, the signal current amplified by the amplifier circuit 12 and the minute current are superimposed. Current is flowing.

On the other hand, the PMOS transistors MP3 and MP
4. If the transistor sizes of the NMOS transistors MN4 and MN5 are set to 1, the transistor sizes of the PMOS transistor MP6 and the NMOS transistor MN7 forming the output circuit are set to 300, for example.
A resistor R1 and a capacitor C1 connected between the drain and source of the NMOS transistor MN2 and a capacitor Cc connected between the source of the PMOS transistor MP4 and the output terminal OUT are for phase compensation.

The operation of the power amplifier circuit having the above configuration will be described. In the above configuration, when the signal is not input to the differential amplifier circuit 10, the current boost circuit 14
, The current set by the resistance values of the resistors R2 and R3 flows in the NMOS transistor MN6 and the PMOS transistor MP5. Then, the NMOS transistor MN
6, a minute current (for example, 1 μA in the present embodiment) according to the transistor ratio flows through the NMOS transistor MN4 and the PMOS transistor MP4 that form a current mirror circuit with the PMOS transistor MP5, and this minute current is the PMOS transistor MP3 and the NMOS. It also flows to the transistor MN5.

As a result, the PMOS transistor MP3,
A PMOS transistor MP6 and an NMOS transistor MN7 that form a current mirror circuit with the NMOS transistor MN5 include a PMOS transistor MP3 and an NMOS transistor MN7, respectively.
Transistor MN5 and PMOS transistors MP6, N
The transistor ratio with the MOS transistor MN7 is 1: 3.
Since the transistor is made to be 00,
When no load is applied, an idle current of 300 μA flows through the PMOS transistor MP6 and the NMOS transistor MN7 of the output circuit 16. This current value is a very small value as compared with the conventional one.

Next, the load RL is connected to the output terminal OUT of the power amplifier circuit, and the input terminal 100 is connected to the differential amplifier circuit 10.
When an AC signal is input from 101, the differential amplification signal output from the differential amplification circuit 10 is amplified to a predetermined level by the amplification circuit 12, and the positive phase component of the AC signal is boosted by the current boost from the power supply VDD. The reverse phase component of the AC signal flows from the drain side of the NMOS transistor MN3 of the amplifier circuit 12 to the PMOS transistor of the current boost circuit 14 via the PMOS transistor MP3 of the circuit 14 and the NMOS transistor MN4. MP4, NMOS transistor M
A signal current flows into N5.

During the period in which the positive phase component of the alternating current signal output from the amplifier circuit 12 is output, the PMOS transistor M
A signal current does not flow in P4 and NMOS transistor MN5, but a signal current flows only in PMOS transistor MP3 and NMOS transistor MN4. In addition, the amplifier circuit 12
In the period in which the opposite phase component of the AC signal current, which is the output of the above, is output, the signal current does not flow in the PMOS transistor MP3 and the NMOS transistor MN4, and the signal current flows only in the PMOS transistor MP4 and the NMOS transistor MN5. As a result, as shown in FIG. 2, during the period in which the positive phase component of the alternating current signal output from the amplifier circuit 12 is output, the PMOS transistor MP of the current boost circuit 14 is output.
3 and PM of the output circuit 16 which constitutes the current mirror circuit
In the OS transistor MP6, a current IMP6 in which the idle current I0 is superimposed with a current 300 times as large as the AC signal current flows, and this current flows to the load RL via the output terminal OUT (FIG. 2B).

On the other hand, during the period in which the opposite phase component of the AC signal current output from the amplifier circuit 12 is output, the NMOS transistor MN of the output circuit 16 forming a current mirror circuit together with the PMOS transistor MN5 of the current boost circuit 14.
A current IMN7 in which the idle current I0 and a current which is 300 times the AC signal current are superposed on the current I7 flows from the load RL side through the output terminal OUT (FIG. 2 (C)). Therefore, the load current IL, which is a combination of the current IMP6 and the current IMN7, flows through the load RL.

As described above, in the power amplifier circuit according to this embodiment, the output circuit 16 is operated when there is no load (when no signal is input).
The idle current flowing through is suppressed so as to have an extremely small current value, and a large current can be supplied to the load RL at the time of load (signal input). In the present embodiment, for example, assuming that the signal current output from the amplifier circuit 12 is 1 mA, a current of ± 300 mA can be supplied to the load RL.

[0025]

As described above, according to the present invention, a differential amplifier circuit for amplifying a differential voltage signal between a + side input signal and a − side input signal, and an output signal of the differential amplifier circuit are provided. An amplifying circuit for amplifying, a first PMOS transistor and a first NMOS transistor connected in a complementary manner, and an output circuit in which a connection point of the PMOS transistor and the NMOS transistor is connected to a load; Since it has a current boost circuit that supplies a current obtained by multiplying the output signal current by a predetermined factor to the load via the output circuit, low voltage driving is possible and the idle current becomes a very small current value. Therefore, the bias stability can be increased. Further, since the ratio of the current supplied to the current boost circuit and the current supplied to the output circuit can be set accurately in the process, a power amplification circuit having high linearity can be obtained.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a configuration of a power amplifier circuit according to an embodiment of the present invention.

FIG. 2 is a waveform diagram showing an operating state of an output circuit in the power amplifier circuit shown in FIG.

FIG. 3 is a circuit diagram showing a configuration of a conventional power amplifier circuit.

[Explanation of symbols]

10, 22 Differential amplifier circuit 12 amplifier circuit 14 Current boost circuit 16, 26 Output circuit 20 bias circuit 24 level shift circuit

Claims (2)

(57) [Claims] 1. A + side input signal and - a differential amplifier circuit for amplifying a difference voltage signal between the negative input signal, an amplifying circuit for amplifying the output signal of the differential amplifier circuit, the complementarily connected An output circuit including a first PMOS transistor and a first NMOS transistor, the connection point of the PMOS transistor and the NMOS transistor being connected to a load, and a first PMOS transistor and a first PMOS transistor forming the output circuit.
And the first NMOS transistor and a current mirror, respectively
A second PMOS transistor and a second
NMOS transistor and the second PM when no signal is input
Flow to the OS transistor and the second NMOS transistor
And a bias setting means for setting a current, and a current boost circuit that supplies a current to multiply the output signal currents of the amplifier circuit at a predetermined ratio to the load via the output circuit, the current The boost circuit is usually the second PMOS transistor.
The transistor and the second NMOS transistor are
Bias by the bias setting means so that the flow
Has been set and a signal has been input to the differential amplifier circuit.
The signal current amplified by the amplifier circuit and the
A power amplifier circuit characterized in that a current in which a small current is superimposed flows . 2. The predetermined magnification is a current mirror circuit.
Forming a first PMOS transistor and a first PMOS transistor
NMOS transistor and the second PMOS transistor
And the transistor size of the second NMOS transistor
2. The ratio according to claim 1, which is set according to the ratio.
Power amplifier circuit.