JPH09102888A - Synchronization processing unit and its processing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To realize a synchronization processing unit and its processing method where the position of a horizontal synchronizing signal is accurately detected even when the amplitude of a video signal or the like with bad linearity is fluctuated. SOLUTION: A video signal is delayed by a prescribed period L1 by loading a counter in response to a start pulse whose start point is a trailing of a Hsync to detect a 0IRE (0%) level of the input video signal for a detection period range W1. Similarly, the signal is delayed by a prescribed period L2 to detect a 40IRE (100%) level of the input video signal for a detection period range W2. A 50% level is calculated from them by an arithmetic operation. Furthermore, the video signal is delayed by a prescribed period L3 to detect a 50% point of a trailing edge of tail end of a signal B1 for a detection period range W3 and a calculated 50% level is used for a cross point of the 50% point of the tail end trailing edge of the signal B1 to obtain a horizontal synchronizing position pulse (A). Thus, the horizontal synchronizing position is stably detected.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a synchronous processing apparatus and a processing method thereof, and more specifically, for example, a second generation E
By improving the synchronous processing device of DTV and its processing method,
The present invention relates to a synchronization processing device and a processing method thereof capable of accurately detecting a horizontal synchronization position.

[0002]

2. Description of the Related Art In recent years, with the remarkable development of telecommunication technology, wireless and wired new media have appeared one after another. High-definition televisions with high image quality and an aspect ratio of 16: 9 and wide-screen televisions with an aspect ratio of 16: 9 are also popular. A second-generation EDT that achieves widening and high image quality while maintaining compatibility with current receivers
V (hereinafter simply referred to as "EDTV-II") has also started broadcasting. The synchronous processing device and the processing method thereof of the present invention are suitable for application to video processing devices in general, but an EDTV-II receiver that has reached a practical stage will be described as an example.

The EDTV-II maintains a compatibility with the current television broadcasting, and has a frequency bandwidth of 6 M per channel.
In order to widen the screen and improve the image quality in Hz, the letter box format is adopted as the transmission format of the wide image. Further, in this broadcasting system, both the broadcasting system and the receiving system have a hierarchical structure capable of both interlaced scanning which is easy to introduce and progressive scanning which facilitates high image quality. For EDTV-II, B
TA (Broadcasting Technology Association), issued on December 9, 1994, "Second Generation E"
The details are described in "DTV system examination report". The present invention also relates to Japanese Patent Application No. 7-74 filed previously by the applicant.
The present invention relates to the "synchronization processing device and the synchronization processing method" video signal processing device "described in the specification of No. 005.

An outline of the identification control signal of the EDTV-II according to the present invention will be described with reference to FIG. Figure 3 shows EDTV-
It is a figure which shows the outline | summary of the identification control signal of II, (a) is a figure which shows an identification control signal waveform, (b) is a figure which shows a bit position and identification content.

The identification control signal used for automation of various controls on the receiver side in FIG. 3 (a) is the control information contained in the 22/285 line of each field, and is a horizontal synchronizing signal Hsync (hereinafter referred to as "hsync"). , Simply referred to as "Hsync")
1, a color burst signal 2 having a reference waveform of 9 cycles in π (radian) phase, an NRZ (Non-Return Zero) signal 3 to which 1/0 is assigned with identification commands B1 to B5, also "1" or " If the information of "0" is modulated and is in phase with the color burst signal 2 (π phase), the identification commands B6 to B23 defined by "1" are interpolated if the phase is opposite (0 phase). Color subcarrier (fsc)
4 and B25 to B27, which is generally composed of the confirmation signal 5 having a frequency of 2.04 MHz. The identification command is an allocation number having a confirmation function for distinguishing from an existing video signal composed of 1 bit = 28 samples,
B1 to B to eliminate the influence of noise such as ghost
5 is the NRZ waveform, and most of the rest is the color subcarrier (fs
This is a modulated wave of c).

The confirmation signal 5 has a carrier frequency (4 / 7f).
sc) modulated 2.04MHz period, ie 1 period 7
Configured as a sample clock. That is, (4 /
The phase of the subcarrier of 7 fsc) is extracted and used as the synchronization timing for decoding the reinforcement signal.
The identification commands B1 bit and B2 bit assigned to the NRZ signal 3 are fixed to "1" and "0", respectively, as reference signals of the identification control signal. Further, the pixel number (Pixel) in the horizontal direction is strictly defined. As an example thereof, the falling point of Hsync1 is defined as "785", and the trailing point of the color burst signal 2 is "909". It will be cleared at "Point" and will start from "0" again. The rising 50% point of the B1 bit inside the NRZ is "7", and the falling 50% point is "3".
5 ".

FIG. 1B is a diagram showing bit positions and identification contents as mode identification information, which is composed of a bit number, identification contents such as a reference signal, and a status section storing 1/0 control information. There is. If you explain a part of it as essential mode identification information, letterbox B
3 is the top priority and necessary information for specifying the display format of the screen on the 16: 9 receiver, the status "0" in normal (4: 3) and the status "1" in letterbox (16: 9). "Indicated by. B8 bit or B1
The presence / absence of various 0-bit reinforcement signals is necessary information for the purpose of preventing S / N deterioration when there is no reinforcement signal. The B11-bit HH precombing information indicates whether or not precombing is being performed on the transmitting side. Note that each bit position and identification content may be adjusted in the future.

Next, the EDTV-II synchronization processing apparatus and its processing method will be described with reference to FIG. Figure 4 shows EDT
It is a figure which shows the detection operation of the identification control signal of V-II,
(A) is a timing chart showing a part of the identification control signal and a horizontal synchronizing position detecting operation, and (b) is a timing chart showing a horizontal synchronizing position detecting operation when the amplitude of the identifying control signal becomes small. is there.

Here, the EDTV-II synchronization processing device is used for detecting the EDTV-II identification control signal and decoding various reinforcing signals to be superimposed on the main image portion and the non-image portion. This is a circuit that generates a horizontal reference timing (horizontal synchronization position). In the “synchronization processing device and synchronization processing method” of the prior application example, this horizontal synchronization position is detected from the phase of the confirmation signal (not shown) of the identification control signal. It was something to do. The horizontal sync position is detected from the phase of the confirmation signal of the identification control signal of the prior application example, and there is also a method of detecting from the 50% falling point of the B1 bit of the NRZ signal. The essence of the present invention is that the falling edge of the B1 bit of the NRZ signal described above 5
The horizontal synchronization position is generated from the 0% point, and the pixel number, for example, “3
5 "is determined, and various reinforcing signals HH, VT, VH are decoded with this horizontal synchronizing position as a reference.

Therefore, the EDTV-II synchronization processing device in the present invention is a circuit for detecting the horizontal synchronization position pulse used when decoding the information superimposed on the EDTV-II identification control signal. The synchronization position is a circuit for detecting the pixel number (defined as "35") at the 50% point of the trailing edge of the reference bit B1 of the identification control signal. When detecting the horizontal sync position pulse, Hsy
After the approximate relative position of the trailing edge 50% point of B1 from the leading edge falling point 50% of nc1 is determined, the position is detected. In the figure, the trailing edge 5 of B1
The position of the 0% reference level will be described as [A].

To explain the operation of detecting the horizontal synchronizing position, a start pulse 6 is generated starting from the 50% point where the leading edge of Hsync1 of the identification control signal falls, and in response to the start pulse 6, a start pulse 6 is generated for a predetermined period L3. After a lapse of time, the detection pulse 7 that determines the detection range W3 is generated. Then, the cross point [A] at the trailing edge of B1 in the detection range W3, for example, with the level of 20 IRE is selected, the pixel number "35" is determined with that position as a reference, and various identification information of the identification control signal is decoded. Has been done. However, in the case of a signal with poor linearity, the 50% point of the trailing edge of B1 of the NZR signal may not be exactly 20 IRE, and the detection position may shift. FIG. 4 shows the state.
(B).

In FIG. 4B, when the amplitude of the NRZ signal becomes small, for example, when a signal having poor linearity is input, the detection position may shift due to the influence of the change in the amplitude. That is, in the figure (b), the detection result, which should be the position [A] in the figure (a), becomes [B] due to the deviation of the detection position, and the accurate horizontal synchronization position cannot be detected. As described above, there is a problem that not only the identification control signal cannot be accurately decoded due to the shift of the horizontal synchronization position, but also the display image is affected.

[0013]

SUMMARY OF THE INVENTION The present invention has been made in view of the above problems. The problem is that the horizontal synchronizing position is changed even when the video signal having poor linearity is input and the amplitude or the like fluctuates. There is provided a synchronous processing device and a processing method thereof capable of accurately detecting a signal and enabling normal decoding of an identification control signal.

[0014]

In order to solve such a problem, in a synchronous processing device and a processing method thereof according to the present invention, a first period from a predetermined time near a horizontal synchronous signal of a video signal in which an identification control signal is present is provided. First detection range setting means for setting an elapsed first detection range, and detection means for detecting a pedestal level of an identification control signal in the range,
Second detection range setting means for setting a second detection range in which a second period has elapsed from a predetermined time near the horizontal synchronization signal;
Detecting means for detecting the 100% level of the identification control signal within the range, calculating means for calculating the 50% reference level by calculating from the pedestal level and the 100% level, and further, desired horizontal synchronization by the 50% reference level. The problem has been solved by providing a detecting unit for detecting the position and synchronizing with the video signal by the horizontal synchronizing position.

As a concrete example of the synchronization processing apparatus and the processing method thereof according to the present invention, a first detection range is set in which a first period has elapsed from a predetermined time near a horizontal synchronization signal of a video signal having an identification control signal. A first detection range setting means, a detection means for detecting the 0IRE level of the identification control signal in the range, and a second detection range for which a second period has elapsed from a predetermined time near the horizontal synchronization signal. Detection range means, and 40 of the reference B1 of the identification control signal in that range.
A detection means for detecting the IRE level and a calculation means for calculating from the 0IRE level and the 40IRE level to calculate the 20IRE level and outputting the 50% reference level are provided. Third detection range setting means for setting the third detection range for which the period has elapsed, and the reference B1 of the identification control signal within the range.
And a detection means for detecting the falling 50% point.
Then, by using the 50% reference level output from the calculating means as a cross point of the falling 50% points of the reference B1, a desired horizontal synchronization position is detected, and the identification control signal is demodulated by the horizontal synchronization position. The above problem was solved by.

According to the synchronous processing apparatus and the processing method thereof of the present invention having such a configuration, the 20 IRE level obtained by calculating the horizontal synchronous position from the 0 IRE level and the 40 IRE level is crossed at the 50% point of the trailing edge of the reference bit B1. I chose it as a point. Therefore, even if the amplitude fluctuation occurs in the video signal, a stable horizontal synchronization position can be detected without being affected by the fluctuation. Therefore, the demodulation of the identification control signal can be stably performed depending on the horizontal synchronization position.

[0017]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of an EDTV-II synchronous processing apparatus and a processing method thereof according to the present invention will be described below with reference to FIGS. The same parts as those in the above-mentioned figure showing the synchronous processing device of EDTV-II and the processing method thereof are designated by the same reference numerals, and the description thereof will be partially omitted.

First, the structure of the synchronous processing apparatus of the present invention will be described with reference to FIG. FIG. 1 is a block diagram showing a main portion of an EDTV-II synchronization processing device of the present invention.

The essential structure of the synchronous processing device of the EDTV-II of the present invention in FIG. 1 is that an input terminal 11 to which a Video signal is input, an input terminal 12 to which a start pulse generated from Hsync and Hsync is input, and a predetermined period. The delay element (DL) 13 for generating L1, the waveform shaper 14 for generating the detection range W1, the 0IRE detection circuit 15 for detecting the 0IRE (0%) level of the NZR signal, and the delay element (DL) for similarly generating the predetermined period L2. ) 16, a waveform shaper 17 that generates a detection range W2, a 40IRE detection circuit 18 that detects a 40IRE (100%) level, and a 50% level detection circuit 1 that detects a 50% level from these by arithmetic processing or the like.
9. Further, a delay element (DL) 20 for generating a predetermined period L3 from Hsync, a waveform shaper 21 for generating a detection range W3, and a predetermined horizontal synchronization position pulse [A].
[A] detector 22, which serves as a replacement means for selecting, and an output terminal 23 and the like.

Next, the detailed structure of the identification control signal according to the present invention will be described with reference to FIG. FIG. 2 is a diagram showing a detection operation of an identification control signal, and FIG. 2 (a) is a timing diagram showing a synchronization predetermined device and its processing method of the present invention.
(B) is an enlarged view of the vicinity of the identification commands B1 and B2.

The identification control signals in FIG. 2A are the Hsync1, the color burst signal 2, and the NRZ signal 3 as described above.
Is roughly composed of. Identification commands B1 to B5 as shown in FIG. 7B are interpolated in the NRZ signal 3. The identification command B1 bit is 100% as shown in the enlarged view of FIG.
Level 40 IRE (Institute of Radio Engineer
20IR which is a 50% level and gradually falls from s)
Transition to identification command B2 bit with E as a boundary, and B2
Has a waveform that stabilizes at 0% level.

Next, the operation of the EDTV-II synchronization processing apparatus of the present invention will be described with reference to FIGS. In response to a start pulse originating from the falling edge of Hsync input to the input terminal 12 of FIG.
-The operation of the horizontal sync position detector of II starts. That is, a start pulse 6 is generated starting from the trailing edge of Hsync1 in FIG. 2A, a counter is loaded in response to the start pulse 6, and a delay element 13 delays for a predetermined period L1. At 14, the detection range is waveform-shaped. 0IRE detection circuit 1 of FIG.
In 5, the 0IRE (0%) level is detected from the input Video signal in the detection range W1.

Similarly, the delay element 16 delays the signal from the falling point of Hsync1 for a predetermined period L2, the waveform shaper 17 shapes the waveform into the detection range W2, and the 40IRE detection circuit 18 extracts 40IRE from the input Video signal in the detection range W2. (100%) level is detected. In the 50% level detection circuit 19, these 0IRE level and 40IR
A 50% level is calculated from the E level by arithmetic processing such as averaging processing and output to the [A] detector 22.

The delay element 20 delays the signal from the falling point of Hsync1 for a predetermined period L3, and the waveform shaper 21 shapes the waveform at the trailing edge 50% of the trailing edge of B1 in the detection range W3. Falling 5
The 0% point is detected and output to the [A] detector 22. [A]
In the detector 22, the input video is detected in the detection range W3.
The point where the signal crosses the 50% level calculated by the 50% detection circuit 19 is detected to obtain the desired horizontal synchronizing position pulse [A]. Then, a desired horizontal synchronization position pulse is superimposed on the input Video signal and output from the output terminal 23. Based on this horizontal synchronizing position pulse, it is used as a reference point for decoding the identification signal that follows.

As described above, according to the EDTV-II synchronous processing apparatus and the processing method thereof of the present invention, the 40 IRE level and the pedestal level (0 IRE) of the reference bit B1 of the EDTV-II are arithmetically processed to obtain 50%.
It was decided to detect the level. Therefore, even if the signal amplitude is distorted by a signal with poor linearity, the horizontal sync position can be detected stably. For example, 20IR
A signal that does not reach E can be detected, and each identification signal can be decoded at a stable timing.

By not detecting the pedestal level at B2 but between the color burst signal and B1, it becomes possible to detect the 50% level before the 50% point of the trailing edge of the trailing edge of B1. It is also possible to make the system capable of handling level fluctuations in the field cycle.

Furthermore, since the detected 50% level is the 50% level of the NRZ signal, it can also be used for decoding the NRZ signal. That is, it is possible to stably detect the information such as the letterbox B3 which is the most important information for specifying the display format of the screen on the 16: 9 receiver.

The present invention is not limited to the above embodiment,
Various embodiments can be adopted. For example, in the embodiment described above, an EDTV-
I explained about the II television receiver, but of course other A
It is also applicable to V devices such as video devices, video disks, recording medium integrated monitor devices, projector devices, and the like. In addition, it goes without saying that the present invention can be developed in various forms without being limited to the embodiment described above.

[0029]

As described above, according to the synchronous processing device and the synchronous processing method of the present invention, the level corresponding to the pedestal level (0IRE) and the level corresponding to the reference bit B1 (40IRE) included in the composite video signal are set. Then, the 50% level of the reference bit was detected from these, and the level was set to the 50% level of the horizontal synchronization position detection. As a result, the horizontal sync position can be stably detected even when a video signal having poor linearity is input, and can be detected even when the reference bit does not reach 40 IRE, for example.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a main part of a synchronization processing device of an EDTV-II according to the present invention.

FIG. 2 is a diagram showing a detection operation of an identification control signal in the synchronization processing device of the present invention, and FIG. 2 (a) is a timing diagram showing the synchronization predetermined device and the processing method thereof.
(B) is an enlarged view of the vicinity of the identification commands B1 and B2.

3A and 3B are diagrams showing an outline of an identification control signal of EDTV-II, FIG. 3A is a diagram showing an identification control signal waveform, and FIG. 3B is a diagram showing bit positions and identification contents.

FIG. 4 is a diagram showing a detection operation of an identification control signal of the EDTV-II, (a) is a timing chart showing a detection operation of a part of the identification control signal and a horizontal synchronization position, and (b) is an identification control. It is a timing diagram which shows the detection operation of the horizontal synchronizing position when the amplitude of a signal becomes small.

[Explanation of symbols]

 1 Horizontal sync signal Hsync 2 Color burst signal 3 NRZ signal 4 Color subcarrier (fsc) 5 Confirmation signal 6 Start pulse 7 Detection pulse 11, 12 Input terminal 13, 16, 20 Delay element (DL) 14, 17, 21 Waveform shaping 15 IRE detection circuit 18 40 IRE detection circuit 19 50% level detection circuit 22 [A] Detector 23 output terminal

Claims (4)

[Claims] 1. A first detection range is a predetermined range in which a first period has elapsed from a predetermined time near a horizontal synchronizing signal of a video signal in which the identification control signal is present, and the identification control in the first detection range. A pedestal level of a signal is detected, and a predetermined range in which a second period has elapsed from a predetermined time near the horizontal synchronization signal is set as a second detection range, and a 100% level of the identification control signal in the second detection range. Is detected, a 50% reference level is calculated by calculating from the pedestal level and the 100% level, a desired horizontal synchronization position is detected by the 50% reference level, and synchronization with the video signal is performed by the horizontal synchronization position. A synchronous processing method characterized by: 2. A predetermined range in which a first period has elapsed from a predetermined time near a horizontal synchronizing signal of a video signal having an identification control signal is defined as a first detection range, and the identification control is performed in the first detection range. A 0-IRE level of the signal is detected, and a predetermined range in which a second period has elapsed from a predetermined time near the horizontal synchronization signal is set as a second detection range, and the reference bit 1 of the identification control signal is set in the second detection range. Of 40
IRE level is detected and the 0IRE level and the 40
20IRE level is calculated by calculating from IRE level,
The reference level is set to 50%, and a predetermined range in which a third period has elapsed from a predetermined time near the horizontal synchronization signal is set as a third detection range, and the third detection range is set.
Reference bit 1 of the identification control signal in the detection range of
Of the reference bit 1 is detected as a cross point of the falling 50% points of the reference bit 1, and the desired horizontal synchronization position is detected, and the identification is performed based on the horizontal synchronization position. A synchronous processing method characterized by demodulating a control signal. 3. A first period after a first period has elapsed from a predetermined time near a horizontal synchronizing signal of a video signal including an identification control signal.
A first detection range setting means for setting a detection range, a detection means for detecting a pedestal level of the identification control signal in the first detection range, and a second period from a predetermined time near the horizontal synchronization signal. Second detection range setting means for setting the elapsed second detection range, and 1 of the identification control signal in the second detection range.
A detection means for detecting a 00% level, a calculation means for calculating a 50% reference level by calculating from the pedestal level and the 100%, and a detection means for detecting a desired horizontal synchronization position by the 50% reference level. The synchronization processing device is characterized in that the video signal is synchronized with the horizontal synchronization position. 4. A first period after a first period has elapsed from a predetermined time near a horizontal synchronizing signal of a video signal including an identification control signal.
A first detection range setting means for setting the detection range, a detection means for detecting the 0IRE level of the identification control signal in the first detection range, and a second period from a predetermined time near the horizontal synchronization signal. Second detection range means for setting the second detection range that has elapsed,
Detecting means for detecting the 40 IRE level of the reference bit 1 of the identification control signal in the second detection range, and calculating 20 IRE level by calculating from the 0 IRE level and the 40 IRE level and outputting a 50% reference level Means, third detection range setting means for setting a third detection range in which a third period has elapsed from a predetermined time near the horizontal synchronization signal, and the identification control signal of the identification control signal in the third detection range. Detecting means for detecting the trailing 50% point of the reference bit 1 and the 50% reference level output by the computing means as a cross point of the trailing 50% point of the reference bit 1 makes it possible to obtain a desired horizontal synchronization. A synchronization processing device which detects a position and demodulates the identification control signal according to the horizontal synchronization position.