JP3278006B2 - Data demodulator - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data demodulator for demodulating various data superimposed during a vertical blanking period of a video signal.

[0002]

2. Description of the Related Art Recently, for example, a character multiplexed signal, a caption signal,
2. Description of the Related Art Various data such as teletext signals are transmitted. As shown in FIG. 5, the format of these data is as follows: at a predetermined horizontal line position within the vertical blanking period of the video signal, after the color burst CB following the horizontal synchronizing signal Hs, first, the reference signal of the data sample clock. A CR (hereinafter referred to as a clock reference signal) and a data signal DT of a predetermined number of bits are superimposed thereon.

[0003] Table 1 shows some of the types and methods of data that are currently superimposed during the vertical blanking period.
Shown in In Table 1, the superimposed line indicates a line position (horizontal position) specified in the vertical blanking period. In addition, the data contents show only an example.

[0004]

[Table 1]

As shown in Table 1, there are various data types in the vertical blanking period of a video signal, and correspondingly, in a television receiver or a video device, the video signal is Therefore, a data demodulator capable of decoding these data is mounted. When a service of various data to be superimposed during the vertical blanking period of the video signal as described above is to be received, a plurality of dedicated decoders (data demodulators) for receiving the respective services are prepared. Therefore, the cost, the circuit scale, and the like increase. further,
Decoders must be changed for each destination, and it is impossible to use a common circuit board. Therefore, a device that decodes a plurality of data with one decoder has been considered.

FIG. 6 shows an example, and FIG. 7 shows signal waveforms shown as "-" in FIG. That is, in FIG. 6, the video signal input from the terminal 1 is supplied to the low-pass filter 2 and the sync separation circuit 3. The output of the low-pass filter 2 is
In the binarizing circuit 4, the signal is compared with a predetermined slice level SL shown in FIG. 7A and is supplied to the gate circuit 5 as a binarized signal as shown in FIG. 7B.

On the other hand, a horizontal synchronizing signal Hs and a vertical synchronizing signal Vs are taken out from the synchronizing separation circuit 3, and the horizontal synchronizing signal Hs and the vertical synchronizing signal Vs are supplied to a line counter 6. The line counter 6 is reset by the vertical synchronizing signal Vs, counts the line position by counting the horizontal synchronizing signal Hs, and the count value is supplied to the line decoder 7. The line decoder 7 is designed so that the DSP controller 29 can designate a line to output a line signal extraction pulse. That is, the DSP controller 2
The output operation of the line decoder 7 is controlled based on parameters supplied to the line decoder 7 from 9. The current line position counted by the line counter 6 is sent to the DSP controller 2 via the line decoder 7.
9 is input.

The horizontal synchronization signal Hs obtained by the synchronization separation circuit 3 is supplied to an in-line counter / decoder 8. The output timing of the reference signal extraction pulse and the data signal extraction pulse of the intra-line counter / decoder 8 is variably controlled based on the horizontal synchronization signal Hs according to the parameters supplied from the DSP controller 29. The reference signal extraction pulse and the data signal extraction pulse whose output timing is variably controlled according to the parameters supplied from the DSP controller 29 are supplied to the gate circuits 9 and 10, respectively.

A binarized signal is extracted from the gate circuit 5 by a line signal extraction pulse specified by the DSP controller 32 and supplied to the register 12 and the gate circuit 9. Then, since the reference signal extraction pulse is supplied to the gate circuit 9, the clock reference signal (FIG. 7 (f)) of the line designated by the DSP controller 29 is extracted from the gate circuit 9, and the PL is output.
It is supplied to the L circuit 11. Therefore, the oscillation frequency of the PLL circuit 11 is locked to the clock reference signal existing on the designated line, and the oscillation continues.

Since a data signal extraction pulse is supplied to the gate circuit 10, the gate circuit 10
The output of the PLL circuit 11 is taken out only during the pulse period and supplied to the register 12 as a data extraction clock (FIG. 7 (g)). The register 12 samples and stores the data signal DT supplied from the gate circuit 5 according to the data extraction clock,
The specified data signal will be captured.

As described above, in the configuration shown in FIG. 6, the supplied video signal has 16 lines, 19 lines, 20 lines, and 21 lines as shown in FIG. Assume that different data are superimposed. The case where the data of the 16th line is extracted and the case where the data of the 21st line is extracted will be described below. It is assumed that the data of the 16th line and the 21st line are both types of data shown in FIG. 5 to which the clock reference signal CR is added.
The operation of decoding data on the line will be described.

The DSP controller 29 sets "16" as a decode value in the line decoder 7, and FIG.
As shown by the solid line, a line signal extraction pulse designating 16 lines is output. In addition, the in-line counter / decoder 8 according to the data format of 16 lines.
To output a reference signal extraction pulse corresponding to the period Tc1 of the clock reference signal CR as shown by the solid line in FIG. 7D, and similarly, as shown by the solid line in FIG. A data signal extraction pulse corresponding to the TD period TD1 is output.

Further, the DSP controller 29 has a PLL
Data of the frequency division ratio for the programmable frequency divider is output so that the circuit 11 oscillates near the sample clock of 16 lines. For example, if the VPS data is superimposed on 16 lines as shown in Table 1, the oscillation frequency of the PLL circuit 11 is set to be around 5.0 MHz.

With this control, the gate circuit 5 extracts 16 lines of data, and the gate circuit 9 further extracts the 16 lines of the clock reference signal C.
R (signal ≒ indicated by a solid line in FIG. 7F) is extracted, and P
It is supplied to the LL circuit 11. Therefore, a clock synchronized with the clock reference signal CR is generated from the PLL circuit 11 and supplied to the register 12 via the gate circuit 10 as a data extraction clock indicated by a solid line in FIG.
That is, the register 12 stores 1 in the binary signal.
The data signal DT on the sixth line is sampled by the data extraction clock and stored. This data is supplied to, for example, the microcomputer 26 and is subjected to a predetermined processing operation.

Next, the operation of the conventional data demodulator shown in FIG. 6 when decoding data on the 21st line will be described.

The DSP controller 29 sets "21" as a decode value in the line decoder 7, and sets the decode value in FIG.
, A line signal extraction pulse designating 21 lines is output. In addition, the in-line counter / decoder 8 is controlled in accordance with the data format of the 21 line, and as shown by the dotted lines in FIGS. 7D and 7E, the reference signal extraction pulse and the data corresponding to the period Tc2 of the clock reference signal CR are output. A data signal extraction pulse corresponding to the period TD2 of the signal DT is output.

Further, the DSP controller 29 includes a PLL
The frequency division ratio data is output to the circuit 11 so as to oscillate near the sample clock of 21 lines. For example, if the closed caption data is superimposed on line 21 as shown in Table 1, P
The oscillation frequency of the LL circuit 11 is set to be around 503 KHz.

With this control, the gate circuit 5 extracts data of 21 lines, and the gate circuit 9 further extracts the clock reference signal C of the 21 line.
R (signal ≒ indicated by a chain line in FIG. 7F) is extracted, and P
It is supplied to the LL circuit 11. Therefore, a clock synchronized with the clock reference signal CR is generated from the PLL circuit 11 and supplied to the register 12 via the gate circuit 10 as a data extraction clock indicated by a chain line in FIG. As a result, the register 12 samples and stores the data signal DT of 21 lines in the binary signal. This data is supplied to, for example, the microcomputer 26 and processed as, for example, character information. The character information is supplied to the video signal processing unit 24 and superimposed on the video signal.

[0019]

As described above, according to the conventional data demodulator, the data to be read is selected by changing the clock frequency and the line position to be extracted according to the format of various data. Or multiple types of data can be captured at once.

However, as shown in FIG. 5, most of the various data signals superimposed on each line in the vertical blanking period have a run-in clock (Ru) at the beginning.
n-In-CLK), that is, the clock reference signal CR is inserted. According to the above-described conventional data demodulator, the PLL circuit 1 is based on the clock reference signal CR.
1 is locked in, a data extraction clock is generated from the PLL circuit 11, and the subsequent data signal DT is read into the register 12.

As shown in FIG. 8, the PLL circuit 11 includes a voltage controlled oscillator (VCO) 111 and the VCO 1
A programmable counter 112 that divides the output signal from the output signal 11 by a division ratio 1 / N, compares the phase of the output of the programmable counter 112 with a reference frequency (fH), and outputs a DC output based on the phase difference between the two. The generated phase difference detector (PD) 113 and this phase difference detector (P
D) The DC output from 113 is smoothed,
, A low-pass filter (LPF) 114 that supplies the output as a control signal.

The PLL circuit 11 changes the frequency division ratio of the programmable counter 112 inserted in the PLL loop according to a control signal supplied from the DSP controller 29, thereby generating a data extraction clock corresponding to each line. The output is generated at the output terminal Out. Therefore, as shown in FIG. 7, when reading data of a plurality of lines at the same time in the same field, the division ratio of the programmable counter 112 is changed for each line, and the division of the PLL loop in a short time is performed. As shown in FIG. 9, the PD 113
A pulsation X occurs in the output of. This is VCO1
As a result, the frequency of the oscillation output 11 pulsates, so that an accurate data extraction clock cannot be generated, thus causing an inconvenience of causing an error in data demodulation for each line.

FIG. 10 shows a conventional PLL circuit configuration in which a programmable counter is divided into a plurality of parts and taps of different frequencies are provided to demodulate a plurality of data formats. In this example, FIG.
The same reference numerals denote the same or corresponding parts, and a description thereof will be omitted. The example shown in FIG. 10 corresponds to the programmable counter 112 in the PLL circuit shown in FIG.
Is divided into a counter A115 and a counter B116 to form a PLL circuit. And VCO11
Switch 117 for selectively outputting an output signal for each line from the output terminal of the counter A115 or the output terminal of the counter A115.
The output of the changeover switch 117 is supplied to a second phase difference detector 118.

On the other hand, the second phase difference detector 118 includes a run-in clock (Run-In-CLK), that is, a run-in clock gate 9 whose gate is opened at the timing of arrival of the clock reference signal CR. A clock reference signal CR (that is, a clock reference signal 示 す shown in FIG. 7F) is supplied through the output terminal Out so that an output corresponding to the phase of the clock reference signal CR is obtained at the output terminal Out.
A reset signal is provided to O111 or the counter A115.

Also in this example, as shown in FIG. 7A, when reading data of a plurality of lines at the same time in the same field, a reset action is applied to the counter A115 for each line, and the PLL loop is disturbed. As a result. FIG. 11 shows this state, and the PD 11
3 produces a pulsation in the output of the VCO 111, which results in a pulsation in the frequency of the oscillation output of the VCO 111. As a result, it is not possible to generate an accurate data extraction clock, and thus an error occurs in data demodulation for each line. Occurs.

The present invention has been made by paying attention to such a point. In a data demodulator for demodulating data superimposed on a predetermined line position in a vertical blanking period of a video signal, the same field is used. It is an object of the present invention to provide a data demodulation device capable of generating an accurate data extraction clock corresponding to data superimposed on each line even when reading data of a plurality of lines at the same time. .

[0027]

According to a first aspect of the present invention, there is provided a data demodulation apparatus comprising: a voltage controlled oscillator for changing an oscillation frequency in accordance with a value of a control signal; Predetermined line position during vertical blanking period
Of the sample clock of the first data superimposed on the
To the voltage controlled oscillator clock frequency least common multiple of the frequency and the frequency of the sample clock of the second data
The voltage control is performed by a predetermined dividing ratio so as to oscillate.
A first programmable counter for dividing the output of the transmitter, an output of the first programmable counter and a video signal;
And a phase difference detector that receives an output of a reference signal of a reference frequency synchronized with the synchronization signal of the signal and outputs an output based on a phase difference between the two as a control signal to a voltage controlled oscillator. The output of the voltage controlled oscillator that constitutes it is input and adjusted for each horizontal line of the video signal.
Min a division ratio, the frequency division ratio for generating a clock necessary for demodulating the data for each line, is input that
A second programmable counter for dividing the output of the voltage-controlled oscillator, and using the output of the second programmable counter as a sample clock for data superimposed on a predetermined line position in the vertical blanking period. It is characterized in that it is made as described above.

[0028]

Furthermore, the data demodulating apparatus according to claim 2 further in the above-described structure, the second programmable counter of the clock reference contained in each data superimposed on a predetermined line position in a vertical blanking interval It is characterized in that it is reset by a signal and the phase of the output of the second programmable counter is made to match the phase of the clock reference signal.

[0030]

In the data demodulating device according to the first aspect,
A voltage controlled oscillator for changing the oscillation frequency in accordance with the value of the control signal, a predetermined La vertical blanking period of the video signal
The frequency of the sample clock of the first data and the frequency of the sample clock of the second data superimposed on the IN position
Oscillator clock with frequency of least common multiple with number
Oscillate by the voltage by the predetermined dividing ratio
The output of the controlled oscillator and the first programmable counter which divides output and movies of the first programmable counter
A PLL circuit configured by a phase difference detector for outputting an output based on the phase difference between the control signal for the voltage controlled Oscillator receives the output of the reference signal of the reference frequency synchronized with the synchronizing signal of the image signal, the output of the voltage controlled oscillator constituting the PLL circuit as an input, a frequency dividing ratio to be adjusted for each horizontal line of the video signal, the frequency division to generate the clock needed to demodulate the data for each line Depending on the ratio,
A second programmable counter for dividing the output of the voltage-controlled oscillator, and using the output of the second programmable counter as a sample clock for data superimposed on a predetermined line position in the vertical blanking period. I am trying to do it.

Therefore, the PLL circuit has, for example, P
It is not necessary to change the division ratio of the LL loop, the originating vibrations
The work can be made extremely stable. And V of PLL
Since the output of the second programmable counter having the CO output as an input is used as a data sample clock, a stable sample clock can be obtained.

[0032]

[0033] In data demodulation apparatus according to claim 2 further second programmable counter is reset by the clock reference signal contained in each data superimposed on a predetermined line position in a vertical blanking period, The phase of the output of the second programmable counter is
This is done to match the phase of the clock reference signal. Therefore, it is possible to accurately demodulate data for each line.

[0034]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 shows an overall configuration when the data demodulation device of the present invention is mounted on a television receiver. In FIG. 1, an RF signal received by an antenna 20 is tuned by a tuner 21 and extracted as an intermediate frequency signal. The composite video signal extracted as the intermediate frequency signal or the composite video signal input from the line input terminal 22 is supplied to the video signal processing circuit 24 via the input switching unit 23.

In the video signal processing circuit 24, Y / C separation,
Luminance signal processing, color difference signal processing, and the like are performed, demodulated into R, G, and B signals, supplied to the CRT 25, and output as video. The microcomputer 26 controls the operation of each unit of the television receiver.

The composite video signal from the input switching unit 23 is supplied to a data demodulation device 27. The data demodulation device 27 superimposes the supplied composite video signal on the vertical blanking period. The data signal is extracted, and, for example, character multiplexed information is superimposed on the video signal to output a video, and mode information or the like is supplied to the microcomputer 26 to be used for various controls. . The data demodulation device 27 is composed of, for example, a combination of a DSP (digital signal processor) 28 and a DSP controller 29. In some cases, the data demodulation device 27 is formed by a part of a software configuration of a microcomputer.

FIG. 2 shows that the data demodulator of the present invention
This shows the overall configuration when mounted on a CR. In addition,
In FIG. 2, the same reference numerals as those in FIG. 1 indicate the same or corresponding parts, and therefore, detailed description thereof will be omitted. In this VCR, the output of the video signal processing circuit 24 is supplied to a magnetic head 30 and recorded on a magnetic tape 31. Also, the head 30 is
Is supplied to the second video signal processing circuit 32, is reproduced as a composite video signal, and is supplied to the input switching unit 23 as a playback signal. In this VCR, a video output terminal 33 is derived from an input terminal of the video signal processing circuit 24.

In this VCR, similarly to the television receiver shown in FIG. 1, the data demodulating device 27 extracts a data signal superimposed in the vertical blanking period from the supplied composite video signal. In response to this, for example, character multiplexed information is superimposed on a video signal to output a video,
To be used for various controls. Similarly, the data demodulation device 27 is composed of, for example, a combination of a DSP (Digital Signal Processor) 28 and a DSP controller 29. In some cases, the data demodulation device 27 is formed by a part of a software configuration of a microcomputer.

As described above, the television receiver or the V
An embodiment of the data demodulation device of the present invention mounted on a video device such as a CR will be described with reference to the drawings. The overall configuration of the data demodulation device of the present invention can be represented, for example, substantially the same as that shown in FIG. Therefore, although the description of the overall configuration is omitted, the data demodulation device of the present invention is characterized by a PLL circuit portion indicated by reference numeral 11 in FIG.

That is, as shown in FIG. 3, the PLL circuit 11 includes a voltage controlled oscillator (VCO) 111 and this VC
A phase comparison is made between a programmable counter 112 that divides the output signal from O111 by a division ratio 1 / N and a reference frequency (fH) synchronized with the output of the programmable counter 112 and a horizontal synchronizing signal. Phase difference detector (PD) 11 for generating a DC output based on the phase difference
3 and a low-pass filter (LPF) 114 for smoothing the DC output from the phase difference detector (PD) 113 and supplying the output to the VCO 111 as a control signal.

The voltage controlled oscillator (VCO) 11
1. First programmable counter 112, phase difference detector (PD) 113, and low-pass filter (LPF)
The PLL loop consisting of 114 provides a sample clock for the data that the VCO 111 is going to receive service (Table 1).
The locked state is established in a state of oscillating at the frequency of the least common multiple of.

A second programmable counter 40 is connected to the output terminal of the VCO 111. The frequency-divided output of the second programmable counter 40 is supplied to one input terminal of a second phase difference detector (PD) 41. And the output terminal Ou as a sample clock of data superimposed on a predetermined line position in the vertical blanking period.
t. Further, the other input terminal of the PD 41 receives a clock reference signal CR via a run-in clock (Run-In-CLK), that is, a run-in clock gate 9 which opens at the arrival timing of the clock reference signal CR. (I.e., the clock reference signal 図 shown in FIG. 7 (f)) is supplied, and the output terminal Out outputs an output that matches the phase of the clock reference signal CR.
A reset signal is supplied to the second programmable counter 40 from 41.

FIG. 4 shows the reset operation.
FIG. 4A shows the oscillation output of the VCO 111, which is set to the frequency of the least common multiple of the sample clock (Table 1) of the data to be serviced, as described above. When the run-in clock shown in FIG. 4C, that is, the clock reference signal CR arrives at the PD 41 via the gate 9, the reset signal is output from the PD 41 at the zero crossing point Z of the clock reference signal CR to the second programmable terminal. It is supplied to the counter 40. As a result,
The frequency divided output by the second programmable counter 40 is
As shown in FIG. 4 (b), it is reset at point Z,
It is provided to the output terminal Out as a sample clock whose phase is synchronized with the clock reference signal CR.

The first programmable counter 112 and the second programmable counter 40 include:
Control data is supplied from the DSP controller 29, respectively. That is, the first programmable counter 11
For 2, the data demodulating device is controlled by the DSP controller 29 to set the frequency division ratio for causing the VCO 111 to oscillate the clock of the least common multiple required to demodulate the data in the required service range depending on the country or region used. Data is given. The DSP controller 29 supplies the second programmable counter 40 with data designating a different frequency division ratio for each line. Therefore, from the second programmable counter 40,
A stable sample clock for demodulating each data superimposed on a predetermined line position in the vertical blanking period of the video signal is sequentially generated.

As described above, the PLL circuit 11 shown in FIG.
, The first programmable counter 112 inserted in the loop does not perform the function of frequently changing the frequency division ratio for each line, so that the PLL circuit 11
VCO 111 oscillates stably in synchronization with the reference frequency (fH) synchronized with the horizontal synchronization signal. And DSP
In accordance with the control data from the controller 29, the frequency division ratio of the second programmable counter 40 is adjusted for each line, and each sample clock required for demodulating the data for each line is generated. In addition, at this time, the sample clock output from the second programmable counter 40 has a phase synchronized with the clock reference signal CR by the reset signal from the PD 41, so that data can be demodulated with high accuracy.

[0046]

As is apparent from the above description, claim 1
According to the demodulation device described in the above, the PLL locked to the reference signal
The input of the circuit and the output of the voltage controlled oscillator that constitutes the PLL circuit is input, and the dividing ratio is adjusted for each horizontal line of the video signal.
The input voltage control is based on the division ratio for generating the clock required to demodulate the data for each line.
A second programmable counter for dividing the output of the control oscillator is provided, and the output of the second programmable counter is used as a sample clock for data superimposed on a predetermined line position in the vertical blanking period. Therefore, the PLL circuit does not need to change the frequency division ratio of the PLL loop for each line, for example, and can make the oscillation operation extremely stable. Then, since the output is used as a data sample block by the programmable counter that receives the supply of the VCO output of the PLL circuit, a stable sample block can be obtained.

[0047]

[0048] According to the data demodulation apparatus according to claim 2, the second programmable counter, so as to reset on the basis of the clock reference signal contained in each data superimposed on a predetermined line position Therefore, the phase of the output of the programmable counter is ensured to match the phase of the clock reference signal. Therefore, an ideal output can be obtained as a sample clock for the data arriving for each line, and the data for each line can be accurately demodulated.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a television receiver equipped with a data demodulation device according to the present invention.

FIG. 2 shows a VC equipped with a data demodulator according to the present invention.
FIG. 3 is a block diagram showing a configuration of R.

FIG. 3 is a block diagram showing a configuration of a PLL circuit portion used in the data demodulation device of the present invention.

FIG. 4 is a timing chart for explaining the operation of the PLL circuit shown in FIG. 3;

FIG. 5 is a format diagram showing an example of a data signal superimposed on a predetermined line position in a vertical blanking period of a video signal.

FIG. 6 is a block diagram showing an example of the entire configuration of the present invention or a conventional data demodulation device.

FIG. 7 is a timing chart for explaining the operation of the data demodulation device shown in FIG. 6;

FIG. 8 is a block diagram showing a configuration of a PLL circuit used in a conventional data demodulation device.

9 is a signal waveform diagram for explaining an operation of the PLL circuit shown in FIG.

FIG. 10 shows another PL used in the conventional data demodulator.
FIG. 3 is a block diagram illustrating a configuration of an L circuit.

11 is a signal waveform diagram for explaining an operation of the PLL circuit shown in FIG.

[Explanation of symbols]

 Reference Signs List 9 gate circuit 11 PLL circuit 26 control microcomputer 27 data demodulation circuit 28 DSP 29 DSP controller 40 second programmable counter 41 second phase difference detector 111 voltage controlled oscillator 112 first programmable counter 113 first phase difference detector 114 low-pass filter

Claims (2)

(57) [Claims] 1. A data demodulator for demodulating data superimposed on a predetermined line position in a vertical blanking period of a video signal , comprising: a voltage controlled oscillator for changing an oscillation frequency in accordance with a value of a control signal; A predetermined vertical blanking period of the video signal;
And the frequency of the sample clock of the first data superimposed on the line position of
The voltage system the clock of the frequency of the least common multiple of the frequency
In order for the oscillator to oscillate,
A first programmable counter for dividing the output of the voltage-controlled oscillator, and receiving the output of the first programmable counter and the output of a reference signal having a reference frequency synchronized with the synchronization signal of the video signal, and detecting the phase difference between the two. And a phase difference detector that outputs an output based on the voltage-controlled oscillator as a control signal to the voltage-controlled oscillator. An output of the voltage-controlled oscillator included in the PLL circuit is input, and for each horizontal line of the video signal , Adjusted division ratio
Wherein the input is determined by a frequency division ratio for generating a clock required to demodulate line- by- line data.
And a second programmable counter for dividing the output of the voltage controlled oscillator, using the output of the second programmable counter, as the sample clock for data superimposed on a predetermined line position in the vertical blanking interval A data demodulation device characterized in that: 2. The second programmable counter comprises:
Reset is performed by a clock reference signal included in each data superimposed on a predetermined line position in the vertical blanking period, and the phase of the output of the second programmable counter is made to match the phase of the clock reference signal. The data demodulation device according to claim 1, wherein: