JPH09102744A - Information signal encoding device and method and information signal decoding method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To further reduce the quantity of data to be sent when the residual signals produced via the estimated encoding are encoded in variable length. SOLUTION: The residual signals which are produced when the input digital information signals undergo the estimated encoding are turned into blocks and quantized by an ADRC encoder 8 serving as a 1st variable length encoding means. The output of the encoder 8 is decomposed into bit planes by a bit plane encoding circuit 9. Then the number of block allocation bits of the encoder 8 is varied according to a dynamic range DR. The 0-bit allocation block is detected out of every bit plane and the data on this block are excluded. These exclude data are encoded and sent by a variable length encoder 13 serving as a 2nd variable length encoding means.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an information signal coding apparatus, a coding method, a decoding method and an information signal recording for reducing the amount of generated data of digital information signals such as digital audio signals and digital image signals. Regarding the medium.

[0002]

2. Description of the Related Art Predictive coding is known in order to reduce the amount of transmitted information such as digital audio signals and digital image signals. For example, the one-dimensional DPCM forms the difference (residual) between the input sample value and the predicted value in the temporal or spatial directions, and the two-dimensional DPCM forms the residual difference between the input sample value and the predicted value in the spatial direction. . Since the digital information signal has the correlation in the time direction and the spatial direction, the level of the residual signal becomes smaller than the input sample value. Therefore, the residual signal can be quantized with a smaller number of bits than the original number of quantized bits, whereby the amount of information can be compressed. In addition, the amount of information can be further compressed by performing variable length coding by utilizing the concentration of distribution of residual signals.

Run length and Huffman coding are known as variable length coding of this type. Furthermore, as one method of variable length coding of the residual signal, a method of combining bit plane coding and variable length coding has been proposed. The bit plane coding is a method of collecting bits of the same digit of a plurality of data to form a bit plane, and performing variable length coding such as run length coding and Huffman coding for each bit plane.

[0004]

One method of quantizing a residual signal is to change the number of quantization bits in accordance with the dynamic range of each block of the residual signal. That is, when the dynamic range of the block is small, the amount of information can be reduced by reducing the number of quantization bits. The smallest number of quantization bits is 0 bit. In case of 0 bit allocation,
No data of the residual signal is transmitted. However, in the conventional method of variable length coding each bit plane, since data of a block of 0 bit allocation is coded, even if variable length coding such as run length is applied, the compression rate is sufficiently high. There was a problem that could not be raised.

Therefore, an object of the present invention is to provide an information signal coding apparatus, a coding method, an information signal decoding method, and an information signal recording method capable of increasing the compression rate when variable length coding is performed for each bit plane. To provide the medium.

[0006]

According to a first aspect of the present invention, in an information signal coding apparatus for coding an input digital information signal so as to reduce the amount of generated data, the sample values of the input digital information signal are different from each other. Means for generating a residual signal, means for dividing the residual signal into blocks, and first variable-length coding means for quantizing the blocked residual signals with the number of quantization bits determined in block units. ,
The data of the block in which the output of the first variable length coding means is divided for each bit plane, and the bit assigned to the bit plane does not exist based on the information defining the number of quantization bits of the first variable length coding. And a second variable length coding means for respectively coding the removed bit planes by variable length coding, the information signal coding apparatus.

According to a fifth aspect of the present invention, in an information signal coding method for coding an input digital information signal so as to reduce the amount of generated data, a residual signal between sample values of the input digital information signal is generated. A step of dividing the residual signal into blocks, a first variable-length coding step of quantizing the blocked residual signals by the number of quantization bits determined in block units,
The variable length coded output of the
Based on the information that defines the number of quantized bits for variable-length coding of, the data of the block in which the bit assigned to the bit plane does not exist is removed, and the bitplanes after this removal are each subjected to variable-length coding. And a variable length coding step.

According to a sixth aspect of the present invention, an information signal code for forming at least first and second hierarchical data from an input digital information signal and encoding and transmitting the first and second hierarchical data. In the digitizing device, means for forming second hierarchical data having a resolution lower than that of the first hierarchical data, means for predicting the first hierarchical data from the second hierarchical data, the predicted data and the first hierarchical data Means for forming a residual signal with hierarchical data, means for blocking the residual signal, and first variable length for quantizing the blocked residual signal by the number of quantization bits determined in block units The output of the encoding means and the output of the first variable length encoding means is divided for each bit plane, and the bit planes are assigned to the bit planes based on the information defining the number of quantization bits for the first variable length encoding. Removing the data blocks bets is not present, the information signal encoding apparatus characterized by comprising a second variable length encoding means for each variable length coded bit-plane after the removal.

According to a seventh aspect of the present invention, an information signal code for forming at least first and second hierarchical data from an input digital information signal and encoding and transmitting the first and second hierarchical data. In the method, the step of forming second hierarchical data having a lower resolution than the first hierarchical data, the step of predicting the first hierarchical data from the second hierarchical data, the predicted data and the first hierarchical data A step of forming a residual signal with hierarchical data, a step of blocking the residual signal, and a first variable length for quantizing the blocked residual signal by the number of quantization bits determined in block units The encoding step and dividing the first variable length encoded output into bit planes,
Based on the information that defines the number of quantized bits for variable-length coding of, the data of the block in which the bit assigned to the bit plane does not exist is removed, and the bitplanes after this removal are each subjected to variable-length coding. An information signal encoding method is characterized by comprising a variable length encoding step.

In the invention described in claim 8, the residual signal is first
In the information signal decoding method of decoding the coded residual signal quantized by the variable length coding of the coded residual signal and coded by the second variable length coding for each bit plane of the coded residual signal, A second step of restoring the data of the removed block in each of the bit planes, decoding the variable length coding, and synthesizing the decoded bit planes based on the information defining the number of quantized bits of the long coding Variable-length coding decoding step, first variable-length coding decoding step of performing variable-length coding decoding on the combined bit plane data, and block decomposition of the decoded residual signal Then, the information signal decoding method is characterized by comprising the steps of:

The residual signal between the digital image signal as the input digital information signal and the prediction signal is divided into blocks and encoded by variable length encoding in which the number of allocated bits is different for each block. For example, the encoded output for one screen is converted into a set of bit planes. In the case of a block of 0 bit allocation in the set of bit planes,
The bit of all planes corresponding to this block is always '0'
Becomes Therefore, by removing the 0 bit based on the information of this 0 bit allocation before performing the variable length coding, it is possible to reduce the data that needs to be variable length coded and transmitted. Further, even in the case of allocating 1 bit other than 0 bit, depending on the allocated bit number, data of a block having no bit is generated. Even in such a case, the data of that block is removed.

[0012]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. In this one embodiment, the video signal is sampled at a predetermined sampling frequency,
The present invention is applied to a digital image signal in which each sample is converted into a predetermined number of quantization bits. FIG.
Shows the overall system configuration of an embodiment of the present invention.

In FIG. 1, a digital video signal is supplied to an input terminal 121. Input signal is subtractor 1
23, the output (residual signal) of the subtractor 123 is supplied to the blocking circuit 124 and the predictor 122, and the prediction signal generated by the predictor 122 is supplied to the subtractor 123. The subtractor 123 subtracts the prediction signal from the input signal to generate a prediction residual. This residual signal is supplied to the blocking circuit 124, and converted from raster scan order data to block order data. The blocked residual signal is supplied to the encoding unit 125.

As will be described later, the encoding unit 125 performs the first variable-length encoding process for requantizing the residual signal with a quantization bit number smaller than the original quantization bit number, and the quantized data. A second variable-length coding process is performed in which the data in each bit-plane is divided into variable-length codes. Further, at the time of requantization, data correction is performed so that the value of 0 of the residual signal is restored to 0.

The encoded output of the encoding unit 125 is supplied to the error correction code encoder 126, and the redundant code of the error correction code is added. The output of the error correction code encoder 126 is supplied to the modulator 127. Modulator 1
Reference numeral 27 modulates the digital signal into a form suitable for recording, transmission and the like. The output signal from the modulator 127 is supplied to the recording unit 128, and the recording unit 128 records the recording signal on the information signal recording medium 129. It is also possible to transmit data via the transmission path 130, in which case a transmission unit is used instead of the recording unit 128. The information signal recording medium 129 is a disk-shaped or tape-shaped recording medium that uses magnetism, magneto-optical property, phase change, or the like. A semiconductor memory is also a kind of recording medium.

The reproduction unit 131 reproduces the data from the recording medium 129, or the data transmitted through the transmission path 130 is received. The data reproduced by the reproduction unit 131 is demodulated by the demodulation unit 132, and the demodulated output is supplied to the error correction code decoder 133. The decoder 133 corrects the error by using the redundant code, and also corrects the error that cannot be corrected and remains.

The output of the error correction decoder 133 is supplied to the decoding unit 134. As will be described later, the decoding unit 134 performs the variable length coding decoding and the inverse quantization processing, which is the reverse of the coding unit 125. A decoded residual signal is generated from the decoding unit 134. This decoded residual signal is supplied to the block decomposition circuit 135.
In the block decomposition circuit 135, the block structure is returned to the raster scanning order.

The decoded residual signal is supplied to the adder circuit 136. A decoded image signal is formed by the adder circuit 136 and is output to the output terminal 137. The decoded image signal is also supplied to the predictor 138 to generate a predicted signal. The prediction signal is supplied to the adder circuit 136.

FIG. 2 shows an example of the encoding unit 125. The blocked residual signal from the blocking circuit 124 is supplied to the input terminal 1. FIG. 3 schematically shows the formation of the residual signal. One rectangular area in FIG. 3 corresponds to one pixel. Each of a to h indicates a locally decoded pixel value, and each of A to P indicates a pixel value before being encoded. Predicted value A'for pixel value A
Are generated by the predictor 122 using locally decoded pixel values in the vicinity. For example, the predicted value A'is A '= 4c-3
(B−f), A ′ = f + c−b, and the like. Prediction values for the pixel values B, C, ... Are calculated by the same prediction formula. Expressed by a general formula, the predicted value is generated by (αa + βb + γf, where α, β, and γ are constants).

The subtractor 123 subtracts the predicted value (eg A ') from the pixel value (eg A) to generate the residual signal Δa. Similarly, residual signals Δb, Δc, ... Are generated. The blocking circuit 124 converts the generated residual signal into a block structure. For example, by the blocking circuit 124, (4
Data of the blocks of the residual signals Δa to Δp corresponding to the block of (4) are formed. When handling a digital audio signal, a prediction value in the time direction is formed,
A block of one-dimensional residual signals is formed.

It is possible to increase the degree of concentration by blocking the level range of the residual signal. In the case where one pixel is 8-bit data, the distribution of the frequency of occurrence of the residual signal in the entire one screen is centered at 0 (-255 to -255).
+255), and the frequency with a residual of 0 is the maximum. However, when divided into blocks,
The residual level distribution is more concentrated than the original distribution. Further, when divided into blocks, the maximum frequency of the residual does not always match 0.

This is because the residual in the block of the small space has a large value in probability as compared with one screen, and
This is also due to the strong residual correlation within the block. Also, the fact that the frequency of the value of 0 does not become maximum occurs when the luminance level in the block gradually changes in the diagonal direction, for example. Note that blocking is an example of a method of increasing the degree of concentration of the residual level distribution, and other methods are also possible.

Returning to FIG. 2, the encoding unit 125 will be described. The residual signal from the input terminal 1 is supplied to the maximum value detection circuit 2, the minimum value detection circuit 3, the offset detection circuit 4, and the delay circuit 5. The maximum value detection circuit 2 detects the maximum value MAX for each block, and the minimum value detection circuit 3 detects the minimum value MIN for each block. The detected maximum value MAX and minimum value MIN are supplied to the offset detection circuit 4 and DR, MIN ′ calculation circuit 7.

The offset detection circuit 4 is supplied with a blocked residual signal, a maximum value MAX and a minimum value MIN, and when the block includes a residual signal of 0, it corresponds to the maximum value MAX and the minimum value MIN. A value for correcting the data, that is, an offset off is calculated so that the quantization restoration value closest to 0 becomes 0 out of the plurality of quantization restoration values. The offset detection circuit 4 will be described later. The calculated offset off is output from the offset detection circuit 4 to D.
It is supplied to the R and MIN ′ calculation circuit 7.

In the DR / MIN 'calculation circuit 7, the maximum value M
Dynamic range DR from AX and minimum value MIN
(= MAX-MIN) is calculated. In addition, (MIN-
off = MIN ') modified minimum value MIN'
Is required. Then, from the DR / MIN ′ calculation circuit 7, the calculated dynamic range DR and minimum value MI
N ′ is supplied to an ADRC (Adaptive Dynamic Range Coding) encoder 8. The ADRC encoder 8 has
The residual signal from the input terminal 1 is supplied through the delay circuit 5 for phase matching.

Here, the offset process applied to the maximum value MAX, the minimum value MIN and the dynamic range DR will be schematically described with reference to FIG. As described above, the residual signal generated by the predictive coding has various biases depending on the block, as shown in FIG. 4A. In FIG. 4A, the residual signal indicated by a is biased to the negative side, the residual signal indicated by b is the one whose maximum frequency is 0, and the residual signal indicated by c is the positive side. Is biased toward. FIG. 4B shows the frequency distribution of the residual signal of a block. In the case of quantizing the residual signal, for example, M
The area between AX and MIN is divided into five parts, and the same code is assigned to the residual signals belonging to that range. The code, when restored, is the central value of the range (indicated by the arrow)
Is converted to Generally, when the number of bits of the code is n, MAX and MIN are divided into 2 ⁿ number ranges.

As can be seen from FIG. 4B, in general, there is a deviation between the actual zero value of the residual signal and the zero value of the quantization reconstruction value. Restoring the 0 value of the residual signal to 0 is important for restoring the original signal. If the residual signal is 0
If the value of is not restored to 0, the error is accumulated, which causes a large deterioration in image quality. Preferably, in order to prevent the accumulation of prediction errors, the original refresh data is periodically transmitted.

In this embodiment, the quantization restoration value is the most zero.
The difference between the value close to and the actual value of 0 is calculated, and the value is set as the offset off, and the minimum value MIN and the maximum value MAX
Is added to. Thereby, as shown in FIG. 4C, the minimum value MIN and the maximum value MAX are converted into values MIN 'and MAX' shifted by the offset off. As a result, 0 of the residual signal can be represented by 0 even in the quantization reconstructed value. At this time, the dynamic range D
R is (MAX'-MIN '= (MAX-off)-(M
IN-off) = MAX-MIN), which does not change even if an offset is added.

An example of the offset detection circuit 4 is shown in FIG. The maximum value MAX and the minimum value MIN of the block are supplied to the subtractor 21, and the dynamic range DR of the block is calculated by subtracting MAX-MIN.
The dynamic range DR is supplied to the bit number determination circuit 22, the code detection circuit 23, and the arithmetic circuit 24. The number-of-bits determination circuit 22 determines the number of quantization bits n of the block.
Is determined based on the dynamic range DR.

The bit number determination circuit 22 uses an ADR described later.
Similar to the C encoder 8, the number of quantization bits n to be assigned to each block is detected according to the dynamic range DR. That is, the dynamic range DR and the minimum value M
Variable length quantization or semi-fixed length quantization in which the number of quantization bits n is set according to IN 'is performed. As an example, the semi-fixed length quantization when the dynamic range DR is 0 to 255 will be described. Dynamic range DR and (0 <T
_The threshold values T ₁ and T ₂ having the relationship of ₁ <T ₂ <255 determine the number n of quantization bits assigned to a block as described below.

0 ≤ DR ≤ T ₁ ... n = 0 (bit) T ₁ <DR ≤ T ₂ ... n = 1 (bit) T ₂ <DR ≤ 255 ... n = 2 (bit)

When setting the thresholds T ₁ and T ₂ ,
The larger the dynamic range DR, the larger the maximum quantization distortion. This is because in human visual characteristics, the recognizable quantization distortion changes depending on the size of the dynamic range DR.
Further, it is possible to make the maximum quantization distortion uniform in each bit allocation.

Code detection circuit 2 of offset detection circuit 4
3 is the determined number of bits n and the dynamic range DR
And the minimum value MIN, the code co
generate de. DR = MAX-MIN Quantization step Δ = DR / ²ⁿ code = [-MIN × ( ²ⁿ / DR] = [-MIN / Δ] [] means to convert the value in parentheses into an integer.

From the determined number of bits n, the dynamic range DR, the minimum value MIN and the code, the arithmetic circuit 24 calculates
An offset off is generated based on the following formula. off = MIN + code × DR / 2 ⁿ + DR / 2 ^{n + 1} = MIN + code × Δ + Δ / 2

The minimum value MIN 'corrected by the dynamic range DR and the offset is ADR shown in FIG.
The residual signal supplied to the C encoder 8 and passed through the delay circuit 5 is semi-fixed length quantized. FIG. 6 shows an example of the ADRC encoder 8. The bit number determination circuit 26, like the bit number determination circuit 22 in the offset detection circuit 4,
The number n of quantization bits assigned to the block is determined from the relationship between the dynamic range DR and the threshold values T ₁ and T ₂ . The number of bits n and the dynamic range DR are supplied to the arithmetic circuit 27, and the arithmetic circuit 27 calculates the quantization step Δ (= DR / 2 ⁿ ).

The residual signal and MIN 'are supplied to the subtraction circuit 28, and the residual signal is normalized by MIN'. The normalized residual signal from the subtraction circuit 28 is the quantizer 29.
Supplied to The quantizer 29 is supplied with the quantization step Δ, and the coded q is generated by dividing the normalized residual signal by the quantization step Δ and converting it into an integer. The ADRC encoder 8 outputs the dynamic range DR of each block, the minimum value MIN ′, and the code q corresponding to each pixel.

Although the residual signal is normalized by subtracting the minimum value MIN 'here, the normalization is performed so as to generate the difference of the residual signal with respect to the maximum value MAX'. Is also good. Furthermore, when transmitting the dynamic range information, the minimum value MIN ′ and the maximum value MAX ′ may be transmitted instead of transmitting the dynamic range DR.

Returning to FIG. 2, the output (q, DR, MIN ') of the ADRC encoder 8 is supplied to the bit plane encoding circuit 9. The bit plane encoding circuit 9 divides the n-bit code q into bit planes. For example, when the number of bits n can be 0, 1, 2 (bits), the code q is divided into an MSB (most significant bit) plane and an LSB (least significant bit) plane. The MSB plane is a set of supplied 2-bit quantized MSBs, and the LSB plane is a set of LSBs. In FIG. 7A, for simplification, one screen has (4 × 3 = 1
2 blocks), and each block includes a code q of a (4 × 4) residual signal. As described above, the blocks (not shown) include the code q having the bit number n determined by the dynamic range DR of the block and the threshold values T ₁ and T ₂ .

In FIG. 7A, the values 0, 1, 2 and 3 of the code q shown as an example are 2 bits each ((0
It means 0), (01), (10) and (11). FIG.
In the example of A, the bit plane encoding circuit 9 divides the code q of one screen into an MSB plane and an LSB plane, as shown in FIG. 7B.

The LSB plane and the MSB plane generated by the bit plane encoding circuit 9 are supplied to the dynamic range determining circuits 11a and 11b, respectively. In the dynamic range determination circuits 11a and 11b, the dynamic range DR is compared with the threshold values T ₁ and T ₂ as described above, and the number of bits of the code q of the block is checked. The bit planes and the outputs of the dynamic range determination circuits 11a and 11b are supplied to the memories 12a and 12b, respectively. When the maximum value of the number of bits n is 3, the plane of the third bit other than the MSB and the LSB is formed, so that it is necessary to add the dynamic range determination circuit 11c and the memory 12c as shown by the broken line in FIG. There is.

Quantization bit number n is 0, 1, 2 (bit)
When they exist, as illustrated in FIG. 8A, blocks of these bit numbers are mixed in one screen. In the example of FIG. 8, the number of blocks in one screen is different from that of FIG. 7, and (9 × 6)
It is assumed that blocks are included in one screen. The residual signal shown in FIG. 8A is divided into an MSB plane and an LSB plane as shown in FIG. 8B. In FIG. 8B, a blank block has all the bits of the block.
Indicates that it is `0 '. In the case of a block of 0 bit allocation, both the LSB plane and the MSB plane are
All bits in that block are '0'. In the block of 1-bit allocation, the bit corresponding to the block of the LSB plane is "0" or "1", and all the bits corresponding to the block of the MSB plane are "0". The block of 2-bit allocation does not always become “0” in both the LSB plane and the MSB plane.

In the embodiment of the present invention, as described above, blocks in which all bits are always "0" are excluded from the targets of variable length coding. In other words, the transmission data amount is further reduced by excluding it from the transmission target. Therefore, the dynamic range determination circuit 1
1a, 11b and memories 12a, 12b are provided. That is, the dynamic range determination circuit 11a determines the bit number n of the block by the dynamic range DR as described above. Then, the LSB plane of the block determined to have 0 bit allocation is not written to the memory 12a. Similarly, regarding the MSB plane, the data of the block determined to have 0 bit allocation is not written in the memory 12b.

As a result of the above exclusion process, the memory 12
As shown in FIG. 8C, the blocks that are always '0' are excluded in a and 12b, so that the code q is stored in the form of being padded on the left side in the drawing. Then, the memories 12a, 1
From 2b, for example, the blocks arranged on the uppermost side are sequentially read from the left side. The last valid block can be known from the determination results of the dynamic range determination circuits 11a and 11b. Next, the data of the block aligned second from the top is read. Then, the reading of the data of each bit plane is completed by reading the data of the last valid block arranged in the lowermost side. When viewed on the time axis, valid data is packed on the front side in time.

The data read from the memories 12a and 12b is supplied to the variable length coding circuit 13. In the variable length coding circuit 13, run length coding, for example, MMR (Modefied MR), is performed for each bit plane. The output of the variable length coding circuit 13 is supplied to the framing circuit 10. The framing circuit 10 includes additional data (DR, MI) for each block generated by ADRC encoding.
N ') is also supplied. To the output terminal 14 of the framing circuit 10, the additional data and the variable-length code are output as data of a predetermined frame structure.

An encoding method other than ADRC may be used. In that case, since it is always "0", it is necessary to simultaneously transmit the ID indicating that there is a removed block. In the case of ADRC encoding, the ID is not required by using the dynamic range DR on the decoding side.

Referring to FIG. 9, the decoding unit 1 of FIG.
An example of 34 will be described. Error correction decoder 13
Reproduction from 3 or received data is decoding unit 1
It is supplied to the input terminal 31 of 34. Frame disassembly circuit 3
2, the code of the variable-length encoded residual signal,
The dynamic range DR and the minimum value MIN 'are separated. The code of the separated residual signal is decoded by the variable length decoding circuit 33. The variable length decoding circuit 33 corresponds to the variable length coding circuit 13.

The decoded output of the variable length decoding circuit 33 is supplied to one input terminal of each of the switching circuits 34a and 34b. Data of "0" is supplied to the other input terminal of each of the switching circuits 34a and 34b. Output data of the switching circuits 34a and 34b are written in the LSB memory 36a and the MSB memory 36b, respectively. The switching circuits 34a and 34b are controlled by the select signal from the select signal generator 35.

The select signal is generated based on the dynamic range DR separated by the frame decomposition circuit 32. That is, as described above, it is known from the dynamic range DR that the number of bits n allocated to the block is known, and that the block having the number of bits n of 0 bit is excluded in the encoding unit 125. The switching circuit 34a adds the "0" data of the block removed in the LSB plane, and the switching circuit 34b adds the "0" data of the block removed in the MSB plane. Therefore, the memory 36
Planes including the added `0` data are written in a and 36b, respectively.

Select signals are supplied to the memories 36a and 36b, respectively, and when the memories 36a and 36b are read, the reading is controlled so that the "0" data is inserted into the position of the block removed at the time of encoding. It The LSB plane from the LSB memory 36a and the MSB memory 36
The MSB plane from b is the bit plane decoding circuit 3
7 is supplied. The bit plane decoding circuit 37 combines the two planes and outputs an ADRC-coded residual signal.

The output of the bit plane decoding circuit 37 is A
It is supplied to the DRC decoder 38. ADRC decoder 3
A dynamic range DR and a minimum value MIN ′ are supplied from 8 to the frame decomposition circuit 32. Although not shown, the ADRC decoder 38 performs a process reverse to the process of the ADRC encoder 8 (see FIG. 6). That is, the bit number n of the block is determined from the dynamic range DR, the quantization step Δ is formed, the quantization step Δ is multiplied by the code signal q, and the minimum value MIN ′ is added to the multiplication result. The decoded residual signal that has been blocked is output to the output terminal 39. In this way, the value of the decoded residual signal is a value of 0 corresponding to the data of a value of 0. The decoded residual signal extracted at the output terminal 39 is supplied to the block decomposition circuit 135 (see FIG. 1).

Next, another embodiment in which the present invention is applied to hierarchical coding will be described. The hierarchical coding apparatus described here can prevent an increase in the number of pixels to be coded by performing prediction between layers and using a simple arithmetic expression for inter-layer data.

This hierarchical coding method will be described with reference to FIG. As an example, FIG. 10 shows a schematic view between four layers, where the first layer is the lowest layer (original image) and the fourth layer is the highest layer. For example, when the average value of spatially corresponding lower layer data of four pixels is adopted as the upper layer data generation method, the number of transmission pixels can be prevented from increasing.

That is, assuming that the upper layer data is M and the lower layer pixel values are x ₀ , x ₁ , x ₂ , x ₃ , M = 1/4 · (x ₀ + x ₁ + x ₂ + x ₃ ) It is formed. And data M and 4
Of the data, three data other than x ₃ , for example, are transmitted. On the receiving or reproducing side, the non-transmitted pixel x ₃ can be easily restored by a simple arithmetic expression: x ₃ = 4 · M− (x ₀ + x ₁ + x ₂ ). In FIG. 10, hatched rectangles indicate non-transmission pixels.

FIG. 11 shows a structure of, for example, five layers of hierarchical coding using the above-described averaging. It is assumed that the first layer is the resolution level of the input image. The block size of the first layer is (1 × 1). The second layer data is generated by averaging four pixels of the first layer data. In this example, the second layer data X ₂ (0) is generated by the average value of the first layer data X ₁ (0) to X ₁ (3). X ₂
Second layer data X ₂ (1) to X ₂ adjacent to (0)
Similarly, (3) is generated by averaging four pixels of the first layer data. The block size of the second layer is (1/2 ×
1/2).

Further, the third hierarchical data is generated by averaging four pixels of the spatially corresponding second hierarchical data. The block size of the third layer is (1/4 × 1/4). Similarly, the data of the fourth layer is also generated from the data of the third layer. The block size of this fourth layer is
(1/8 × 1/8). Finally, the fifth layer data X ₅ (0), which is the highest layer, is the fourth layer data X ₄ (0).
Is generated by the average value of X ₄ (3). The block size of the fifth layer is (1/16 × 1/16).

By applying the class classification adaptive prediction to the upper layer data with respect to the hierarchical structure data in which the increase in the number of encoding target pixels is prevented, the lower layer data is predicted,
It is possible to reduce the amount of transmission data by generating the difference between the lower layer data and its predicted value (that is, the residual signal). FIG. 12 shows such an encoding unit. The first layer data d0 is supplied to the averaging circuit 42 and the subtractor 46 as the input image data d0 via the input terminal 41. The first layer data is the image data of the original resolution.

The averaging circuit 42 performs 1/4 averaging processing on the input pixel data d0 to generate hierarchical data d1. This hierarchical data d1 is the second data shown in FIG.
Corresponds to hierarchical data. The generated hierarchical data d1 is
It is supplied to the averaging circuit 43 and the subtractor 47.

The averaging circuit 43 is applied to the hierarchical data d1.
Then, processing similar to that of the averaging circuit 42 is performed to generate hierarchical data d2. This hierarchical data d2 corresponds to the third hierarchical data. The generated hierarchical data d2 is supplied to the averaging circuit 44 and the subtractor 48. Similarly, the averaging circuit 44 also performs a quarter averaging process on the hierarchical data d2 to generate hierarchical data d3. This hierarchical data d3 corresponds to the fourth hierarchical data. The generated hierarchical data d3 is used in the averaging circuit 45 and the subtractor 49.
Supplied to Further, the averaging circuit 45 similarly similarly performs the quarter averaging process on the hierarchical data d3 to generate hierarchical data d4. This hierarchical data d4 corresponds to the fifth hierarchical data. The generated hierarchical data d4 is supplied to the quantizer 54.

Then, prediction is performed between layers for these five hierarchical data. First, the quantization process for compression performed in the fifth layer is performed by the quantizer 54. The output data d21 of the quantizer 54 is supplied to the variable-length code encoder 71 and also to the inverse quantizer 58. The output of the encoder 71 is taken out to the output terminal 76 as data of the fifth layer. Output data d of the inverse quantizer 58 to which the encoded data d21 is supplied
16 is supplied to the class classification adaptive prediction circuit 62.

In the class classification adaptive prediction circuit 62, a prediction process is performed using the data d16 to generate a prediction value d12 of the fourth hierarchical data, and this prediction value d12 is used as the subtractor 4
9. In the subtractor 49, the averaging circuit 44
The difference value between the hierarchical data d3 supplied from the above and the predicted value d12 is obtained, and the difference value d8 is supplied to the quantizer 53.

In the quantizer 53, to which the difference value d8 is supplied, requantization is performed so as to reduce the number of quantization bits as in the quantizer 54. The output data of the quantizer 53 is supplied to the calculator 66 and the inverse quantizer 57.
The arithmetic unit 66 performs a process of thinning out one pixel from four pixels. The data d20 output from the arithmetic unit 66 is encoded by the encoder 70 of the variable length code, and the encoder 7
The output of 0 is taken out to the output terminal 75 as the output data of the fourth layer.

The fourth layer data d12 predicted by the class classification adaptive prediction circuit 62 and the output data (decoded residual signal) d15 of the inverse quantizer 57 are supplied to the class classification adaptive prediction circuit 61. In the class classification adaptive prediction circuit 61,
By adding the data d15 to the data d12, local decoded data of the fourth layer is formed, the prediction process is performed using this local decoded data, and the predicted value d11 of the third layer data is generated. Predicted value d11
Are supplied to the subtractor 48. The subtractor 48 obtains the difference value between the data d2 supplied from the averaging circuit 43 and the predicted value d11, and the difference value d7 is supplied to the quantizer 52.

The output data of the quantizer 52, to which the difference value d7 is supplied, is supplied to the calculator 65 and the inverse quantizer 56. The computing unit 65 performs a process of thinning out one pixel from four pixels. The third layer data d19 output from the calculator 65 is supplied to the encoder 69 of the variable length code, and the output of the encoder 69 is taken out to the output terminal 74 as the third layer data.

The third layer data d11 predicted by the class classification adaptive prediction circuit 61 and the output data d14 of the dequantizer 56 to which the coded data is supplied from the quantizer 52.
Are supplied to the class classification adaptive prediction circuit 60. In the class classification adaptive prediction circuit 60, the data d14 is added to the data d11 to form the third-layer local decoded data, and the prediction process is performed using this local decoded data to obtain the second-layer data. The predicted value d10 is generated, and the predicted value d10 is supplied to the subtractor 47. In the subtractor 47, a difference value between the data d1 supplied from the averaging circuit 42 and the predicted value d10 is obtained, and the difference value d6 is supplied to the quantizer 51.

The output data of the quantizer 51 is the arithmetic unit 64.
And to the inverse quantizer 55. In this computing unit 64, a process of thinning out one pixel from four pixels is performed. The second layer data d18 output from the arithmetic unit 64 is supplied to the variable-length code encoder 68, and the output of the encoder 68 is taken out to the output terminal 73 as the second layer data.

The second layer data d10 predicted by the class classification adaptive prediction circuit 60 and the output data d13 of the dequantizer 55 to which the coded data is supplied from the quantizer 51.
Are supplied to the class classification adaptive prediction circuit 59. The class classification adaptive prediction circuit 59 forms the second layer of local decoded data by adding the data d13 to the data d10, and the local decoded data is used to perform the prediction process to generate the first layer data. The predicted value d9 is generated, and the predicted value d9 is supplied to the subtractor 46. The subtractor 46 obtains a difference value between the input pixel data d0 supplied from the input terminal 41 and the predicted value d9, and the difference value d5 is supplied to the quantizer 50.

The output data of the quantizer 50 to which the difference value d5 is supplied is supplied to the calculator 63. This calculator 63
In, the process of thinning out one pixel from four pixels is performed. The first layer data d17 output from the computing unit 63 is supplied to the encoder 67 of the variable length code, and the output of the encoder 67 is taken out to the output terminal 72 as the first layer data.

Class classification adaptive prediction circuits 59, 60, 6
Each of 1 and 62 is for predicting a pixel of a lower hierarchy to be predicted based on the level distribution of a plurality of pixels spatially nearby (included in the upper hierarchy). FIG.
4 shows an example of the configuration of the class classification adaptation processing unit. The input signal from the input terminal 141 is supplied to the peripheral code forming unit 142. The peripheral code forming unit 142 uses a plurality of data x ₁ , x ₂ , ... Which are located in the vicinity of the pixel to be predicted.
..., x _n are synchronized. The peripheral code value is supplied to the class classification unit 143 and the delay unit 145. Classification section 143 outputs a class code corresponding to the pattern of the level distribution around code values x ₁ ~x _n. The peripheral code value itself may be used as the class code, but since the number of classes is enormous, the bit number of each of the peripheral codes is compressed to, for example, 1 bit by ADRC or the like. The class code generated from the class classification unit 143 is supplied to the prediction coefficient memory 144 as an address signal.

The prediction coefficient memory 144 stores prediction coefficients w _{1 to} w _n acquired by learning in advance for each address. That is, using a teacher signal and an input signal, a predicted value is obtained by linear linear combination of a plurality of data and coefficients of the input signal, and the sum of squares of the error between the predicted value and the true value of the teacher signal is minimized. The coefficient such as is obtained for each class by the method of least squares. From the prediction coefficient memory 144 corresponding to the class code and the prediction coefficients W1～w _n read out a peripheral code values x ₁ ~x _n from the delay unit 145 is supplied to the prediction computation unit 146.

The prediction calculation unit 146 calculates the prediction value y by the following linear linear combination equation. y = w ₁ x ₁ + w ₂ x ₂ + ... + w _n x _{n The} prediction value y obtained by the prediction calculation unit 146 is taken out to the output terminal 147. The peripheral code value used for class classification and the peripheral code value used for prediction calculation may be different.

Class classification adaptive prediction circuits 59, 60, 6
1 and 62 classify the pixel of the lower hierarchy to be predicted based on the level distribution of a plurality of pixels spatially nearby (included in the upper hierarchy). Then, a table of prediction coefficients or prediction values for each class, which is obtained by learning in advance, is stored in the memory, and a plurality of prediction coefficients or one prediction value corresponding to the class is read from the memory. The prediction value is used as it is, and the prediction coefficient is generated by linear linear combination with a plurality of pixels. Such class classification adaptive prediction is disclosed in, for example, Japanese Patent Application No. 4-155719 proposed by the present applicant.

The same configuration as the coding unit 125 (see FIG. 2) in the above-described embodiment is provided on the encoder side of hierarchical coding. That is, the quantizers 50, 5 have the same configuration as that of the previous stage up to the ADRC encoder 8.
The variable length encoders 67, 68, 69, 70, 71 have the same configurations as those of the bit plane encoding circuit 9, respectively.

Next, FIG. 13 shows an example of the configuration on the decoder side of hierarchical encoding corresponding to the above encoder. The respective hierarchical data generated on the encoder side are supplied to the input terminals 81, 82, 83, 84 and 85 as d30 to d34, respectively. And variable length code decoders 86, 87, 8
Variable length codes are decoded at 8, 89 and 90. For these decoders, the inverse quantizers 91, 92, 93,
94 and 95 are respectively connected.

First, the fifth layer input data d34 is subjected to a decoding process corresponding to the quantization applied by the encoder in the inverse quantizer 95 to become the image data d39, which is the class classification adaptive prediction circuit 107 and the computing unit. 103 is supplied. Further, the image data d39 is taken out from the output terminal 112 as an image output of the fifth layer.

In the class classification adaptive prediction circuit 107, the fourth
The class classification adaptive prediction is performed on the image data of the hierarchy, and the prediction value d47 of the fourth hierarchy data is generated. The data d38 (that is, the difference value) from the inverse quantizer 94 and the predicted value d47 are added by the adder 99. Adder 99
To the image data d43 supplied from the inverse quantizer 95 to the arithmetic unit 103, and the arithmetic unit 103 performs the above-described calculation to obtain the value of the non-transmission pixel. To all pixel values of the fourth hierarchy are restored. In this calculator 103, all the pixel values restored are supplied to the class classification adaptive prediction circuit 106 and the calculator 102 as image data d51. Further, the image data d51 is taken out from the output terminal 111 as the output of the fourth layer.

In the class classification adaptive prediction circuit 106, the third
The class classification adaptive prediction is performed on the image data of the hierarchy, and the prediction value d46 of the third hierarchy data is generated. The data d37 from the inverse quantizer 93 and the predicted value d46 are added by the adder 98. Image data d42 from the adder 98
Is supplied to the arithmetic unit 102, the value of the non-transmission pixel is obtained by the arithmetic unit 102, and all pixel values of the third layer are restored from the image data d51 and the image data d42 supplied from the arithmetic unit 103. In this arithmetic unit 102, the restored all pixel values are supplied to the class classification adaptive prediction circuit 105 and the arithmetic unit 101 as image data d50. Further, the image data d50 is taken out from the output terminal 110 as an output of the third layer.

In the class classification adaptive prediction circuit 105, the class classification adaptive prediction is performed on the image data of the second layer, and the prediction value d45 of the second layer data is generated. The data d36 from the inverse quantizer 92 and the predicted value d45
And are added by the adder 97. The image data d41 is supplied from the adder 97 to the arithmetic unit 101, the value of the non-transmission pixel is obtained by the arithmetic unit 101, and all the pixel values of the second layer from the image data d50 and the image data d41 supplied from the arithmetic unit 102. Is restored. In this arithmetic unit 101,
The restored all pixel values are supplied to the class classification adaptive prediction circuit 104 and the calculator 100 as image data d49. Further, the image data d49 is taken out from the output terminal 109 as an output of the second layer.

Further, in the class classification adaptive prediction circuit 104, the class classification adaptive prediction is performed on the image data of the first layer, and the predicted value d44 of the first layer data is generated. The data d35 from the inverse quantizer 91 and the predicted value d44
And are added by the adder 96. The image data d40 is supplied from the adder 96 to the arithmetic unit 100, the value of the non-transmission pixel is obtained by the arithmetic unit 100, and all pixel values of the first layer are calculated from the image data d49 and the image data d40 supplied from the arithmetic unit 101. Is restored. In this arithmetic unit 100,
The restored all pixel values are the first image data d48 and the first
It is taken out from the output terminal 108 as the output of the hierarchy.
Class classification adaptive prediction circuits 104, 105, 106, 10
Each of 7 has the configuration described above and shown in FIG. Thus, in hierarchical coding in which the number of pixels to be coded is prevented from increasing, it is possible to improve coding efficiency by introducing the class classification adaptive prediction.

Decoding unit 134 of the above-described embodiment.
And a variable length code decoder 86, 87, 8
8, 89, 90 and inverse quantizers 91, 92, 93, 9
4 and 95 respectively. Therefore, according to another embodiment in which the present invention is applied to the above-mentioned hierarchical encoding,
As in the above-described embodiment, the amount of data can be further reduced without transmitting the data of the block of 0-bit allocation.

The present invention can also be applied to the quantization of the residual signal generated by the predictive coding other than the predictive coding described above. The present invention can also be applied to a system having a buffering configuration that controls the amount of generated data by controlling the quantization step width.

[0081]

According to the present invention, it is possible to remove the plane that is always 0 in the bit planes, so that it is possible to further reduce the amount of transmission data.

[Brief description of the drawings]

FIG. 1 is a block diagram of an example of a recording / reproducing or transmission system to which the present invention can be applied.

FIG. 2 is a block diagram of an embodiment of the present invention.

FIG. 3 is a schematic diagram used to explain the generation of a residual signal and its blocking in an embodiment of the present invention.

FIG. 4 is a schematic diagram used to explain offset calculation in an embodiment of the present invention.

FIG. 5 is a block diagram of an example of an offset detection circuit in an embodiment of the present invention.

FIG. 6 is a block diagram of an example of an ADRC encoder according to an embodiment of the present invention.

FIG. 7 is a schematic diagram used for explaining a bit plane in an embodiment of the present invention.

FIG. 8 is a schematic diagram used for explaining a process of removing 0 data in the embodiment of the present invention.

FIG. 9 is a block diagram of a decoding unit according to an embodiment of the present invention.

FIG. 10 is a schematic diagram used to describe an example of hierarchical encoding.

FIG. 11 is a schematic diagram used to describe an example of hierarchical encoding.

FIG. 12 is a block diagram showing an example of a configuration on the encoding side of another embodiment in which the present invention is applied to hierarchical encoding.

FIG. 13 is a block diagram showing an example of a configuration on the decoding side according to another embodiment of the present invention.

FIG. 14 is a block diagram showing an example of the configuration of a class classification adaptive prediction circuit according to another embodiment of the present invention.

[Explanation of symbols]

2 ... Maximum value detection circuit, 3 ... Minimum value detection circuit, 4
... Offset detection circuit, 7 ... DR, MIN 'calculation circuit, 8 ... ADRC encoder, 9 ... Bit plane coding circuit, 11a, 11b, 11c ... Dynamic range determination circuit, 12a, 12b, 12c
..Memory, 13 ... Variable-length coding circuit

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Kunio Kawaguchi 6-735 Kitashinagawa, Shinagawa-ku, Tokyo Sony Corporation

Claims (8)

[Claims] 1. An information signal coding apparatus for coding an input digital information signal so as to reduce the amount of generated data, a means for generating a residual signal between sample values of the input digital information signal, and the residual difference. Means for dividing the signal into blocks, first variable-length encoding means for quantizing the blocked residual signal with the number of quantization bits determined in block units, and first variable-length encoding means Is divided into bit planes, the data of the block in which the bit assigned to the bit plane does not exist is removed based on the information that defines the number of quantized bits for the first variable length coding, and this removal is performed. An information signal coding device, comprising: second variable length coding means for variable length coding each subsequent bit plane. 2. The information signal coding apparatus according to claim 1, wherein the first variable-length coding means detects the maximum value and the minimum value of a plurality of residual signals included in the block. Means for detecting the dynamic range of the block from the maximum value and the minimum value, and modified input data modified to have a relative level relationship based on the value defining the dynamic range. An information signal code comprising a forming means and a means for quantizing the modified input data with the number of bits equal to or less than the original number of quantization bits and with the number of quantization bits defined by the dynamic range. Device. 3. The information signal encoding device according to claim 2, wherein the second variable-length encoding means extracts data of a block in which no bit assigned to the bit plane exists based on the dynamic range. An information signal coding device, characterized in that the bit plane after the removal is subjected to variable length coding. 4. The information signal coding apparatus according to claim 1, wherein the first variable length coding means sets a quantization restoration value corresponding to a residual signal having a value of 0 to 0. An information signal coding apparatus characterized by correcting data. 5. An information signal encoding method for encoding an input digital information signal so as to reduce the amount of generated data, a step of generating a residual signal between sample values of the input digital information signal, and the residual error. A step of dividing the signal into blocks, a first variable-length encoding step of quantizing the blocked residual signal with a quantization bit number determined in block units, and a first variable-length encoding step The output is divided for each bit plane, and based on the information that defines the number of quantized bits for the first variable length coding, the data of the block in which the bit assigned to the bit plane does not exist is removed, and after this removal And a second variable-length coding step for variable-length coding each of the bit planes. 6. An information signal coding apparatus for forming at least first and second hierarchical data from an input digital information signal and coding and transmitting the first and second hierarchical data. Means for forming the second hierarchical data having a resolution lower than that of the first hierarchical data, means for predicting the first hierarchical data from the second hierarchical data, the predicted data and the first hierarchical data A first means for forming a residual signal with the hierarchical data; a means for blocking the residual signal; and a first quantization step for quantizing the blocked residual signal by the number of quantization bits determined in block units. The output of the variable length coding means and the output of the first variable length coding means is divided into bit planes, and based on the information that defines the number of quantization bits for the first variable length coding, An information signal coding apparatus comprising: second variable-length coding means for removing data of a block having no bits allocated to the topplane and performing variable-length coding on each of the removed bitplanes. 7. An information signal encoding method for forming at least first and second hierarchical data from an input digital information signal, and encoding and transmitting the first and second hierarchical data. Forming the second hierarchical data having a lower resolution than that of the first hierarchical data; predicting the first hierarchical data from the second hierarchical data; the predicted data and the first hierarchical data; A step of forming a residual signal with hierarchical data; a step of dividing the residual signal into blocks; a step of quantizing the blocked residual signal with a quantization bit number determined in block units; A variable length coding step, and an information for dividing the first variable length coded output for each bit plane to define the number of quantization bits for the first variable length coding. Based on the information, the second variable-length coding step of removing the data of the block in which the bit assigned to the bit-plane does not exist and performing the variable-length coding on the removed bit-planes, respectively. Information signal coding method. 8. A residual signal is quantized by a first variable length coding, and a coded residual signal coded by a second variable length coding is decoded for each bit plane of the coded residual signal. In the information signal decoding method, the data of the block removed in each of the bit planes is restored based on the information defining the number of quantization bits of the first variable length coding, and the variable length coding is decoded. And secondly combining the decoded bit planes
Variable-length coding decoding step, variable-length coding decoding step for performing the variable-length coding decoding on the combined bit plane data, and the decoded residual A method for decoding an information signal, comprising the steps of: decomposing the signal into blocks and converting it into the original order.