JP3629826B2 - Information signal encoding apparatus, encoding method, and information signal decoding method - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to an information signal encoding device, an encoding method, and an information signal decoding method that reduce the amount of generated data of digital information signals such as digital audio signals and digital image signals.
[0002]
[Prior art]
Predictive coding is known to reduce the amount of transmission information such as digital audio signals and digital image signals. For example, a one-dimensional DPCM forms a difference (residual) between an input sample value and a predicted value in the time or spatial direction, and a two-dimensional DPCM forms a residual between the input sample value and a predicted value in the spatial direction. . Since the digital information signal has a correlation in the time direction and the spatial direction, the level of the residual signal is smaller than the sample value. Therefore, the residual signal can be requantized with a smaller number of bits than the original number of quantization bits, thereby reducing the amount of information.
[0003]
As a quantization device for a residual signal, a nonlinear quantization device is known in which the quantization step width near 0 is made finer and the quantization step width becomes coarser as the level increases. In the conventional quantization apparatus including this nonlinear quantization, all levels of the residual signal that can be generated are targeted for quantization. For example, when one sample (one pixel) of a digital image signal is quantized to 8 bits, a value of (−255 to +255) may exist as a residual signal. The conventional quantization apparatus uses the entire range as the object of quantization.
[0004]
[Problems to be solved by the invention]
Since the conventional quantization apparatus targets the entire range of residual signals that can be generated, if the number of quantization bits is reduced, the quantization accuracy decreases, and the number of quantization bits increases. There was a problem that the amount of generated data increased. As a result, there has been a problem that audio signals and image signals with sufficient quality cannot be obtained when decoding.
[0005]
Accordingly, an object of the present invention is to provide an information signal encoding apparatus, encoding method, and decoding method capable of further reducing the data amount of the quantized output when the residual signal is quantized. In other words, when the residual signal is blocked and the level range of the residual signal for each block satisfies a certain condition, the quantization mode is switched so as to reduce the number of quantization bits.
[0006]
[Means for Solving the Problems]
The invention of claim 1 is an information signal encoding apparatus for encoding an input digital information signal so as to reduce the amount of generated data.
Input digital information signalAnd the predicted value of the input digital information signalMeans for generating a residual signal of
Means for blocking the residual signal;
Means for detecting the maximum and minimum values for each block;
The residual signal for each block from the maximum and minimum valuesExistenceDetermine if the range is crossing zero,ExistenceInstruct the first quantization mode when the range crosses 0,ExistenceMode determining means for instructing the second quantization mode when the range does not cross 0;
In the first quantization mode, the residual signal is quantized with a predetermined number of bits less than the original number of bits, and in the second quantization mode, the residual signal is quantized with a number of bits smaller than the original number of bits. And quantization means adapted to reduce the number of bits by code conversion,
Information identifying first and second quantization modes;
Transmission means for transmitting the output of the quantization means;
An information signal encoding device characterized by comprising:
[0007]
According to a third aspect of the present invention, there is provided an information signal encoding method for encoding an input digital information signal so as to reduce the amount of generated data.
Input digital information signalAnd the predicted value of the input digital information signalGenerating a residual signal of
Blocking the residual signal;
Detecting the maximum and minimum values for each block;
The residual signal for each block from the maximum and minimum valuesExistenceDetermine if the range is crossing zero,ExistenceInstruct the first quantization mode when the range crosses 0,ExistenceA mode determining step for indicating the second quantization mode when the range does not cross 0;
In the first quantization mode, the residual signal is quantized with a predetermined number of bits less than the original number of bits, and in the second quantization mode, the residual signal is quantized with a number of bits smaller than the original number of bits. And a quantization step to reduce the number of bits by code conversion,
Information identifying first and second quantization modes;
Transmitting the output of the quantizing means;
An information signal encoding method characterized by comprising:
[0008]
According to a fourth aspect of the present invention, there is provided an information signal encoding apparatus in which at least first and second hierarchical data are formed from an input digital information signal, and the first and second hierarchical data are encoded and transmitted.
Means for forming second hierarchical data having a lower resolution than the first hierarchical data;
Means for predicting the first hierarchical data from the second hierarchical data;
Means for forming a residual signal between the predicted data and the first tier data;
Means for blocking the residual signal;
Means for detecting the maximum and minimum values for each block;
The residual signal for each block from the maximum and minimum valuesExistenceDetermine if the range is crossing zero,ExistenceInstruct the first quantization mode when the range crosses 0,ExistenceMode determining means for instructing the second quantization mode when the range does not cross 0;
In the first quantization mode, the residual signal is quantized with a predetermined number of bits less than the original number of bits, and in the second quantization mode, the residual signal is quantized with a number of bits smaller than the original number of bits. And quantization means adapted to reduce the number of bits by code conversion,
Information identifying first and second quantization modes;
Transmission means for transmitting the output of the quantization means;
An information signal encoding device characterized by comprising:
[0009]
According to a fifth aspect of the present invention, there is provided an information signal encoding method in which at least first and second hierarchical data are formed from an input digital information signal, and the first and second hierarchical data are encoded and transmitted.
Forming second hierarchical data having a lower resolution than the first hierarchical data;
Predicting first hierarchical data from second hierarchical data;
Forming a residual signal between the predicted data and the first tier data;
Blocking the residual signal;
Detecting the maximum and minimum values for each block;
The residual signal for each block from the maximum and minimum valuesExistenceDetermine if the range is crossing zero,ExistenceInstruct the first quantization mode when the range crosses 0,ExistenceA mode determining step for indicating the second quantization mode when the range does not cross 0;
In the first quantization mode, the residual signal is quantized with a predetermined number of bits less than the original number of bits, and in the second quantization mode, the residual signal is quantized with a number of bits smaller than the original number of bits. And a quantization step to reduce the number of bits by code conversion,
Information identifying first and second quantization modes;
A transmission step for transmitting the quantized output and
An information signal encoding method characterized by comprising:
[0010]
The invention of claim 6A residual signal between the input digital information signal and the predicted value of the input digital information signal is generated, the residual signal is blocked, the maximum and minimum values are detected for each block, and the maximum and minimum values are detected for each block. It is determined whether or not the existence range of the residual signal is crossing 0, the first quantization mode is instructed when the existence range crosses 0, and the second quantum when the existence range does not cross 0 Mode is instructed,In the first quantization mode, the residual signal is quantized with a smaller number of bits than the original number of bits, and in the second quantization mode, the residual signal is quantized with a smaller number of bits than the original number of bits. At the same time, it is encoded to reduce the number of bits by code conversion.And an information signal encoding method in which information for identifying the first and second quantization modes and information on the residual signal are transmitted.In the decryption method,
Based on the identification information, in the first quantization mode, the data is inversely quantized, and in the second quantization mode, the data is transcoded and inversely quantized,
An information signal decoding method comprising the steps of: decomposing a dequantized residual signal into blocks and converting the residual signal into an original order.
[0011]
By increasing the degree of concentration of the level distribution of the residual signal, the residual signal can be requantized with a smaller number of bits than the original number of quantization bits. Also, when the residual signal distribution satisfies a certain condition, the residual signal can be quantized with a smaller number of bits.
[0012]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, an embodiment of the present invention will be described with reference to the drawings. In this embodiment, the present invention is applied to a digital image signal obtained by sampling a video signal at a predetermined sampling frequency and converting each sample into a predetermined number of quantization bits. FIG. 1 shows the overall configuration of a system according to an embodiment of the present invention.
[0013]
In FIG. 1, a digital video signal is supplied to an input terminal indicated by 121. The input signal is supplied to the subtractor 123, the output (residual signal) of the subtractor 123 is supplied to the blocking circuit 124 and the predictor 122, and the prediction signal generated by the predictor 122 is supplied to the subtractor 123. . The subtractor 123 subtracts the prediction signal from the input signal to generate a prediction residual. This residual signal is supplied to the block forming circuit 124 and converted from raster scan order to block order data. The blocked residual signal is supplied to the encoding unit 125.
[0014]
As will be described later, the quantization circuit in the encoding unit 125 is switched between the first quantization mode and the second quantization mode in accordance with the frequency distribution of the blocked residual signal. . For example, when the number of bits of the residual signal is 8 bits, when the first quantization mode is selected, a 3-bit quantization output is generated from the encoding unit 125. When the second quantization mode is selected, a quantized output converted into 2 bits is generated by the code conversion table in the encoding unit 125.
[0015]
The encoded output of the encoding unit 125 is supplied to the error correction code encoder 126, and a redundant code of the error correction code is added. The output of the error correction code encoder 126 is supplied to the modulation unit 127. The modulation unit 127 modulates the digital signal into a form suitable for recording, transmission, and the like. An output signal from the modulation unit 127 is supplied to the recording unit 128, and the recording signal is recorded on the information signal recording medium 129 by the recording unit 128. It is also possible to transmit data via the transmission path 130. In this case, a transmission unit is used instead of the recording unit 128. A mode signal indicating the quantization mode is also recorded or transmitted together with the encoded residual signal. The information signal recording medium 129 is a disk-like or tape-like recording medium using magnetism, magneto-optical, phase change or the like. A semiconductor memory is also a kind of recording medium.
[0016]
Data is reproduced from the recording medium 129 by the reproduction unit 131 or data transmitted via the transmission path 130 is received. The data reproduced by the reproduction unit 131 is demodulated by the demodulator 132, and the demodulated output is supplied to the error correction code decoder 133. The decoder 133 corrects the error by using the redundant code, and corrects the remaining error that cannot be corrected to be inconspicuous.
[0017]
The output of the error correction decoder 133 is supplied to the decoding unit 134. As will be described later, the decoding unit 134 performs inverse quantization processing for converting the quantized output into a representative value (quantized restoration value), contrary to the encoding unit 125. The inverse quantization circuit in the decoding unit 134 performs inverse quantization processing according to the quantization mode indicated by the mode signal. A decoded residual signal is generated from the decoding unit 134. This decoded residual signal is supplied to the block decomposition circuit 135. In the block decomposition circuit 135, the block structure is returned to the order of raster scanning.
[0018]
The decoded residual signal is supplied to the adder circuit 136. A decoding image signal is formed by the adding circuit 136 and taken out to the output terminal 137. Further, the decoded image signal is supplied to the predictor 138, and a prediction signal is generated. The prediction signal is supplied to the addition circuit 136.
[0019]
FIG. 2 shows an example of the encoding unit 125. The blocked residual signal from the blocking circuit 124 is supplied to the input terminal 1. FIG. 3 schematically shows the formation of the residual signal. One rectangular area in FIG. 3 corresponds to one pixel. Each of a to h represents a locally decoded pixel value, and AP represents a pixel value before being encoded. A predicted value A ′ for pixel value A is generated by the predictor 122 using neighboring local decoded pixel values. For example, the predicted value A ′ is formed according to a prediction formula such as A ′ = 4c−3 (b−f), A ′ = f + c−b, or the like. The predicted values for the pixel values B, C,... Are calculated by the same prediction formula. When represented by a general formula, a predicted value is generated by (αa + βb + γf, where α, β, and γ are constants).
[0020]
The subtractor 123 subtracts the predicted value (for example, A ′) from the pixel value (for example, A) to generate a residual signal Δa. Similarly, residual signals Δb, Δc,... Are generated. In the blocking circuit 124, the generated residual signal is converted into a block structure. For example, the block forming circuit 124 forms data of blocks of residual signals Δa to Δp corresponding to the (4 × 4) block, as shown by the thick line frame in FIG. 3A. When a digital audio signal is handled, a prediction value in the time direction is formed, and a one-dimensional residual signal block is formed.
[0021]
By concentrating the level range of the residual signal, the degree of concentration can be increased. When one pixel is 8-bit data, the distribution of the occurrence frequency of the residual signal of one screen is in the range of (−255 to +255) around 0, and the frequency of the residual is 0. Maximum. However, when divided into blocks, the frequency distribution of residuals is more concentrated than the original distribution.
[0022]
This is due to the fact that the residuals in the blocks in the small space are relatively large in comparison with one screen, and the residuals are strongly correlated in the blocks. Therefore, the block residual signal can be requantized with a smaller number of bits than the original number of quantization bits. Further, in the distribution of the residual signals that are blocked, the frequency of the value of 0 is not necessarily the maximum. For example, when the luminance level gradually changes in the diagonal direction in the block, for example, a distribution in which the frequency of the value of 0 does not become maximum occurs. Note that the method of increasing the degree of concentration of the residual signal distribution is an example of blocking, and other methods are also possible.
[0023]
Returning to FIG. 2, the encoding unit 125 will be described. The residual signal from the input terminal 1 is supplied to the maximum value detection circuit 2, the minimum value detection circuit 3, and the delay circuit 4. The maximum value detection circuit 2 detects the maximum value MAX for each block, and the minimum value detection circuit 3 detects the minimum value MIN for each block. The detected maximum value MAX and minimum value MIN are supplied to the mode determination circuit 5.
[0024]
The mode determination circuit 5 is supplied with the block residual signal, the maximum value MAX, and the minimum value MIN, and the quantization mode is determined based on the level range of the residual signal of the block to indicate the mode. A signal MODE (for example, 1 bit) is generated. The mode signal MODE is supplied to the quantization circuit 6, and the residual signal from the input terminal 1 is supplied to the quantization circuit 6 through the delay circuit 4 for phase matching. In the quantization circuit 6, the residual signal is requantized with a smaller number of quantization bits than the original number of quantization bits (for example, 8 bits). In the quantization circuit 6, the first and second quantization modes are selected according to the mode signal MODE.
[0025]
The first quantization mode is a normal one that re-quantizes the 8-bit residual signal to generate a smaller number of quantization bits, eg, 3 bits. The second quantization mode is applied when the level range of the blocked residual signal does not cross zero. In this embodiment, when the minimum value MIN of the residual signal is larger than (Δ / 2), the second quantization mode is applied. Here, Δ is DR / 2 when the number of requantization bits is n.ⁿIs a quantization step calculated by DR is a dynamic range and can be calculated by (MAX-MIN).
[0026]
In the second quantization mode, a code signal (for example, 3 bits) generated by re-quantization is converted according to a predetermined rule in the same manner as in the first quantization mode, and a quantized output having a smaller number of bits, for example, 2 bits Converted. Code conversion rules for converting a 3-bit code into a 2-bit quantized output are shown below.
100-00
101-01
110-10
111-11
[0027]
The quantization process will be described with reference to FIG. As described above, the residual signal generated by the predictive coding has the maximum frequency of 0 when viewed in the whole frame. However, the residual signal varies depending on the block as shown in FIG. 4A. Have a bias. FIG. 4A shows a distribution of residual signals biased to the negative side, a distribution of residual signals that coincided with a value having a maximum frequency of 0, and a distribution of residual signals biased to the positive side.
[0028]
FIG. 4B shows the frequency distribution of the residual signal that crosses the value of 0. In the case of quantizing the residual signal, for example, the interval between MAX and MIN is 2³= 8, and the same code is assigned to the residual signals belonging to the range. When the code is restored, it is converted to a representative value in the middle of the range. In general, if the code has n bits, 2ⁿThe range between MAX and MIN is divided into a number range. Such quantization is the first quantization mode.
[0029]
FIG. 4C shows an example of the frequency distribution of the blocked residual signal. That is, FIG. 4C shows a distribution 30a in which the minimum value MIN is equal to Δ / 2, a distribution 30b (shown by a broken line) that crosses 0 similarly to that in FIG. 4B, and a maximum value MAX is −Δ / 2. A distribution 30c (indicated by a broken line) equal to is shown. In this embodiment, when the condition of (MIN ≧ Δ / 2) is satisfied as in the frequency distribution 30a, the second quantization mode is applied. In the second quantization mode, the code as described above is used. Conversion is done. On the decoding side, code conversion in the reverse direction from 2 bits to 3 bits is performed, and the 3 bits code is inversely quantized.
[0030]
For example, if the residual signal having the frequency distribution 30a in FIG. 4C is quantized in the second quantization mode, 100 to 111 quantized outputs in the range of MIN to MAX are converted to 00 to 11 quantized outputs. On the other hand, on the decoding side, the quantized output of 00 to 11 is converted into the code of 100 to 111. Inverse quantization can be performed by converting the converted 3-bit code into a representative value in the same manner as the 3-bit quantization output generated in the first quantization mode.
[0031]
Unlike the embodiment of the present invention, the second quantization mode may be applied when the maximum value MAX of the residual signal of the block is smaller than −Δ / 2 (for example, the frequency distribution 30c in FIG. 4C). good. Further, the second quantization mode may be applied when the minimum value MIN is (MIN ≧ 0) or when the maximum value MAX is (MAX ≦ 0).
[0032]
An example of the quantization circuit 6 is shown in FIG. A delayed residual signal is supplied from the delay circuit 4 to the input terminal indicated by 15. An input residual signal is supplied to the input terminal of the switching circuit 16 switched by the mode signal MODE. For example, quantizers 17a and 17b that generate a 3-bit output are connected to output terminals a and b of switching circuit 16, respectively. A code conversion circuit 18 is connected to the quantizer 17b. The code conversion circuit 18 is a circuit that converts 3 bits into 2 bits as described above. The output of the quantizer 17a or 17b is taken out to the output terminal 19.
[0033]
The mode signal MODE indicates the second quantization mode when (MIN ≧ Δ / 2) with respect to the residual signal of the block by the mode determination circuit 5, while in other cases, A mode signal MODE indicates the first quantization mode. In the first quantization mode, the output terminal a of the switching circuit 16 is selected, and in the second quantization mode, the output terminal b of the switching circuit 16 is selected. Therefore, in the first quantization mode, a 3-bit quantization output is generated at the output terminal 19, and in the second quantization mode, a 2-bit quantization output is generated at the output terminal 19. The quantizers 17a and 17b may be shared.
[0034]
Returning to FIG. 2, the output of the quantization circuit 6 is supplied to the bit plane encoding circuit 7. The bit plane encoding circuit 7 divides n bits, for example, a 2-bit code q into an MSB (most significant bit) plane and an LSB (least significant bit) plane. The MSB plane is a set of MSBs of supplied 2-bit quantized values, and the LSB plane is a set of LSBs. For simplicity, FIG. 6A shows a case where one screen is composed of (4 × 3 = 12 blocks) and each block includes a code q of (4 × 4) residual signals.
[0035]
In FIG. 6A, 0, 1, 2, 3 of the value of the code q shown as an example means (00), (01), (10), (11) with 2 bits, respectively. In the example of FIG. 6A, as shown in FIG. 6B, the bit plane encoding circuit 7 divides, for example, the code q of one screen into an MSB plane and an LSB plane. When the number of quantization bits is 3 bits, an intermediate bit plane is further formed. In one embodiment of the present invention, a two-bit or three-bit quantized output is generated by two quantization modes. In the case of forming a bit plane, it is necessary to know the number of bits of the quantized output. For this reason, the mode signal MODE is supplied to the bit plane encoding circuit 7.
[0036]
Each bit plane generated by the bit plane encoding circuit 7 is supplied to the variable length encoding circuit 8, and each bit plane is variable length encoded. The variable length coding circuit 8 performs run length coding, for example, MMR (Modified MR), for each bit plane. The output of the variable length coding circuit 8 is supplied to the framing circuit 9. The above-described mode signal MODE is also supplied to the framing circuit 9. The mode signal MODE and the variable-length encoded code are output to the output terminal 10 of the framing circuit 9 as data having a predetermined frame structure.
[0037]
Next, referring to FIG.1An example of the decoding unit 134 in the middle will be described. Reproduced or received data from the error correction decoder 133 is supplied to the input terminal 31 of the decoding unit 134. The frame decomposition circuit 32 separates the variable-length encoded residual signal code from the mode signal MODE. The code of the separated residual signal is decoded by the variable length decoding circuit 33. The variable length decoding circuit 33 corresponds to the variable length encoding circuit 13. The decoded output of the variable length decoding circuit 33 is supplied to the bit plane decoding circuit 34 to synthesize the bit plane. In this case, the bit plane is correctly synthesized by the separated mode signal MODE.
[0038]
The output of the bit plane decoding circuit 34 is supplied to the input terminal of the switching circuit 35. The switching circuit 35 is controlled by a mode signal MODE. When the mode signal MODE indicates the first quantization mode, the output terminal a of the switching circuit 35 is selected, and when this indicates the second quantization mode, the output terminal b of the switching circuit 35 is selected. The The output terminal a is connected to an inverse quantizer 36a that dequantizes a 3-bit quantization code and generates a quantized restoration value. A code conversion circuit 37 that converts a 2-bit quantized output into a 3-bit code is connected to the output terminal b, and an inverse quantizer 36 b is connected to the code conversion circuit 37. The inverse quantizer 36b converts a 3-bit code into a restored value, similarly to the inverse quantizer 36a.
[0039]
The restored values generated by the inverse quantizers 36a and 36b, that is, the decoded decoded residual signals are taken out to the output terminal 38. The decoded residual signal taken out to the output terminal 38 is supplied to the block decomposition circuit 135 (see FIG. 1). The inverse quantizers 36a and 36b may be shared.
[0040]
Next, another embodiment in which the present invention is applied to hierarchical coding will be described. The hierarchical encoding device described here can prevent an increase in the number of encoding target pixels by performing prediction between hierarchies and using a simple arithmetic expression for the inter-layer data.
[0041]
The hierarchical encoding method will be described with reference to FIG. FIG. 8 shows, as an example, a schematic diagram between four hierarchies having the first hierarchy as the lowest hierarchy (original picture) and the fourth hierarchy as the highest hierarchy. For example, when the average value of the lower layer data of four pixels corresponding spatially is adopted as the upper layer data generation method, the number of transmission pixels can be prevented from increasing.
[0042]
That is, the upper layer data is M and the lower layer pixel value is x.₀  , X₁  , X₂  , X₃  Then,
M = 1/4 · (x₀  + X₁  + X₂  + X₃)
As a result, data M is formed. And, for example, x of the data M and the four data₃The other three data are transmitted. On the receiving or playback side,
x₃  = 4 · M- (x₀  + X₁  + X₂  )
Non-transmission pixel x by a simple arithmetic expression₃  Can be easily restored. In FIG. 8, hatched rectangles indicate non-transmission pixels.
[0043]
FIG. 9 shows a configuration of hierarchical encoding of, for example, five layers using the above-described averaging. Assume that the first hierarchy is the resolution level of the input image. The block size of this first layer is (1 × 1). The second layer data is generated by averaging four pixels of the first layer data. In this example, the first hierarchy data X₁  (0) to X₁  Based on the average value of (3), the second hierarchical data X₂  (0) is generated. X₂  Second layer data X adjacent to (0)₂  (1) to X₂  Similarly, (3) is generated by averaging four pixels of the first layer data. The block size of the second hierarchy is (1/2 × 1/2).
[0044]
Further, the third layer data is generated by averaging four pixels of the second layer data corresponding spatially. The block size of the third hierarchy is (1/4 × 1/4). Similarly, the fourth layer data is generated from the third layer data. The block size of the fourth layer is (1/8 × 1/8). Finally, the fifth hierarchy data X which is the highest hierarchy₅  (0) is the fourth layer data X₄  (0) to X₄  It is generated by the average value of (3). The block size of the fifth layer is (1/16 × 1/16).
[0045]
By applying the class classification adaptive prediction to the upper layer data for the hierarchical structure data in which the increase in the number of encoding target pixels is prevented, the lower layer data is predicted, and the difference between the lower layer data and the predicted value ( That is, it is possible to reduce the amount of transmission data by generating a residual signal. FIG. 10 shows such a coding unit. The first hierarchy data d0 is supplied as input image data d0 to the averaging circuit 42 and the subtractor 46 via the input terminal 41. The first layer data is image data of the original resolution.
[0046]
The input pixel data d0 is subjected to ¼ averaging processing in the averaging circuit 42 to generate hierarchical data d1. This hierarchical data d1 corresponds to the second hierarchical data shown in FIG. The generated hierarchical data d1 is supplied to the averaging circuit 43 and the subtractor 47.
[0047]
The averaging circuit 43 performs the same processing as the averaging circuit 42 on the hierarchical data d1, and generates hierarchical data d2. This hierarchical data d2 corresponds to the third hierarchical data. The generated hierarchical data d2 is supplied to the averaging circuit 44 and the subtracter 48. Similarly, the averaging circuit 44 performs ¼ averaging processing on the hierarchical data d2 to generate hierarchical data d3. This hierarchical data d3 corresponds to the fourth hierarchical data. The generated hierarchical data d3 is supplied to the averaging circuit 45 and the subtracter 49. Further, the averaging circuit 45 similarly performs a 1/4 averaging process on the hierarchical data d3 to generate hierarchical data d4. This hierarchical data d4 corresponds to the fifth hierarchical data. The generated hierarchical data d4 is supplied to the quantizer 54.
[0048]
And about these five hierarchical data, prediction is performed between hierarchies. First, the quantization processing for compression performed in the fifth layer is performed by the quantizer 54. The output data d21 of the quantizer 54 is supplied to the variable length code encoder 71 and also to the inverse quantizer 58. The output of the encoder 71 is taken out to the output terminal 76 as fifth-layer data. The output data d16 of the inverse quantizer 58 supplied with the encoded data d21 is supplied to the class classification adaptive prediction circuit 62.
[0049]
In the class classification adaptive prediction circuit 62, prediction processing is performed using the data d16, a predicted value d12 of the fourth layer data is generated, and the predicted value d12 is supplied to the subtractor 49. In the subtractor 49, a difference value between the hierarchical data d3 supplied from the averaging circuit 44 and the predicted value d12 is obtained, and the difference value d8 is supplied to the quantizer 53.
[0050]
In the quantizer 53 to which the difference value d8 is supplied, requantization is performed so as to reduce the number of quantization bits as in the quantizer 54. The output data of the quantizer 53 is supplied to the arithmetic unit 66 and the inverse quantizer 57. In this calculator 66, a process of thinning out one pixel from four pixels is performed. Data d20 output from the arithmetic unit 66 is encoded by the variable-length code encoder 70, and the output of the encoder 70 is taken out as output data of the fourth layer to the output terminal 75.
[0051]
The fourth layer data d12 predicted by the class classification adaptive prediction circuit 62 and the output data (decoded residual signal) d15 of the inverse quantizer 57 are supplied to the class classification adaptive prediction circuit 61. In the class classification adaptive prediction circuit 61, the data d15 is added to the data d12 to form local decoded data of the fourth layer, and prediction processing is performed using the local decoded data. A predicted value d11 is generated, and this predicted value d11 is supplied to the subtractor 48. In the subtracter 48, a difference value between the data d2 supplied from the averaging circuit 43 and the predicted value d11 is obtained, and the difference value d7 is supplied to the quantizer 52.
[0052]
The output data of the quantizer 52 supplied with the difference value d7 is supplied to the arithmetic unit 65 and the inverse quantizer 56. In this calculator 65, a process of thinning out one pixel from four pixels is performed. The third layer data d19 output from the arithmetic unit 65 is supplied to the variable length code encoder 69, and the output of the encoder 69 is taken out to the output terminal 74 as third layer data.
[0053]
The third layer data d11 predicted by the class classification adaptive prediction circuit 61 and the output data d14 of the inverse quantizer 56 supplied with the encoded data from the quantizer 52 are supplied to the class classification adaptive prediction circuit 60. In the class classification adaptive prediction circuit 60, the data d14 is added to the data d11 to form third-layer local decoded data, and the local decoded data is used to perform prediction processing. A predicted value d10 is generated, and the predicted value d10 is supplied to the subtractor 47. In the subtractor 47, a difference value between the data d1 supplied from the averaging circuit 42 and the predicted value d10 is obtained, and the difference value d6 is supplied to the quantizer 51.
[0054]
The output data of the quantizer 51 is supplied to the arithmetic unit 64 and the inverse quantizer 55. The calculator 64 performs a process of thinning out one pixel from four pixels. The second layer data d18 output from the computing unit 64 is supplied to the variable length code encoder 68, and the output of the encoder 68 is taken out to the output terminal 73 as second layer data.
[0055]
The second hierarchy data d10 predicted by the class classification adaptive prediction circuit 60 and the output data d13 of the inverse quantizer 55 supplied with the encoded data from the quantizer 51 are supplied to the class classification adaptive prediction circuit 59. In the class classification adaptive prediction circuit 59, the data d13 is added to the data d10 to form second-level local decoded data, and prediction processing is performed using the local decoded data. A predicted value d9 is generated, and the predicted value d9 is supplied to the subtractor 46. In the subtractor 46, a difference value between the input pixel data d0 supplied from the input terminal 41 and the predicted value d9 is obtained, and the difference value d5 is supplied to the quantizer 50.
[0056]
The output data of the quantizer 50 supplied with the difference value d5 is supplied to the calculator 63. The calculator 63 performs a process of thinning out one pixel from four pixels. The first layer data d17 output from the computing unit 63 is supplied to the variable length code encoder 67, and the output of the encoder 67 is taken out to the output terminal 72 as the first layer data.
[0057]
Each of the class classification adaptive prediction circuits 59, 60, 61, and 62 predicts a lower layer pixel to be predicted based on a level distribution of a plurality of spatially neighboring pixels (included in the upper layer). It is. FIG. 12 shows an example of a class classification adaptive prediction circuit. Local decoded data from the input terminal 141 is supplied to the peripheral code value forming unit 142. The peripheral code value forming unit 142 includes a plurality of pieces of data x located in the vicinity of the lower layer pixel to be predicted.₁, X₂, ..., x_nAre synchronized. The peripheral code value is supplied to the class classification unit 143 and the delay unit 145. The class classification unit 143 calculates the peripheral code value x₁~ X_nThe class code corresponding to the level distribution pattern is output. As the class code, the peripheral code value itself may be used. However, since the number of classes becomes enormous, a code obtained by compressing each bit number of the peripheral code to 1 bit by ADRC or the like is used. The class code generated from the class classification unit 143 is supplied to the prediction coefficient memory 144 as an address signal.
[0058]
The prediction coefficient memory 144 stores the prediction coefficient w acquired in advance by learning.₁~ W_nIs stored for each address. That is, using a teacher signal (for example, fourth layer data) and an input signal (fifth layer data formed by averaging from the fourth layer data), a plurality of input signal data and coefficients A predicted value is obtained by linear linear combination of the above, and a coefficient that minimizes the square sum of errors between the predicted value and the true value of the teacher signal is obtained for each class by the method of least squares. Prediction coefficients w1 to w read from the prediction coefficient memory 144 corresponding to the class code._nAnd the peripheral code value x from the delay unit 145₁~ X_nAre supplied to the prediction calculation unit 146.
[0059]
In the prediction calculation unit 146, the predicted value y is calculated by the following linear linear combination formula.
y = w₁x₁+ W₂x₂+ ... + w_nx_n
The predicted value y obtained by the prediction calculation unit 146 is taken out to the output terminal 147. Note that the peripheral code value used for classification and the peripheral code value used for prediction calculation may be different.
[0060]
A configuration similar to that of the encoding unit 125 (see FIG. 2) in the above-described embodiment is also provided on the encoder side of the hierarchical encoding. That is, each of the quantizers 50, 51, 52, 53, and 54 has the same configuration as the configuration of the preceding stage up to the quantization circuit 6, and the configuration similar to the configuration of the subsequent stage from the bit plane encoding circuit 7 has a variable length. Each of the encoders 67, 68, 69, 70, 71 has.
[0061]
Next, FIG. 11 shows a configuration example on the decoder side of the hierarchical encoding corresponding to the encoder described above. Each hierarchical data generated on the encoder side is supplied to input terminals 81, 82, 83, 84, 85 as d30 to d34, respectively. The variable length code decoders 86, 87, 88, 89, 90 decode the variable length code. Inverse decoders 91, 92, 93, 94, and 95 are connected to these decoders, respectively.
[0062]
First, the fifth hierarchy input data d34 is subjected to decoding processing corresponding to the quantization performed by the encoder in the inverse quantizer 95, and becomes image data d39, which is supplied to the class classification adaptive prediction circuit 107 and the arithmetic unit 103. Is done. Further, the image data d39 is taken out from the output terminal 112 as the image output of the fifth hierarchy.
[0063]
In the class classification adaptive prediction circuit 107, class classification adaptive prediction is performed on the image data of the fourth layer, and the predicted value d47 of the fourth layer data is generated. The adder 99 adds the data d38 (that is, the difference value) from the inverse quantizer 94 and the predicted value d47. The image data d43 is supplied from the adder 99 to the calculator 103, and the calculator 103 performs the above-described calculation to obtain the value of the non-transmission pixel, and the image data d39 supplied from the inverse quantizer 95 and All pixel values in the fourth layer are restored from the image data d43. In this calculator 103, all the restored pixel values are supplied as image data d51 to the class classification adaptive prediction circuit 106 and the calculator 102. The image data d51 is taken out from the output terminal 111 as the output of the fourth hierarchy.
[0064]
In the class classification adaptive prediction circuit 106, class classification adaptive prediction is performed on the image data of the third hierarchy, and the predicted value d46 of the third hierarchy data is generated. The adder 98 adds the data d37 from the inverse quantizer 93 and the predicted value d46. The image data d42 is supplied from the adder 98 to the computing unit 102, the value of the non-transmission pixel is obtained by the computing unit 102, and all the pixel values of the third hierarchy are obtained from the image data d51 and the image data d42 supplied from the computing unit 103. Is restored. In this computing unit 102, all the restored pixel values are supplied as image data d50 to the class classification adaptive prediction circuit 105 and the computing unit 101. The image data d50 is taken out from the output terminal 110 as the output of the third hierarchy.
[0065]
Also, the class classification adaptive prediction circuit 105 performs class classification adaptive prediction on the second layer image data, and generates a predicted value d45 of the second layer data. The adder 97 adds the data d36 from the inverse quantizer 92 and the predicted value d45. The image data d41 is supplied from the adder 97 to the computing unit 101, the value of the non-transmission pixel is obtained by the computing unit 101, and all the pixel values of the second hierarchy are obtained from the image data d50 and the image data d41 supplied from the computing unit 102. Is restored. In this computing unit 101, all the restored pixel values are supplied as image data d49 to the class classification adaptive prediction circuit 104 and the computing unit 100. Further, the image data d49 is taken out from the output terminal 109 as the output of the second hierarchy.
[0066]
Further, the class classification adaptive prediction circuit 104 performs class classification adaptive prediction on the first layer image data, and generates a predicted value d44 of the first layer data. The adder 96 adds the data d35 from the inverse quantizer 91 and the predicted value d44. The image data d40 is supplied from the adder 96 to the computing unit 100, the value of the non-transmission pixel is obtained by the computing unit 100, and all the pixel values of the first layer are obtained from the image data d49 and the image data d40 supplied from the computing unit 101. Is restored. In this computing unit 100, all restored pixel values are taken out from the output terminal 108 as image data d48 as the output of the first layer. Each of the class classification adaptive prediction circuits 104, 105, 106, and 107 has the specific configuration shown in FIG. In this way, it is possible to improve coding efficiency by introducing class classification adaptive prediction in hierarchical coding in which an increase in the number of pixels to be coded is prevented.
[0067]
The variable length code decoders 86, 87, 88, 89, 90 and the inverse quantizers 91, 92, 93, 94, 95 have the same configuration as that of the decoding unit 134 of the above-described embodiment. Therefore, according to another embodiment in which the present invention is applied to the above-described hierarchical coding, as in the case of the above-described one embodiment, when the level range of the blocked residual signal satisfies a predetermined condition, The number of quantization bits can be reduced.
[0068]
Various methods for transmitting the mode signal MODE and the encoded residual signal generated in the present invention are possible. For example, the mode signals for one frame can be transmitted together and the encoded residual signal can be transmitted thereafter. Further, in the present invention, three or more quantization modes can be set. For example, considering not only the level range of the residual signal of the block but also its dynamic range DR, when the dynamic range DR is small, the third quantization mode having a smaller number of bits than the number of bits in the second quantization mode is obtained. It may be set. Furthermore, the quantization mode may be determined based on the level range of the quantization output of the first quantization mode.
[0069]
Furthermore, the present invention can be applied to quantization of a residual signal generated by predictive encoding other than the predictive encoding described above. The present invention can also be applied to a system having a buffering configuration for controlling the amount of generated data by controlling the quantization step width.
[0070]
【The invention's effect】
According to the present invention, it is possible to detect a case where the frequency distribution of the blocked residual signal does not cross 0, in which case the number of quantization bits can be further reduced and the amount of transmission data can be further reduced. it can.
[Brief description of the drawings]
FIG. 1 is a block diagram of an example of a recording / reproducing or transmission system to which the present invention can be applied.
FIG. 2 is a block diagram of an embodiment of the present invention.
FIG. 3 is a schematic diagram used for explaining generation of a residual signal and its blocking in one embodiment of the present invention.
FIG. 4 is a schematic diagram used for explaining quantization processing in one embodiment of the present invention;
FIG. 5 is a block diagram of an example of a quantization circuit in one embodiment of the present invention.
FIG. 6 is a schematic diagram used for explaining a bit plane in one embodiment of the present invention;
FIG. 7 is a block diagram of a decoding unit in one embodiment of the present invention.
FIG. 8 is a schematic diagram used to describe an example of hierarchical encoding.
FIG. 9 is a schematic diagram used to describe an example of hierarchical encoding.
FIG. 10 is a block diagram showing an example of a configuration on the encoding side of another embodiment in which the present invention is applied to hierarchical encoding.
FIG. 11 is a block diagram showing an example of a configuration on the decoding side according to another embodiment of the present invention.
FIG. 12 is a block diagram showing an example of the configuration of a class classification adaptive prediction circuit according to another embodiment of the present invention.
[Explanation of symbols]
2 ... Maximum value detection circuit, 3 ... Minimum value detection circuit, 5 ... Mode decision circuit
6 ... Quantization circuit

Claims (6)

In an information signal encoding apparatus for encoding an input digital information signal so as to reduce the amount of generated data,
Means for generating a residual signal between the input digital information signal and a predicted value of the input digital information signal ;
Means for blocking the residual signal;
Means for detecting the maximum and minimum values for each block;
It is determined from the maximum value and the minimum value whether or not the existence range of the residual signal for each block crosses 0, and when the existence range crosses 0, the first quantization mode is indicated and the presence Mode determining means for instructing the second quantization mode when the range does not cross 0;
In the first quantization mode, the residual signal is quantized with a predetermined number of bits less than the original number of bits, and in the second quantization mode, the residual is calculated with a number of bits less than the original number of bits. Quantization means adapted to quantize the signal and reduce the number of bits by code conversion;
Information identifying the first and second quantization modes;
An information signal encoding apparatus comprising transmission means for transmitting the output of the quantization means. In the information signal encoding device according to claim 1,
The mode determining means includes
An information signal encoding apparatus characterized by instructing a second quantization mode when the minimum value is 0 or more, or when the maximum value is 0 or less. In an information signal encoding method for encoding an input digital information signal so as to reduce the amount of generated data,
Generating a residual signal between the input digital information signal and a predicted value of the input digital information signal ;
Blocking the residual signal;
Detecting a maximum value and a minimum value for each of the blocks;
It is determined from the maximum value and the minimum value whether or not the existence range of the residual signal for each block crosses 0, and when the existence range crosses 0, the first quantization mode is indicated and the presence A mode determining step for indicating the second quantization mode when the range does not cross 0;
In the first quantization mode, the residual signal is quantized with a predetermined number of bits less than the original number of bits, and in the second quantization mode, the residual is calculated with a number of bits less than the original number of bits. Quantization of the signal, and a quantization step for reducing the number of bits by code conversion,
Information identifying the first and second quantization modes;
An information signal encoding method comprising the step of transmitting the output of the quantization means. In an information signal encoding apparatus for forming at least first and second layer data from an input digital information signal and encoding and transmitting the first and second layer data,
Means for forming the second hierarchical data having a lower resolution than the first hierarchical data;
Means for predicting the first hierarchical data from the second hierarchical data;
Means for forming a residual signal between the predicted data and the first hierarchical data;
Means for blocking the residual signal;
Means for detecting the maximum and minimum values for each block;
It is determined from the maximum value and the minimum value whether or not the existence range of the residual signal for each block crosses 0, and when the existence range crosses 0, the first quantization mode is indicated and the presence Mode determining means for instructing the second quantization mode when the range does not cross 0;
In the first quantization mode, the residual signal is quantized with a predetermined number of bits less than the original number of bits, and in the second quantization mode, the residual is calculated with a number of bits less than the original number of bits. Quantization means adapted to quantize the signal and reduce the number of bits by code conversion;
Information identifying the first and second quantization modes;
An information signal encoding apparatus comprising transmission means for transmitting the output of the quantization means. In an information signal encoding method for forming at least first and second layer data from an input digital information signal, and encoding and transmitting the first and second layer data,
Forming the second hierarchical data having a lower resolution than the first hierarchical data;
Predicting the first hierarchical data from the second hierarchical data;
Forming a residual signal between the predicted data and the first hierarchical data;
Blocking the residual signal;
Detecting a maximum value and a minimum value for each of the blocks;
It is determined from the maximum value and the minimum value whether or not the existence range of the residual signal for each block crosses 0, and when the existence range crosses 0, the first quantization mode is indicated and the presence A mode determining step for indicating the second quantization mode when the range does not cross 0;
In the first quantization mode, the residual signal is quantized with a predetermined number of bits less than the original number of bits, and in the second quantization mode, the residual is calculated with a number of bits less than the original number of bits. Quantization of the signal, and a quantization step for reducing the number of bits by code conversion,
Information identifying the first and second quantization modes;
An information signal encoding method comprising: a transmission step for transmitting the quantized output. A residual signal between an input digital information signal and a predicted value of the input digital information signal is generated, the residual signal is blocked, and a maximum value and a minimum value are detected for each block, and the maximum value and the minimum value are detected. It is determined from the value whether or not the existence range of the residual signal for each block crosses 0, and when the existence range crosses 0, the first quantization mode is indicated, and the existence range crosses 0. If not, the second quantization mode is instructed . In the first quantization mode, the residual signal is quantized with a smaller number of bits than the original number of bits, and in the second quantization mode, the residual is The signal is quantized with a smaller number of bits than the original number of bits and encoded to reduce the number of bits by code conversion, and information identifying the first and second quantization modes, and a residual Signal In the decoding method for the information signal encoding method in which the broadcast is transmitted,
Based on the identification information, in the first quantization mode, the data is inversely quantized, and in the second quantization mode, the data is transcoded and inversely quantized,
An information signal decoding method comprising the steps of: block-decomposing the inversely quantized residual signal and converting it to the original order.

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