JPH09102665A - Circuit board - Google Patents

Abstract

PROBLEM TO BE SOLVED: To judge the mounting condition of an electronic component without requiring labor and cost. SOLUTION: An GND electrode 11 to be connected with the GND pin 21 of an IC 2 mounted on a circuit board 1 is composed of split pads 11a and 11b. The split pad 11a is grounded, while the split pad 11b is connected with the power source Vcc of the IC 2 through a pull-up resistance R1 and is connected with a mounting judging output terminal 12. Thus, when the IC 2 is not mounted on the circuit board 1, the conduction is not provided between the split pads 11a and 11b, and 'HIGH' is outputted to the mounting judging output terminal 12 through the pull-up resistance R1 by a power source voltage Vcc. When the IC 2 is mounted on the circuit board 1, since the split pads 11a and 11b makes a continuity by the GND pin of the IC 2, the mounting judging output terminal 12 is connected with the ground, 'LOW' is outputted to the mounting judging output terminal 12, and the mounting condition of the electronic component such as IC is judged.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

TECHNICAL FIELD The present invention relates to a circuit board on which a plurality of electronic components are mounted.

[0002]

2. Description of the Related Art Usually, a circuit board used for a digital circuit or the like is provided with a plurality of mounting points. However, in practice, the same circuit board may have different circuit configurations. Depending on the configuration, I may be added to all mounting points.
It is used in a state where electronic components such as C are all mounted or only part thereof is mounted.

By the way, in such a circuit board,
When the circuit configuration is not fixed to one and there are multiple mounting states, conventionally, it has been decided whether to switch the switch etc. according to the mounting state of the electronic component or to directly access the electronic component to cause an error. The circuit configuration of the circuit board in which the electronic components are mounted is determined by the determination.

[0004]

However, the method of determining the circuit configuration on the circuit board by switching the switch according to the mounting state of the electronic component requires manpower for switching the switch, which is troublesome. At the same time, there is also a problem that a switch switching error may occur due to human intervention, and the mounted state of the electronic component cannot be reliably determined.

Further, in the method of directly accessing the electronic component, there is a problem that it takes time to wait for a so-called bus time-out, the time is wasted, and a bus-timeout detection circuit is required, resulting in cost increase. .

Therefore, the present invention has been made in view of such a problem, and it is possible to easily determine the circuit configuration on the circuit board in which the electronic components are mounted without manpower or cost. An object is to provide a circuit board.

[0007]

In order to achieve the above object, in the invention according to claim 1, in a circuit board on which an electronic component is mounted, when the electronic component is mounted, conduction is achieved by coupling pins of the electronic component. And a mounting discrimination output terminal connected to the mounting discrimination electrode, the circuit board comprising:

According to a second aspect of the present invention, in the circuit board according to the first aspect, the mounting discrimination electrodes are two electrodes which are electrically connected by the bonding of the GND pin of the electronic component when the electronic component is mounted. One electrode is grounded, while the other electrode is a GND electrode connected to a power source via a pull-up resistor, and the mounting discrimination output end is connected to the other electrode of the mounting discrimination electrode. It has been characterized.

According to a third aspect of the present invention, in the circuit board according to the first aspect, the mounting discrimination electrodes are two electrodes which are electrically connected by the connection of the power pins of the electronic component when the electronic component is mounted. One electrode is connected to a power source, the other electrode is a power electrode grounded via a pull-down resistor, and the mounting determination output end is connected to the other electrode of the mounting determination electrode. It is characterized by

According to a fourth aspect of the present invention, in the circuit board according to the first aspect, the second aspect, or the third aspect, the mounting discrimination electrode is composed of two electrodes provided around the pin insertion hole. Is characterized by.

According to a fifth aspect of the present invention, in the circuit board according to the first, second, third or fourth aspect of the present invention, the circuit board is connected to an output terminal for mounting determination, and the mounting determination is made by inputting a chip select signal. It is characterized by further comprising storage means for storing whether or not two electrodes of the mounting discrimination electrode are conducted based on the output of the output terminal for use.

According to a sixth aspect of the present invention, in the circuit board according to the first aspect, the second aspect, the third aspect, or the fourth aspect, it is connected to an output terminal for mounting determination and the mounting determination is performed by inputting a chip select signal. And a logical product means for outputting whether or not the two electrodes of the mounting discrimination electrode are conducted based on the output of the mounting output terminal.

According to a seventh aspect of the invention, in the circuit board according to the first, second, third, fourth, fifth or sixth aspect, the electronic components mounted are a plurality of ICs. And the mounting discrimination electrode is provided only on one IC of the above IC bank.
It is characterized by the following.

According to an eighth aspect of the invention, in the circuit board according to the first, second, third or fourth aspect, the electronic components to be mounted are a plurality of ICs each formed of a plurality of ICs. Each of the plurality of IC banks is provided with a mounting discrimination electrode and only in one IC of each IC bank. Each chip select signal input to each IC bank and each of the IC banks described above. It is characterized by further comprising: a determination unit that inputs the output of each mounting determination electrode and determines whether or not the IC is mounted in the IC bank corresponding to the input chip select signal.

According to a ninth aspect of the present invention, a plurality of electronic components are mounted on the circuit board according to the first, second, third or fourth circuit board, and each of the plurality of electronic components is mounted. A discrimination electrode and a mounting discrimination output terminal are provided, and a clock signal generating means for outputting a clock signal of a different frequency for each of the plurality of electronic components and a clock signal of a different frequency generated by the clock signal generating means are input. At the same time, the output from each of the mounting discrimination output ends of each of the plurality of electronic components is input, and the clock signals of different frequencies are synthesized based on the output from each of the mounting discrimination output ends to synthesize the plurality of electronic components. A signal synthesizing unit that outputs a signal corresponding to the mounting state of the component, and a determining unit that determines the mounting state of the plurality of electronic components based on the output signal from the signal synthesizing unit, Further characterized by comprising.

Therefore, in the inventions according to claims 1 to 9,
When the electronic component is not mounted, the two electrodes that form the mounting determination electrode do not conduct, while when the electronic component is mounted, the two electrodes that form the mounting determination electrode conduct, so It is possible to determine whether or not the electronic component is mounted by detecting whether or not the two electrodes of the determining electrode are electrically connected.

[0017]

DETAILED DESCRIPTION OF THE INVENTION First to seventh embodiments of a circuit board according to the present invention will be described below with reference to the drawings.

(1) First Embodiment FIG. 1 shows the configuration of a first embodiment of a circuit board according to the present invention.

The circuit board 1 of the first embodiment is composed of a printed wiring board (PWB) or the like, and as shown in the figure, the GND pin 21 of the IC 2 which is an electronic component mounted on the board 1 and The divided pads 11a and 1 electrically cut off the GND pad 11 which is the GND electrode to be connected.
It is characterized by being configured by 1b.

The split pad 11a is grounded to GND, while the split pad 11b is connected to a power source Vcc for supplying a driving current to the IC2 via a pull-up resistor R1 and the IC2 is mounted. It is connected to the mounting determination output terminal 12 used for determination.

2A and 2B, the GND of the IC 2 in the GND pad 11 of the circuit board 1 of the first embodiment is shown.
A method of joining the D pin 21 will be described.

In (a), the GND pin 21 of IC2 is grounded.
It shows a case where the D pad 11 is placed on both of the divided pads 11a and 11b and soldered at the solder points 21a and 21b. As a result, the division pad 11a and the division pad 11b are electrically connected via the GND pin 21 of the IC2.

(B) shows that the GND pin 21 of IC2 is
The divided pad 11a of the D pad 11, that is, the divided pad grounded as shown in FIG.
It shows a case where the solder bridge 3 is formed by solder in the slit between b and the split pad 11a and the split pad 11b are electrically connected via the solder bridge 3.

In the case of (b), GND of IC2
Since the pin 21 is bonded only to the split pad 11a,
As shown in the figure, a conventional GND pad may be used as the split pad 11a, and the split pad 11a may be provided with a short distance to newly provide the split pad 11b.

Next, the operation of this embodiment will be described with reference to the drawings.

First, as shown in FIG. 1, when the IC 2 is not yet mounted on the circuit board 1, the GND pin 21 of the IC 2 is not bonded on the GND pad 11, and the GND
Since the divided pads 11a and 11b forming the pad 11 are not conductive, "HIGH" is output to the mounting determination output terminal 12 by the power supply voltage Vcc via the pull-up resistor R1.

On the other hand, when the IC2 is mounted on the circuit board 1, that is, as shown in FIGS. 2A and 2B, the GND pin 21 of the IC2 is soldered to the GND pad 11 to be joined. In this case, since the division pads 11a and 11b forming the GND pad 11 are conductive, the mounting discrimination output end 12 is connected to GND, and the output of the mounting discrimination output end 12 becomes "LOW".

Therefore, according to the first embodiment, the mounting state of the IC 2 on the circuit board 1 can be determined only by checking the potential of the mounting determination output terminal 12.
It is not necessary to switch the switch or provide a bus timeout detection circuit as in the above-described conventional technique, and it is possible to easily determine the mounting state of the IC on the circuit board without manpower and cost.

(2) Second Embodiment Next, a second embodiment of the circuit board according to the present invention will be described.

Since the circuit board of the second embodiment has a structure in which the pins of the IC are joined through the pin (terminal) insertion holes, the divided pads constituting the GND pad 11 of the first embodiment shown in FIG. Since only the shapes of 11a and 11b are changed, the configurations of the circuit board and the GND pad different from those of the first embodiment will be illustrated and described.

FIGS. 3A and 3B show the main structure of the second embodiment of the circuit board according to the present invention.

(A) is a circuit board 1 of the second embodiment.
The pin pad hole 13 is formed in the circuit board 1, and the GND pin 21 of the IC 2 is inserted in the pin hole 13 and the divided pad constituting the GND pad 11 ′ by the solder 3. It shows a state of being joined to 11a 'and 11b'.

(B) is seen from the back side of the circuit board 1,
The shape of the division pads 11a 'and 11b' constituting the GND pad 11 'of the second embodiment is shown. Specifically, the division pads 11a' and 11b 'are divided into two and electrically cut. Pin insertion hole 1
3 indicates that they are arranged in the periphery.

Therefore, in the second embodiment, the first
Since only the shapes of the division pads 11a 'and 11b' constituting the GND pad 11 'are different from those of the embodiment, the division pads 11a' and 1b are similar to those of the first embodiment.
By the conduction and non-conduction of 1b ', it becomes possible to easily determine the mounting state of the IC on the circuit board 1 without manpower and cost.

(3) Third Embodiment Next, a third embodiment of the circuit board according to the present invention will be described.

FIG. 4 shows the configuration of the third embodiment of the circuit board according to the present invention.

The circuit board of the third embodiment differs from the first embodiment and the like shown in FIG. 1 in that the power supply pad 14 connected to the power supply pin 22 of the IC 2 mounted on the circuit board 1 is It is characterized in that it is composed of divided pads 14a and 14b similar to the GND pad 11 of the first embodiment.

The split pad 14a is connected to the power supply Vcc, while the split pad 14b is connected to GND via the pull-down resistor R2 and the mounting used for determining the mounting of the IC2. It is connected to the discrimination output terminal 12.

Next, the operation of the third embodiment will be described with reference to the drawings.

In this embodiment, unlike the first embodiment in which the potential of the GND pad 11 is output to the mounting discrimination output end 12, the potential of the power supply pad 14 is changed to the mounting discrimination output end 1.
Since the data is output to No. 2, the polarity of the output terminal 12 for mounting determination depending on whether or not the IC 2 is mounted is opposite to that of the first embodiment.

That is, as shown in FIG. 4, when the IC 2 is not yet mounted on the circuit board 1, the division pads 14a and 14b forming the power supply pad 14 are not conductive and a current from the power supply Vcc flows. Since there is no voltage drop in the pull-down resistor R2, the output terminal 1 for mounting determination is eliminated.
Since the potential of 2 becomes equal to the potential of GND, the output of the mounting determination output terminal 12 is "LOW", which is the reverse of the case of the first embodiment.

On the other hand, when the IC 2 is mounted on the circuit board 1, that is, the power supply pin 22 of the IC 2 is placed on the power supply pad 14, the same as in the first embodiment shown in FIG.
When soldering is performed as shown in (b), since the divided pads 14a and 14b forming the power supply pad 14 become conductive, a current flows through the pull-down resistor R2 and the potential of the mounting determination output end 12 rises, The output of the output terminal 12 for mounting discrimination is "HIGH", contrary to the case of the first embodiment.

Therefore, according to the third embodiment as well, as in the case of the first embodiment, only by checking the output of the output terminal 12 for mounting discrimination, it is possible to easily mount the IC without manpower and cost. It becomes possible to determine the state.

Also in this third embodiment, when the circuit board having the pin insertion holes is used, the power supply pad 1 is used.
The shape of No. 4 may be formed in a semicircular arc shape which is divided into two, like the GND pad 11 ′ of the second embodiment shown in FIG.

(4) Fourth Embodiment Next, a fourth embodiment of the circuit board according to the present invention will be described.

FIG. 5 shows the configuration of the fourth embodiment of the circuit board according to the present invention.

The fourth embodiment is the same as the first embodiment shown in FIG.
This is a modification of the embodiment, in which the power supply V of the GND pad 11 is
It is characterized in that the mounting discrimination output end 12 connected to the division pad 11b on the cc side is used as the data input end of the register (buffer) 15.

That is, the register 15 is connected to the division pad 11b on the power supply Vcc side of the GND pad 11 via the mounting discrimination output terminal 12 and mounted by the input of a chip select signal from a processor (not shown) or the like. Taking in the output of the discrimination output terminal 12, the potential of the division pad 11b is
Whether it is "LOW" or "HIGH", that is, whether the division pads 11a and 11b are conductive,
It is configured to store "0" and "1".

Next, the operation of the fourth embodiment will be described with reference to FIG.

First, in the fourth embodiment, the mounting discrimination output end 12 in the first embodiment shown in FIG.
Since it is only connected to the data input terminal 5 of FIG. 5, “HIGH” is output from the mounting determination output terminal 12 when the IC 2 is not mounted on the circuit board 1 as in the first embodiment.

At this time, when a chip select signal is input to the register 15 by the processor or the like, the register 15 outputs the output "HI" of the mounting determination output terminal 12.
GH ”is fetched and“ 1 ”indicating that the IC 2 is not mounted on the circuit board 1 is stored.

On the other hand, when the IC 2 is mounted on the circuit board 1, "LOW" is output from the mounting determination output terminal 12, and when a chip select signal is input to the register 15, the register 15 is The "LOW" is taken in and "0" indicating that the IC 2 is mounted on the circuit board 1 is stored.

Therefore, according to the fourth embodiment, just by accessing the register 15, as in the first embodiment, the mounting state of the IC on the circuit board can be easily performed without manpower and cost. It becomes possible to determine.

The fourth embodiment has been described by connecting the mounting determination output end 12 of the first embodiment to the input end of the register 15. However, the present invention is not limited to this, and the second embodiment is not limited to this. The mounting determination output end of the embodiment or the third embodiment may be connected to the input end of the register 15.

(5) Fifth Embodiment Next, a fifth embodiment of the circuit board according to the present invention will be described.

FIG. 6 shows the configuration of the fifth embodiment of the circuit board according to the present invention.

In the fifth embodiment, the ICs mounted on the circuit board 1 are a plurality of IC memories 16a to 16d (four in the present embodiment for convenience) constituting the memory bank 16 which is an IC bank. It is characterized in that it can be easily and inexpensively determined whether or not the IC memories 16a to 16d are mounted in the memory bank 16.

That is, in the fifth embodiment, each of the IC memories 16a to 16d forming the memory bank 16 is not provided with the GND pad or the power supply pad formed of the divided pads according to the first to fourth embodiments. , One of the IC memories 16a to 16d forming the memory bank 16,
That is, in this embodiment, as shown in FIG.
It is characterized in that a GND pad (not shown) to which the GND pin 16d1 of d is connected is provided with a GND pad composed of the division pads of the first to second embodiments.

As in the first embodiment shown in FIG. 1 and the like, one of the divided pads forming the GND pad is grounded, while the other divided pad is connected to the power supply Vcc and the AND circuit is formed. It is connected to the first input terminal 17 a of the terminal 17.

The second input terminal 17b of the AND circuit 17
Includes a memory bank 16 from a processor or the like (not shown).
It is connected so that a chip select signal which is an output enable signal for operating the memory bank 16 which is transmitted to the memory bank 16 is input.

Next, the operation of the fifth embodiment will be described.

First, in the memory bank 16, the IC memory 16
If d is not mounted, the other IC memories 16a to
Since c is not mounted and the memory bank 16 is not used, the divided pad of the GND pad to which the GND pin 16d1 of the IC memory 16d is to be connected is shown as in the case of the first embodiment. Does not conduct, and "HIGH" is input to the first input terminal 17a of the AND circuit 17 by the power supply Vcc.

On the other hand, when the IC memory 16d is mounted on the memory bank 16, the other IC memories 16a to
Since c is also mounted and the memory bank 16 is used, as in the case of the first embodiment, etc.,
G to which the GND pin 16d1 of the IC memory 16d is connected
The divided pad of the ND pad becomes conductive, the first input terminal 17a of the AND circuit 17 becomes the same potential as the GND pin 16d1, and "LOW" is input.

Therefore, when the processor or the like outputs the chip select signal to the memory bank 16 in order to access the memory bank 16, the chip select signal is also input to the second input terminal 17b of the AND circuit 17 and ""HIGH". Therefore, when the memory bank 16 is not used, "HIGH" of the second input terminal 17b.
And "HIGH" which is the logical product of "HIGH" of the first input terminal 17a is output from the output terminal 17c, and the IC memories 16a to 16d are not mounted in the memory bank 16.
"HIGH" is output as an output indicating that the memory bank 16 is not used.

On the other hand, when the memory bank 16 is used, "LO" which is the logical product of "HIGH" of the second input terminal 17b and "LOW" of the first input terminal 17a.
W ″ is output from the output terminal 17c and the memory bank 16
"LOW" is output as an output indicating that the IC banks 16a to 16d are mounted on the memory bank 16 and the memory bank 16 is used.

Therefore, according to the fifth embodiment, the mounted state of the IC memories 16a to 16d forming the memory bank 16 is output from the AND circuit 17 only by transmitting the chip select signal to the memory bank 16 to access the memory bank 16. Therefore, the IC memories 16a to 16a that constitute the memory bank 16 on the circuit board 1 can be easily formed without requiring manpower and cost.
Since it is possible to determine the mounting state of the 16d and it is not necessary to provide a GND pad composed of divided pads or an AND circuit for each of the IC memories 16a to 16d forming the memory bank, the cost is reduced in this respect as well.

Although the fifth embodiment has been described as having the above-mentioned structure, the present invention is different from the fifth embodiment in that the GND having the shape of the second embodiment shown in FIG. 3 is used.
The pads may be used, or the power supply pad may be composed of divided pads instead of the GND pad as in the third embodiment shown in FIG. 4, and further, it may be an IC bank other than the IC memory. Alternatively, the register of the fourth embodiment may be provided instead of the AND circuit 17.

(6) Sixth Embodiment Next, a sixth embodiment of the circuit board according to the present invention will be described.

FIG. 7 shows a schematic structure of a sixth embodiment of the circuit board according to the present invention.

In the sixth embodiment, as in the fifth embodiment, a plurality of memory banks A18 and B1 each including a plurality of IC memories (two in this embodiment are used for convenience).
The circuit configuration of the circuit board described in the third embodiment is adopted as one of the IC memories each having 9 and configuring each of the two memory banks A18 and B19.

The power supply pad outputs of the memory banks A18 and B19, and the memory banks A18 and B19.
Low active type chip select signal A input to
B is input to the error discrimination circuit 20 and the error discrimination circuit 20
To output an error signal for each of the memory banks A18 and B19.

FIG. 8 shows the memory banks A18 and B19 and the error discrimination circuit 20 of the sixth embodiment of the circuit board shown in FIG.
An example of the internal configuration of is shown.

First, the structure of the memory banks A18 and B19 will be described. The power supply pads 18a and 19a to which the power supply pins (not shown) of any one IC memory forming the memory banks A18 and B19 are connected will be described. Similar to the third embodiment shown in FIG. 4, it is characterized in that it is composed of divided pads 18a1, 18a2, 19a1 and 19a2 connected to the power source Vcc and GND.

The error discrimination circuit 20 includes OR gates 20a and 20b of negative logic on the input / output side and an AND gate 20.
c and 20d, and a three-state buffer 20e having negative logic on the input / output side and negative logic on the control input side.

The OR gate 20a is connected so as to input the low active chip select signals A and B and to input its output to the three-state buffer 20e, while the AND gates 20c and 20d are respectively connected.
The chip select signals A and B and the memory bank A1
The outputs of the power supply pads 18a and 19a of B8 and B19 are input and the outputs thereof are connected to the OR gate 20b. And three-state buffer 2
0e inputs the output of the OR gate 20a, and
The output of the R gate 20b is used as a control input to output an error only when an IC memory is not mounted in each of the memory banks A18 and B19. This output is shared with other devices on the board and is a signal used to indicate the occurrence of an error on the entire board.

The output of the three-state buffer 20e is connected to the power supply VCC through the pull-up resistor 20f.

Next, the operation of the sixth embodiment thus constructed will be described with reference to FIG.

For example, even one IC in the memory bank A18
If the memory is not mounted, the power supply pad 18a
Output becomes "LOW" as described in the third embodiment, on the other hand, when the memory bank A18 is accessed by the processor or the like in this state, the low active chip select signal A becomes "LOW". Is output.

Then, since "LOW" is inputted to both input terminals of the AND gate 20c of the error discrimination circuit 20,
The three-state buffer 20e of the error determination circuit 20 outputs "LOW" as an error signal indicating that the IC memory is not mounted in the memory bank A18. That is, when no IC memory is mounted in the memory bank A18, the three-state buffer 2
0e is driven, the error signal "LOW" is output, and the memory access ends in error.

On the other hand, when all the IC memories are mounted in the memory bank A18, the output of the power supply pad 18a is "HIGH" as described in the third embodiment.
Meanwhile, in this state, when the memory bank A18 is accessed by the processor or the like and "LOW" is output to the chip select signal A in this state, the three-state buffer 20 of the error determination circuit 20 is pulled up by pull-up.
From "e", "HIGH" is output as an output indicating that all the IC memories are mounted in the memory bank A18.
That is, when all the IC memories are mounted in the memory bank A18, the three-state buffer 20e is not driven, and the access ends normally.

As in the case of the memory bank A18 described above, it is possible to determine the mounted state of the IC memory for the memory bank B19.

Therefore, according to the sixth embodiment, even when a plurality of memory banks are formed on the circuit board, it is possible to access the memory banks by sending a chip select signal and accessing the memory banks. Since the mounting state of the IC memory forming the memory bank is output, the mounting state of the IC memory forming each memory bank can be easily determined without manpower or cost.

Further, according to the sixth embodiment, the procedure of making an access beforehand and making a determination is omitted, and an illegal access countermeasure can be taken by generating an error each time a memory bank which is not mounted is accessed. .

Although the sixth embodiment has been described as having the above-described configuration, the present invention is different from the sixth embodiment in that the GND having the shape of the second embodiment shown in FIG. 3 is used.
The pads may be used, or the power supply pad may be composed of divided pads instead of the GND pad as in the third embodiment shown in FIG. 4, and further, a plurality of ICs other than the IC memory may be used. You may make it comprise an IC bank. Further, not only the memory but also other ICs can be used.

(7) Seventh Embodiment Next, a seventh embodiment of the circuit board according to the present invention will be described.

FIG. 9 shows the configuration of the seventh embodiment of the circuit board according to the present invention.

In the seventh embodiment, a clock signal having a different frequency is assigned to each of a plurality of ICs 41 to 44 (in this embodiment, four ICs are used for convenience) on the circuit board 1 and the ICs 41 to 44 are mounted. Depending on the state, the corresponding clock signals are combined and output,
Based on the waveform of the synthesized signal of each clock signal, the IC 41-
The mounting state of 44 is determined.

Specifically, a system clock generating circuit 31 for generating a system clock having a frequency f, and a frequency dividing circuit 3 for frequency-dividing the system clock by 2, 4, and 8 and outputting the frequency-divided circuit 3.
2 and the GND pads 41a to 44 of the ICs 41 to 44, which are composed of the split pads described in the first and second embodiments.
a plurality of GND pads to which each a is connected (not shown)
And the output of each GND pad as a control input, the system clock output from the system clock generating circuit 31 and each clock signal output from the frequency dividing circuit 32 as an input, and the output terminals are opened. A clock signal synthesizing circuit 33 composed of control input inversion type three-state buffers 33a to 33d connected by collectors and synthesizing and outputting by a logical product of clock signals as described later, and an output of the clock signal synthesizing circuit 33. And an error discriminating circuit 34 for discriminating an error.

FIG. 10 shows an example of the internal configuration of the frequency dividing circuit 32 shown in FIG.

As shown in the figure, the frequency dividing circuit 32 further includes three D-FFs 32a which further invert the inverted output to obtain the D input.
32 to 32c, the clock signal of frequency f output from the system clock generation circuit 31 is set to 2, 4, 8
The frequency division is performed to output clock signals of frequencies f / 2, f / 4, f / 8.

That is, the D-FF 32a divides the system clock of the frequency f output from the system clock generation circuit 31 into two and outputs a clock signal of the frequency f / 2, and the D-FF 32b outputs from the D-FF 32a. The output clock signal of frequency f / 2 is further divided by two to output a clock signal of frequency f / 4, and the D-FF 32c outputs D
The clock signal of frequency f / 4 output from the -FF 32b is further divided into two to output a clock signal of frequency f / 8.

11 (a) to 11 (p) show the waveform of the signal output from the clock signal synthesis circuit 33 and input to the error discrimination circuit 34 in the seventh embodiment, the discrimination method in the error discrimination circuit 34, and the like. Show.

In this figure, the signal 1 means the system clock of the frequency f which is the output of the three-state buffer 33a, and the signal 2 of the frequency f / 2 which is the output of the three-state buffer 33b. The clock signal is the signal 3 and is the three-state buffer 33c.
The clock signal of frequency f / 4, which is the output of the above, and the signal 4 is the clock signal of frequency f / 8, which is the output of the three-state buffer 33d.

First, in the figure, the output waveforms of the signals 1 to 4 shown in (a) to (d) are output waveforms of only the signals 1 to 4, that is, when only one IC 41 to 44 is mounted. The waveforms output from the clock signal synthesizing circuit 33 are shown. The system clock of the frequency f output by the system clock generating circuit 31 and the frequencies f / 2, f / 4, f / 8 output by the frequency dividing circuit 32 are shown. It becomes the clock signal of.

The output waveform of the signal 1 + 2 + 3 + 4 shown in (e) is the output waveform from the clock signal synthesizing circuit 33 when all the ICs 41 to 44 are mounted.
The output waveform of the signal 1 + 2 + 3 shown in (f) is the IC 41, 42, 4
It is an output waveform from the clock signal synthesis circuit 33 when only 3 is mounted, and is an output waveform obtained by ANDing the signals 1, 2, and 3.

The output waveforms of the signals shown in (g) to (n) below are the output waveforms from the clock signal synthesizing circuit 33 when only the ICs corresponding to the signals are mounted, as described above. (O) is an output waveform from the clock signal synthesis circuit 33 when only the ICs 43 and 44 are mounted.

Next, (p) shows the sampling timing of the signals of the waveforms shown in (a) to (o) in the error discrimination circuit 34, that is, the sampling timing of the output signal from the clock signal synthesis circuit 33, and (a). It indicates that the output signal from the clock signal synthesizing circuit 33 having the waveforms shown in (a) to (o) is sampled at the sampling frequency 2f which is twice the frequency f of the signal shown in FIG.

The error discriminating circuit 34 converts the sampled 16-bit data into binary-hexadecimal number and represents it by 4 bits. The output signal from the clock signal synthesizing circuit 33 shown in (a) to (o) is used. The binary-to-hexadecimal converted data is the data shown in (q) after the arrow of the output signal shown in each of (a) to (o).

Specifically, as shown in (q), (a)
In the case of the signal of, "AAAA" is sampled,
The signal of (b) is sampled as "CCCC", the signal of (c) is sampled as "F0F0", and the signals of (d) to (o) are sampled as shown in the figure.

Therefore, in the error discrimination circuit 34,
It is stored in advance as a table which signal of the output signals from the clock signal synthesis circuit 33 shown in (a) to (o) corresponds to each data shown in (q). When the output signal is input, sampling is performed at the timing shown in (p), the sampling data is referred to in the table, and the output signal from the clock signal synthesis circuit 33 has any pattern shown in (a) to (o). Is determined, and the determination result is output.

Next, the operation of the seventh embodiment will be described.

First, as shown in FIG.
When all are implemented, the control input inversion type three-state buffers 33a to 33d are supplied with "L" through the respective GND pads as in the case of the first embodiment.
OW ”is input and the outputs of the buffers 33a to 33d are released, so that the signal 1
A signal having a waveform shown in (e), which is the logical product of + 2 + 3 + 4, is output and input to the error determination circuit 34.

In the error discrimination circuit 34, (p) of FIG.
The input signal from the clock signal synthesizing circuit 33 is sampled at the timing shown in, and the data "8000" is taken out.
Can be determined to be the case where all are entered.
1 to 44 are all mounted. A normal signal such as "is output.

Further, in FIG. 9, when, for example, only the IC 42 is not mounted, the signal having the waveform shown in (h) is output from the clock signal synthesis circuit 33, input to the error determination circuit 34, and similarly sampled. However, in this case, the sampling data becomes "A000", and the error discrimination circuit 34 can discriminate that the signal 1 + 3 + 4 shown in (h) is input, so that "IC42 is not mounted". Output an error signal.

Therefore, according to the seventh embodiment, even when a plurality of ICs are mounted on the circuit board, the system clock is divided to allocate clock signals of different frequencies to each IC, and Each clock signal is output and combined depending on whether it is mounted or not, and it is possible to determine the mounting state of the IC on the circuit board by the combined waveform, so it requires manpower and cost without accessing each IC. The mounting state of the IC can be easily determined without the need.

Although the seventh embodiment has been described as having the above-mentioned configuration, the present invention is different from the seventh embodiment in that the GND of the shape of the second embodiment shown in FIG. 3 is used.
Alternatively, the pads may be used, or the power supply pad may be composed of divided pads instead of the GND pad as in the third embodiment shown in FIG.

[0107]

As described above, according to the present invention, the GN
The D electrode or the power electrode is composed of two divided electrodes, and I
When an electronic component such as C is not mounted, the two electrodes do not conduct, while when an electronic component is mounted,
Since the two electrodes are configured to be conductive, it is possible to determine whether or not the electronic component is mounted by detecting whether or not the two electrodes of the mounting determination electrodes are conductive. As described above, it is not necessary to switch the switch or provide the bus timeout detection circuit, and it is possible to easily determine the mounting state of the electronic component on the circuit board without manpower and cost.

[Brief description of the drawings]

FIG. 1 is an explanatory diagram showing a configuration of a first embodiment of a circuit board according to the present invention.

FIG. 2A and FIG. 2B are explanatory views showing a method of joining GND pins of an IC in a GND pad of the circuit board of the first embodiment, respectively.

3 (a) and 3 (b) are explanatory views each showing a configuration of a main part sentence of the second embodiment of the circuit board according to the present invention.

FIG. 4 is an explanatory diagram showing a configuration of a third embodiment of a circuit board according to the present invention.

FIG. 5 is an explanatory diagram showing a configuration of a fourth embodiment of a circuit board according to the present invention.

FIG. 6 is an explanatory diagram showing a configuration of a fifth embodiment of a circuit board according to the present invention.

FIG. 7 is an explanatory diagram showing a schematic configuration of a sixth embodiment of a circuit board according to the present invention.

8 is an explanatory diagram showing an internal configuration of a memory bank and an error determination circuit of a sixth embodiment of the circuit board shown in FIG. 7.

FIG. 9 is an explanatory diagram showing a configuration of a seventh embodiment of a circuit board according to the present invention.

FIG. 10 is an explanatory diagram showing an internal configuration of a frequency dividing circuit.

11A to 11Q are explanatory diagrams showing waveforms of signals input to the error determination circuit in the seventh embodiment, a determination method in the error determination circuit, and the like.

[Explanation of symbols]

 1 circuit board 2 IC (electronic component) 11 GND pad (GND electrode) 11a, 11b split pad (split electrode) 11a ', 11b' split pad (split electrode) 12 output terminal for mounting determination 13 pin insertion hole 14 power supply pad ( Power supply electrode) 14a, 14b Divided pad (divided electrode) 15 Register (storage means) 16 Memory bank (IC bank) 16a to 16d IC memory 17 AND circuit (logical product means) 18, 19 Memory bank 18a, 19a Power supply pad (power supply) Electrodes 18a1 and 18a2 Divided pads (divided electrodes) 19a1 and 19a2 Divided pads (divided electrodes) 20 Error determination circuit (determination means) 21 GND pin 22 Power supply pin 31 System generation circuit (clock signal generation means) 32 Dividing circuit (clock) Signal generating means) 33 Clock signal synthesizing circuit (signal Forming means) 34 error determination circuit (determination means) 41 to 44 IC (electronic component) 41 a to 44 GND pin

Claims (9)

[Claims] 1. A circuit board on which an electronic component is mounted, wherein the mounting discrimination electrode is formed of two electrodes that conduct when the electronic component is mounted by connecting pins of the electronic component, and the mounting discrimination electrode is connected. A circuit board, comprising: 2. The mounting discrimination electrode is two electrodes that conduct when the electronic component is mounted by the connection of the GND pin of the electronic component, and one electrode is grounded while the other electrode is grounded. Is a GND electrode connected to a power source via a pull-up resistor, and an output terminal for mounting discrimination is connected to the other electrode of the mounting discrimination electrode, The circuit according to claim 1, substrate. 3. The mounting discrimination electrode is two electrodes that are electrically connected to each other when a power supply pin of the electronic component is mounted when the electronic component is mounted, and one electrode is connected to a power source while the other electrode is connected to the power source. 2. The circuit board according to claim 1, wherein the electrode is a power supply electrode grounded via a pull-down resistor, and the mounting discrimination output end is connected to the other electrode of the mounting discrimination electrode. . 4. The circuit board according to claim 1, wherein the mounting discrimination electrode is composed of two electrodes provided around the pin insertion hole. 5. Storage means connected to the mounting discrimination output end, for storing whether or not two electrodes of the mounting discrimination electrode are conducted based on the output of the mounting discrimination output end by the input of a chip select signal, The circuit board according to claim 1, claim 2, claim 3, or claim 4, further comprising: 6. A logical product means that is connected to an output terminal for mounting discrimination and outputs whether or not two electrodes of the electrode for mounting discrimination are conducted based on the output of the output terminal for mounting discrimination according to the input of a chip select signal. The circuit board according to claim 1, claim 2, claim 3, or claim 4, further comprising: 7. The electronic component to be mounted is an IC bank composed of a plurality of ICs, and the mounting discrimination electrode is provided only on one IC of the IC bank. The circuit board according to claim 2, claim 3, claim 4, claim 5, or claim 6. 8. The mounted electronic component is a plurality of IC banks each composed of a plurality of ICs, and a mounting discrimination electrode is provided for each of the plurality of IC banks and one IC of each IC bank. The chip select signal input to each IC bank and the output of each mounting discrimination electrode of each IC bank are input, and the IC is mounted on the IC bank corresponding to the input chip select signal. The circuit board according to claim 1, claim 2, claim 3, or claim 4, further comprising: a determining unit that determines whether or not the circuit board is present. 9. A plurality of electronic components are mounted, a mounting discrimination electrode and a mounting discrimination output end are provided for each of the plurality of electronic components, and a clock signal of a different frequency is output for each of the plurality of electronic components. And a clock signal of different frequency generated by the clock signal generating means, and the outputs from the mounting discrimination output terminals of each of the plurality of electronic components are input to each of the mounting parts. Based on the output signal from the signal synthesizing means for synthesizing the clock signals of the different frequencies based on the output from the discrimination output end and outputting a signal corresponding to the mounting state of the plurality of electronic components, 5. The circuit board according to claim 1, further comprising: a determining unit that determines a mounting state of the plurality of electronic components. .