JPH09101545A - Liquid crystal display device and its production - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a liquid crystal display device with which the yield in production stages is high and an opening rate is sufficiently assured and a process for producing the same. SOLUTION: This liquid crystal display device is improved in its yield by forming inorg. protective films 17 which are the structural parts of thin-film transistors (TFTs) 12 formed on a first substrate 11 in a self-aligning manner by back surface exposure utilizing gate electrodes 13 to lower the parasitic capacitance of the TFTs 12 and eventually to decrease the width (area) of corresponding storage capacitor electrodes 14, thereby assuring the spacings of the regions where scanning lines 13 and the storage capacitor electrodes 14 are in proximity without decreasing the opening rate.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to, for example, an active matrix type liquid crystal display device using a thin film transistor as an active element, and more particularly to an array substrate and a structure and manufacturing method of the display device.

[0002]

2. Description of the Related Art As a display device using liquid crystal, a large capacity for television display or graphics play, etc.
The development and practical application of high-density active matrix type liquid crystal display devices have been brisk.

In such a display device, a semiconductor switch is used for driving and controlling each pixel so that high-contrast display without crosstalk can be performed. As the semiconductor switch, a thin film transistor formed on a transparent insulating substrate is used because it can be used for transmissive display and can be easily enlarged. Among them, an amorphous silicon thin film transistor using amorphous silicon as a material of the thin film transistor is currently the mainstream because of the reason that the substrate area can be increased and a low temperature process can be used in the manufacturing process.

The structure of an amorphous silicon thin film transistor is roughly classified into a coplanar type and a staggered type depending on the relative positional relationship between the gate electrode, the semiconductor thin film layer, the source and the drain electrode. Note that in the case of an amorphous silicon thin film transistor formed over an insulating substrate, a staggered type, which has many effective surfaces in a manufacturing process, is often used. Above all, a gate electrode, a gate insulating film layer, and an amorphous layer are formed over the insulating substrate. Silicon thin film,
An inverted staggered type structure having a structure in which a low resistance semiconductor layer, a source and a drain electrode are formed in this order is common.

As a structure of an inverted staggered amorphous silicon thin film transistor, as shown in FIGS. 4 and 6, a scanning line (row selection) formed on one surface of a supporting glass (insulating substrate) 111 of an array substrate 110. Line) 112, an amorphous silicon thin film 115 for forming the amorphous silicon thin film transistor 114, for example, an inorganic protective film 116 made of silicon nitride and a low resistance semiconductor layer 117 are sequentially stacked on the insulating layer 113 to cover the insulating layer 113. Before forming the resistive semiconductor layer 117,
A method has been proposed in which the workability of the low-resistance semiconductor layer 117 is improved by processing the inorganic protective film 116 into a predetermined shape. In the active matrix type liquid crystal display device shown in FIGS. 4 and 5, the array substrate 110 and the counter substrate 120 (support glass (insulating substrate) 121, the light shielding film 122, the coloring layer 123, and the counter electrode 124 are sequentially arranged. Alignment films 118 and 125 provided with a predetermined alignment direction by rubbing are formed on the side facing the respective liquid crystal composition 130 (formed by forming) so as to deviate the alignment direction by 90 °. This is a twisted nematic liquid crystal display device in which substrates 120 are opposed to each other substantially in parallel, and a nematic liquid crystal composition 130 is sealed between the substrates.

By the way, the array substrate 110 of the active matrix type liquid crystal display device shown in FIGS.
A well-known storage capacitor electrode 141 for compensating for the capacitance characteristic of the amorphous silicon thin film transistor 114 is arranged in the.

Since the storage capacitor electrode 141 is generally formed in the same layer as the scanning line 112 by the same metal material as the gate electrode, in order to avoid an undesired short circuit with the pixel electrode 140, It is arranged at a position apart from the pixel electrode 140 so as to cross the pixel electrode 140.

However, according to this method, the storage capacitor electrode 141 is provided in a region where the orientation of the liquid crystal composition is changed in the range covered by the pixel electrode 140, that is, in the opening which is restricted by the light shielding film 122 formed on the counter substrate 129. Therefore, the aperture ratio is lowered.

For this reason, there has been proposed a method of forming the storage capacitor electrode 141 with a material different from that of the scanning line or a different layer. However, both methods increase the number of steps and the number of steps. It is known that the yield decreases due to the occurrence of defects and the like.

[0010]

Therefore, as shown in FIG. 7, a method has been proposed in which the storage capacitor electrode 141 is formed around the pixel electrode 140, that is, in the non-opening region. According to this method, when the liquid crystal display device 100 is configured by arranging the peripheral portion of the light shielding film 122 of the counter substrate 120 in parallel with the array substrate 110 and the counter substrate 120, the assembling accuracy of the array substrate 110 and the counter substrate 120 is high. It uses the fact that it overhangs the inside of the pixel electrode 140 by the amount of
It is possible to minimize the decrease in the aperture ratio due to the formation of the storage capacitor electrode 141.

At this time, as shown in FIG.
By providing 2 with a structure that also serves as the storage capacitor electrode 141, the aperture ratio can be further improved. However, in this method, for example, as shown in FIG. 7, in order to secure the capacitance required as the storage capacitor electrode 141, the region where the storage capacitor electrode 141, that is, the scanning line 112 is expanded, is formed substantially in the pixel electrode 140. It needs to be formed all around.

In this case, the storage capacitor electrode 141 must be formed in a region corresponding to the assembly margin between the array substrate 110 and the counter substrate 120 (generally, 5 to 10 μm is secured), which is hatched in FIG. Therefore, the distance between the storage capacitor electrode 141 and the scanning line 112 or the distance between the storage capacitor electrode 141 and the gate electrode becomes very narrow, which causes a problem such as a short circuit between both electrodes. An object of the present invention is to provide a liquid crystal display device which has a high yield in the manufacturing process and has a sufficient and sufficient aperture ratio, and a manufacturing method thereof.

[0013]

The present invention has been made based on the above-described problems, and a plurality of scanning lines and signal lines formed on an insulating substrate intersect with each other, and the scanning lines and the signal lines intersect with each other. A pixel electrode disposed in a region, a gate connected to the scanning line, a drain connected to the signal line, a source connected to the pixel electrode, and a drain disposed between the drain and the source. And a thin film transistor having an overlapping portion with a source and having a protective film formed in a self-aligned manner with respect to the gate, and the pixel electrode and the thin film transistor which are overlapped via an interlayer insulating film to form a storage capacitor. An active matrix substrate including a capacitance electrode, wherein the pixel electrode includes a storage capacitance electrode that overlaps with the storage capacitance electrode and an effective region other than the storage capacitance electrode;
The liquid crystal display device is characterized in that the storage capacitor region is formed at an end portion of the pixel electrode parallel to the signal line, and the effective region is disposed between storage capacitor regions separated from each other. To do.

Further, according to the present invention, a plurality of scanning lines and signal lines formed on the insulating substrate, a pixel electrode arranged in an area where the scanning lines and the signal lines intersect, and the scanning lines are connected. The gate, the drain connected to the signal line, the source connected to the pixel electrode, and the drain and the source overlapped with each other. And a thin film transistor having a protective film shaped in a self-aligning manner,
A method of manufacturing a liquid crystal display device, comprising: an active matrix substrate that includes a storage capacitor electrode that overlaps with the pixel electrode via an interlayer insulating film and that forms a storage capacitor. A method of manufacturing a liquid crystal display device is provided, which is characterized in that the storage capacitor electrode is formed in a self-aligning manner with respect to an electrode, and the storage capacitor electrode is formed in a portion along an outer peripheral portion of the pixel electrode along the signal line.

As described above, according to the liquid crystal display device of the present invention, the protective film in the thin film transistor is shaped in a self-aligned manner with respect to the gate electrode to reduce the required storage capacity by half, and Since the storage capacitor electrode is formed on the outer peripheral portion of the pixel electrode along the signal line, the aperture ratio can be significantly increased.

Further, since the storage capacitor electrode is formed only in the portion along the signal line, it is possible to increase the distance between the storage capacitor electrode and the scanning line and between the gate electrode and the storage capacitor electrode.
Problems such as a short circuit between both electrodes in the manufacturing process are reduced.

Further, the storage capacitor electrode is formed in a portion along the signal line in a predetermined shape that ensures a sufficient space between the storage capacitor electrode and the scanning line and between the gate electrode and the storage capacitor electrode. Therefore, problems such as a short circuit between both electrodes are eliminated in the manufacturing process, and the manufacturing yield of the array substrate is improved.

[0018]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings. 1 and 2 respectively,
FIG. 1 is an enlarged partial plan view and partially expanded cross-sectional view of a pixel portion of an active matrix type liquid crystal display device to which a first embodiment of the present invention is applied.

Referring to FIGS. 1 and 2, the liquid crystal display device 1 includes, for example, a first substrate, ie, an array substrate 10, on which a plurality of amorphous silicon thin film transistors as active elements are integrally formed, and this array. The counter substrate 30 is opposed to the substrate 10 at a predetermined interval substantially in parallel with the array substrate, and the liquid crystal composition 50 is interposed between the array substrate 10 and the counter substrate 30.

The array substrate 10 has an insulating substrate (support glass) 11 formed of a transparent material such as glass. On one surface of the insulating substrate 11, a scanning line (row selection line) formed integrally with the gate electrode of the amorphous silicon thin film transistor 12, that is, an electrode made of metal or semiconductor corresponding to the gate electrode 13 and the storage capacitor electrode 14 is formed. A part is formed. Note that, hereinafter, the respective electrode portions will be referred to as a scanning line (gate electrode) 13 and a storage capacitor electrode 14.
Is shown. Each of the scanning line 13 and the storage capacitor electrode 14 is formed of, for example, Al (aluminum), Ti (titanium), Cr (chrome), Mo (molybdenum), Ta.
It is provided by a single layer or a laminated layer of a metal material such as (tantalum) or W (tungsten) or its alloy. When the scanning line 13 and the storage capacitor electrode 14 are shaped, they can be used in a technique such as a taper etching technique in which an etching cross section is inclined.

Here, as shown in FIG. 1, the storage capacitor electrode 14 connected to the scan line 13 of the n−1 stage is formed on the periphery of the pixel region of the n stage, which will be described later, which is formed in the subsequent process. It is arranged along and around the pixel region of n stages. In this case, the storage capacitor electrode 1 connected to the (n-1) th scanning line 13
4 is arranged apart from the scanning line 13 of n stages by a predetermined distance.

Further, the closest spacing between the (n-1) th stage storage capacitor electrode 14 and the nth stage scanning line 13 is, for example, 40 microns (hereinafter referred to as 40 .mu.m). The storage capacitor electrode 14 is formed around the pixel electrode described later along the signal line (column electrode) described later. In this case, the storage capacitor electrode 14 is arranged at a position defined so that the pixel electrode, which will be described later, is not covered with the light-shielding film (described later) provided on the counter substrate 30 in the pixel electrode, that is, the display region. To be done.

Above the scanning line 13 and the storage capacitor electrode 14, that is, on the side facing the liquid crystal composition 50 when the array substrate 10 is assembled with the counter substrate 30, the scanning line 13 and the storage line 13 are made of, for example, silicon nitride. An insulating layer (gate insulating film) 15 that covers each of the capacitance electrodes 14 is formed.

Above the insulating layer (gate insulating film) 15,
The amorphous silicon thin film 16 and the inorganic protective film 17 are sequentially stacked. In addition, for the inorganic protective film 17, for example, silicon nitride or the like is preferable. Insulating layer (gate insulating film) 1
5, the laminated film including the amorphous silicon thin film 16 and the inorganic protective film 17 is formed by, for example, any one of the plasma CVD method, the atmospheric pressure CVD method and the low pressure CVD method. In this case, the thickness of each layer is, for example, 40
It is defined as 0 nm, 50 nm and 200 nm. Here, an example in which each layer of the laminated film is made of a single material and a single layer film is shown, but for example, each layer may be made of a laminated film made of different materials.

Inorganic protective film 17 and amorphous silicon thin film 16
Above the above, the whole area of the amorphous silicon thin film 16 and the inorganic protective film 1
A low-resistance semiconductor layer 18 is arranged so as to cover a part of 7. As the low-resistance semiconductor layer 18, amorphous silicon doped with phosphorus is preferably used.

On the insulating substrate 11 along the insulating substrate 11,
At a position spaced a predetermined distance from the gate electrode 13,
A transparent conductive film, that is, an ITO film 19 used as a pixel electrode is arranged. The ITO film, that is, the pixel electrode 19 has, for example, a target pixel pitch of 80 μm.
It is needless to say that it is formed in a shape excluding a portion occupied by the amorphous silicon thin film transistor 12 and a signal line (column selection line) described later from × 240 μm.

On the insulating substrate 11 along the insulating substrate 11,
At a predetermined position in a direction orthogonal to the gate electrode (scanning line) 13, a metal or a semiconductor which is substantially the same as the scanning line, that is, the gate electrode 13 and the storage capacitor electrode 14, or a metal provided with an arbitrary combination, or An electrode portion made of a semiconductor is formed. Hereinafter, the electrode portion will be referred to as a signal line (column selection line) 20. Also, the signal line 2
0 is, for example, Al (aluminum), Ti (titanium)
, Cr (chromium), Mo (molybdenum), Ta (tantalum), W (tungsten), or a single layer or a laminated layer of an alloy thereof.

In the region on the insulating substrate 11 which partially covers the low resistance semiconductor layer 18 of the amorphous silicon thin film transistor 12 and the pixel electrode 19, it is used as a source electrode and a drain electrode of the amorphous silicon thin film transistor 12. Electrode portions (hereinafter, referred to as a source electrode and a drain electrode) 21 and 22 made of a single layer or a laminated layer made of a metal or alloy are formed. In addition, each of the electrodes 21 and 22 is a scanning line, that is, the gate electrode 1.
3 and the signal line 20 are formed of a metal or a semiconductor provided with substantially the same material or an arbitrary combination thereof, for example, Al, Ti, Cr, Mo, Ta or W. Here, the respective electrodes 21 and 22
Is formed by being integrally formed by the same process and then removing the low resistance semiconductor layer 18 between the source electrode 21 and the drain electrode 22 by etching. The source electrode 21, the drain electrode 22, and the inorganic protective film 17
A surface protective layer, that is, a passivation film 23 is disposed on the surface layer side of the exposed portion. Further, on the surface layer side of the passivation film 23, an alignment film 24 on the array substrate 10 side is formed on the entire surface.

On the other hand, the remaining surface of the insulating substrate 11, that is, the surface facing the outside when the array substrate 10 and the counter substrate 30 are assembled, protects the surface of the insulating substrate 11 and passes through the insulating substrate 11. A polarizing plate 25 for matching the characteristics of the wave front of the light is provided integrally with the insulating substrate 11.

The counter substrate 30 has an insulating substrate (support glass) 31 formed of a transparent material such as glass. The insulating substrate 31 is made of substantially the same material as the insulating substrate 11 used for the array substrate 10.
In addition, the one surface of the insulating substrate 31 facing outward when the array substrate 10 and the counter substrate 30 are assembled together protects the surface of the insulating substrate 31 and prevents the wave front of the light passing through the insulating substrate 31. A polarizing plate 32 for matching the characteristics is provided integrally with the insulating substrate 31.

The remaining surface of the insulating substrate 31 is located at a position facing the thin film transistor 12 formed on the array substrate 10 when the thin film transistor 12 is overlapped with the array substrate 10 by the light passing through the insulating substrate 31. In order to prevent the malfunction of the thin film transistor 12,
And a light shielding film 33 that shields light traveling toward the vicinity thereof. The size of the light-shielding film 33 is such that the shadow of the light-shielding film 33 is projected even if the centers of the light-shielding film 33 and the thin film transistor 12 are deviated due to an error when the insulating substrate 10 and the counter substrate 30 are superposed on each other. The size is defined so that the thin film transistor 12 does not come off from the region to be opened.

R (red), G (green) and B (blue) are provided on the surface layer side of the light shielding film 33 (the surface facing the liquid crystal composition 50 when the counter substrate 30 and the array substrate 10 are assembled). The colored resin layers, that is, the color filters 34 colored with the dyes corresponding to the respective colors are arranged.

Surface layer of color filter 34 (counter substrate 3
0 and the array substrate 10 are assembled into a liquid crystal composition 50.
A transparent conductive film, that is, an ITO film 35 used as a counter electrode is arranged on the side facing the surface). An alignment film 36 on the counter substrate 30 side is formed on the entire surface layer of the counter electrode 35 (the surface facing the liquid crystal composition 50 when the counter substrate 30 and the array substrate 10 are assembled).

FIG. 3 is a schematic diagram showing an equivalent circuit corresponding to one pixel in the pixel portion of the array substrate of the active matrix type liquid crystal display device shown in FIGS. As is clear from FIG. 3, the array substrate 10 of the active matrix type liquid crystal display device 1 is formed integrally with the gate electrode 13 of the amorphous silicon thin film transistor 12 that drives each pixel for screen display. A scanning line (row selection line) 13 for applying a row signal to the source electrode 21 and a signal line (column selection line) 20 for applying a column signal to the source electrode 21 of the amorphous silicon thin film transistor 12 are connected to each other. ing. It is well known that the scanning line 13 and the signal line 20 are arranged so as to intersect with each other, and the amorphous silicon thin film transistor 12 is formed at each intersection obtained by the intersection. It goes without saying that the pixel electrode 19 is connected to the drain electrode 21 of the amorphous silicon thin film transistor 12.

Next, the manufacturing process of the liquid crystal display device 2 described above will be briefly described. First, a film of tantalum (Ta) or the like having a predetermined thickness is formed on a predetermined surface of the insulating substrate 11 by a sputtering method, and the film is etched into a predetermined shape by photoetching. In addition, the storage capacitor electrode 14 is formed.

Next, SiOx (silicon oxide) used as the gate insulating film 15 and a-Si (amorphous silicon thin film) 1 used as the gate electrode of the thin film transistor 12 1
6. SiNx (silicon nitride) used as the inorganic protective film 17 is formed at a predetermined position on the gate insulating film 15 by, for example, the plasma CVD method.

Subsequently, the inorganic protective film 17 is shaped in a self-aligning manner with respect to the gate electrode (portion corresponding to the gate electrode) 13. The self-aligning shape processing referred to here corresponds to the gate electrode 13 by exposing the insulating substrate 12 from the back surface side after applying a photosensitive resist film on the inorganic protective film 17, for example. It means that the shape and position of the inorganic protective film 17 are aligned with the gate electrode by using the backside exposure technique that defines the shape. According to this method, the position shift of the inorganic protective film 17 with respect to the gate electrode 13 does not occur in principle, and the same offset amount (ΔW) can be obtained on the source side and the drain side. Further, since ΔW (offset amount) is defined by utilizing the diffraction reduction of the exposure light by the gate electrode 13 at the time of the back surface exposure, in the prior art, in consideration of the problem of the mask alignment accuracy at the time of photoetching, etc. The offset amount that was required to be 4 μm is, for example, 1
It can be made as small as μm and the accuracy is improved. Therefore, the parasitic capacitance (Cgs) of the amorphous silicon thin film can be greatly reduced.

Next, a low resistance semiconductor layer 18 having a predetermined thickness is formed on the surface layer of the inorganic protective film 17 and processed into a predetermined shape by etching. Then, a transparent conductive film, that is, an ITO film used as the pixel electrode 19 is formed to have a predetermined thickness by, for example, a sputtering method, and processed into a predetermined shape by photoetching.

Next, a through hole is formed in the gate insulating film 15 by photoetching to function as a gate electrode of the thin film transistor 12 opposed to the gate electrode 13 with the scanning line (gate electrode) 13 and the gate insulating film 15 interposed therebetween. The amorphous silicon thin film 16 is connected.

Subsequently, a metal or semiconductor layer typified by aluminum (Al) or the like is formed to a predetermined thickness by, for example, a sputtering method, and the signal line 20, the source electrode 21 and the drain electrode 22 are formed by photoetching. Each is processed into a predetermined shape.

Up to this point, the basic part of the array pattern including the amorphous silicon thin film transistor 12 as a switching element is completed. Next, for example, a passivation film 23 made of SiNx (silicon nitride) is formed to a predetermined thickness.

As a result, the array substrate 10 of the liquid crystal display device 1 is completed. Next, on the supporting glass of the counter substrate 30, that is, the insulating substrate 31, a thin film, that is, a light-shielding film 33 typified by a metal such as chromium (Cr) is formed to a predetermined thickness by a sputtering method, and is photoetched. Process into a predetermined shape.

Then, R (red), G (green) and B
A color filter 34 colored with a dye corresponding to each of (blue) is formed. After that, the ITO film 35 as the counter electrode is formed to a predetermined thickness, and the counter substrate 30 is completed.

Hereinafter, the array substrate 10 and the counter substrate 30 will be described.
Alignment films 24 and 36 are arranged on each of the two substrates, and the liquid crystal composition 50 is injected after being bonded at a predetermined interval through a spacer (not shown), and a peripheral drive circuit (not shown) is attached to the liquid crystal display. The device 1 is completed.

As described above, according to the liquid crystal display device and the manufacturing method thereof shown in FIGS. 1 and 2, the invention described in the claims has at least a row selection line (scanning line) on the insulating substrate 11. That is, the gate electrode 13 and the column selection line
(Signal line) 20 is formed, and an amorphous silicon thin film transistor 12 is formed in a region where each selection line intersects. The amorphous silicon thin film transistor includes a gate electrode, a gate insulating film 15, an amorphous silicon thin film 16, The inorganic protective film 17 and the low-resistance semiconductor layer 18, and the source electrode 21 and the drain electrode 24, the source electrode is connected to the pixel electrode 19 made of a transparent electrode, and the pixel electrode is formed of amorphous silicon. In an amorphous silicon thin film transistor array substrate 10 in which a storage capacitor electrode 14 that complements the capacitance characteristics of a thin film transistor is formed so as to overlap a part of a pixel electrode,
The inorganic protective film 17 of the amorphous silicon thin film transistor 12 is
Shaped in a self-aligned manner in relation to the gate electrode 13,
The storage capacitor electrode 14 is provided on the outer peripheral portion of the pixel electrode 19,
Provided is a liquid crystal display device 1 including an amorphous silicon thin film transistor array substrate 10 characterized by being formed along a signal line 20.

In the liquid crystal display device 1, the inorganic protective film 17 is set by the back exposure using the gate electrode 13 so as to correspond to the width of the scanning line 13.
By reducing the width of 3, it is possible to reduce the occurrence of the inorganic protective film 17 having a small parasitic capacitance.

FIG. 4 is an enlarged partial plan view of a pixel portion of an active matrix type liquid crystal display device to which the second embodiment of the present invention is applied. Note that, as can be easily inferred from FIG. 4, the cross sections have substantially the same structure, and therefore are omitted.

The same structures as those shown in FIGS. 1 and 2 are designated by the same reference numerals, detailed description thereof will be omitted, and the features will be described along with the manufacturing process. First
First, a film of tantalum (Ta) or the like is formed to a predetermined thickness on a predetermined surface of the insulating substrate 11 by a sputtering method, and is etched into a predetermined shape by photoetching, and the scanning line and the gate electrode corresponding portion 13 and the storage portion are accumulated. The capacitor electrode 1014 is formed.

At this time, the shape of the storage capacitor electrode 1014 is given a characteristic, and as shown in FIG.
The storage capacitor electrode 1014 connected to 3 is arranged along the periphery of the n-stage pixel region formed in the subsequent step, and
The scanning lines 13 of n stages are formed with a spacing of 100 μm, for example. In this case, the storage capacitor electrode 101
In No. 4, since it is necessary to secure a predetermined storage capacity, a part of the storage capacity electrode 1014 must inevitably protrude into the effective portion of the pixel electrode 19 (the area other than the area covered by the light shielding portion 33). Becomes Therefore, the aperture ratio is
And slightly reduced compared to the first example shown in FIG.

However, according to the shape of the storage capacitor electrode 1014 shown in FIG. 4, the storage capacitor electrode 1014 connected to the (n-1) th scanning line 13 is sufficiently separated from the nth scanning line 13. Since the liquid crystal display device 1000, that is, the array substrate 1010 is manufactured, the yield is significantly improved because the liquid crystal display device 1000, that is, the array substrate 1010 is formed.

Next, SiOx (silicon oxide) used as the gate insulating film 15 and a-Si (amorphous silicon thin film) 1 used as the gate electrode of the thin film transistor 12 1
6. SiNx (silicon nitride) used as the inorganic protective film 17 is formed at a predetermined position on the gate insulating film 15 by, for example, the plasma CVD method.

Then, only the inorganic protective film 17 is scanned with a scanning line.
(Gate electrode) 13 is processed into a predetermined shape by backside exposure. That is, the width (area) of the inorganic protective film 17
Is defined with respect to the width (area) of the scanning line 13 as if the self-alignment (Self Align) method is used, that is, the scanning line 13 is self-aligned. According to this method, the width (area) of the inorganic protective film 17 is set corresponding to the width (area) of the scanning line 13. Therefore, by reducing the width of the scanning line 13, It is possible to reduce the magnitude of the parasitic capacitance that occurs. This makes it possible to control the length (area) of the storage capacitor electrode 14 described above to a predetermined size, which is useful for increasing the closest distance between the scanning line 13 and the storage capacitor electrode 14. Is.

Next, the low resistance semiconductor layer 18 having a predetermined thickness is formed on the surface layer of the inorganic protective film 17, and is processed into a predetermined shape by etching. Then, a transparent conductive film, that is, an ITO film used as the pixel electrode 19 is formed to have a predetermined thickness by, for example, a sputtering method, and processed into a predetermined shape by photoetching.

Next, a through hole is formed in the gate insulating film 15 by photoetching to function as a gate electrode of the thin film transistor 12 opposed to the gate electrode 13 with the scanning line (gate electrode) 13 and the gate insulating film 15 interposed therebetween. The amorphous silicon thin film 16 is connected.

Subsequently, a metal or semiconductor layer typified by aluminum (Al) or the like is formed to have a predetermined thickness by, for example, a sputtering method, and the signal line 20, the source electrode 21, and the drain electrode 22 are photoetched. Each is processed into a predetermined shape.

Up to this point, the basic part of the array pattern including the amorphous silicon thin film transistor 12 as a switching element is completed. Next, for example, a passivation film 23 made of SiNx (silicon nitride) is formed to a predetermined thickness.

As a result, the array substrate 1010 of the liquid crystal display device 1000 is completed. Next, the supporting glass of the counter substrate 30, that is, the insulating substrate 31, is coated with, for example, chromium.
A thin film represented by a metal such as (Cr), that is, a light shielding film 33
Is formed into a predetermined thickness by a sputtering method and processed into a predetermined shape by photoetching.

Then, R (red), G (green) and B
A color filter 34 colored with a dye corresponding to each of (blue) is formed. After that, the ITO film 35 as the counter electrode is formed to a predetermined thickness, and the counter substrate 30 is completed.

Hereinafter, the array substrate 10 and the counter substrate 30 will be described.
Alignment films 24 and 36 are arranged on each of the two substrates, and the liquid crystal composition 50 is injected after being bonded at a predetermined interval through a spacer (not shown), and a peripheral drive circuit (not shown) is attached to the liquid crystal display. The device 1000 is completed.

As described above, according to the liquid crystal display device and the manufacturing method thereof shown in FIG. 4, the invention described in the claims is at least the row selection line, that is, the gate electrode 13 and the column selection on the insulating substrate 11. Line 20 is formed, and the amorphous silicon thin film transistor 1 is formed in a region where each selection line intersects.
2, the amorphous silicon thin film transistor is composed of a gate electrode, a gate insulating film 15, an amorphous silicon thin film 16, an inorganic protective film 17, a low resistance semiconductor layer 18, a source electrode 21 and a drain electrode 24. A pixel electrode 19 made of a transparent electrode is connected to the source electrode, and a storage capacitor electrode 1014 for compensating for the capacitance characteristic of the amorphous silicon thin film transistor is formed on the pixel electrode so as to overlap a part of the pixel electrode. In the crystalline silicon thin film transistor array substrate 1000, the storage capacitor electrode 1014 is formed to have a predetermined shape protruding so as to cover a part of the pixel electrode 19 and a predetermined distance from the scanning line 13 of the adjacent pixel electrode. , Amorphous silicon thin film transistor 12
There is provided a liquid crystal display device 1000 including an amorphous silicon thin film transistor array substrate 1000 in which the inorganic protective film 17 is processed in a self-aligned manner in relation to the gate electrode 13.

That is, according to the pixel structure shown in FIG. 4, although the storage capacitor electrode 1014 shown by hatching protrudes into the opening covered with the light shielding film 33 formed on the counter substrate, that is, the display region, n Since the gap between the scanning line 13 in the first stage and the storage capacitor electrode 1014 in the (n-1) th stage is sufficient, a short circuit between both wirings is less likely to occur. It should be noted that, from the experimental results of the inventors of the present invention in which the distance L between the storage capacitor electrode and the scanning line is changed, for example, when L = 10 μm and L = 20 μm, the short-circuit yield alone is about 20.
% Improvement has been confirmed, and when L = 20 μm and L =
An improvement of about 5% is confirmed in the case of 40 μm. Therefore, in order to achieve a sufficiently high yield, 20
It is considered that the interval L of μm or more is necessary.

In any of the inventions, it is needless to say that various modifications can be made, for example, with respect to the structure of the amorphous silicon thin film transistor, the pixel structure, the manufacturing method, etc. within a range satisfying the constituent requirements of the invention. Absent.

[0063]

As described above in detail, according to the present invention, a plurality of scanning lines and signal lines formed on an insulating substrate, and pixel electrodes arranged in regions where the scanning lines and the signal lines intersect. A gate connected to the scanning line, a drain connected to the signal line, a source connected to the pixel electrode, and a drain and a source overlapped with each other. A thin film transistor having a protective film formed in a self-aligning manner with respect to the gate, and a storage capacitor electrode that is overlapped with the pixel electrode via an interlayer insulating film to form a storage capacitor. An active matrix substrate, the pixel electrode includes a storage capacitor electrode that overlaps the storage capacitor electrode and an effective region other than the storage capacitor electrode, and the storage capacitor region is the signal line of the pixel electrode. 1) Amorphous since a liquid crystal display device and a method for manufacturing the same are provided, wherein the effective regions are formed between parallel storage regions and the effective regions are disposed between storage capacitor regions that are separated from each other. By processing the inorganic protective film in the silicon thin film transistor in a self-aligned manner with respect to the gate electrode,
The required storage capacitance can be halved, and the aperture ratio can be greatly increased by forming the storage capacitance electrode along the signal line on the outer peripheral portion of the pixel electrode.

2) Since the storage capacitance electrode is formed only in the region along the gate electrode, that is, along the signal line spaced from the scanning line, the distance between the storage capacitance electrode and the scanning line and the gate electrode is increased. Therefore, it is possible to eliminate the problem that a short circuit between both electrodes occurs in the manufacturing process. This improves the manufacturing yield of the array substrate.

[Brief description of the drawings]

FIG. 1 is a partially enlarged plan view showing a first embodiment of a pixel portion formed on an array substrate of a liquid crystal display device of the present invention.

FIG. 2 is a partially developed cross-sectional view of a pixel portion of the array substrate shown in FIG.

FIG. 3 is a schematic diagram showing an equivalent circuit corresponding to one pixel in the pixel portion of the array substrate shown in FIGS. 1 and 2.

4 is a partially enlarged plan view showing a second embodiment of a pixel portion formed on the array substrate shown in FIG.

FIG. 5 is a partially enlarged plan view showing one pixel of a pixel portion formed on an array substrate of a general liquid crystal display device.

6 is a partially developed cross-sectional view of a pixel portion of the array substrate shown in FIG.

FIG. 7 is a partially enlarged plan view showing one pixel of a pixel portion formed on an array substrate of a general liquid crystal display device.

[Explanation of symbols]

 1, 1000 ... Liquid crystal display device, 10, 1010 ... Array substrate, 11 ... Insulating substrate (supporting glass) 12 ... Amorphous silicon thin film transistor, 13 ... Scan line (row selection line, gate electrode), 14, 1014 ... Storage Capacitance electrode, 15 ... Gate insulating film (insulating layer), 16 ... Amorphous silicon thin film, 17 ... Inorganic protective film, 18 ... Low resistance semiconductor layer, 19 ... Pixel electrode, 20 ... Signal line (column selection line), 21 ... Source electrode, 22 ... Drain electrode, 23 ... Passivation film, 24, 36 ... Alignment film, 25, 32 ... Polarizing plate, 30 ... Counter substrate, 31 ... Insulating substrate (supporting glass), 33 ... Shading film, 34 ... Color filter, 35 ... Counter electrode, 50 ... Liquid crystal composition.

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Rinko Kitazawa 8 Shinsugita-cho, Isogo-ku, Yokohama-shi, Kanagawa Prefecture Inside the Toshiba Yokohama Office (72) Inventor Tetsuya Iizuka 7-1-1 Nisshincho, Kawasaki-ku, Kawasaki-shi, Kanagawa Shiba Electronics Engineering Co., Ltd.

Claims (7)

[Claims] 1. A plurality of scanning lines and signal lines formed on an insulating substrate, a pixel electrode arranged in an area where the scanning lines and the signal lines intersect, a gate connected to the scanning lines, and the signal. A drain connected to a line, a source connected to the pixel electrode, and a drain disposed between the source and the source, the drain overlapping the source, and self-aligned with the gate. A thin film transistor having a processed protective film, and an active matrix substrate including a storage capacitor electrode that is overlapped with the pixel electrode via an interlayer insulating film to form a storage capacitor, the pixel electrode, The storage capacitor electrode includes a storage capacitor electrode overlapping with the storage capacitor electrode and an effective region other than the storage capacitor electrode, the storage capacitor region being formed at an end portion of the pixel electrode parallel to the signal line, and the effective region. Is disposed between the storage capacitor regions separated from each other. 2. The liquid crystal display device according to claim 1, wherein the scanning line forming the thin film transistor also serves as a gate electrode. 3. The liquid crystal display device according to claim 1, wherein a distance between the storage capacitor electrode and the scanning line or the gate electrode at the closest portion is 20 μm or more. 4. The liquid crystal display device according to claim 3, wherein the closest distance between the storage capacitor electrode and the scanning line or the gate electrode is 100 μm or more. 5. The storage capacitor electrode formed so as to overlap a part of the pixel electrode connected to the scanning line of n stages through the thin film transistor is connected to the scanning line of n−1 stages. The liquid crystal display device according to any one of claims 1 to 4. 6. A plurality of scanning lines and signal lines formed on an insulating substrate, a pixel electrode arranged in an area where the scanning lines and the signal lines intersect, a gate connected to the scanning lines, and the signal. A drain connected to a line, a source connected to the pixel electrode, and a drain disposed between the source and the source, the drain overlapping the source, and self-aligned with the gate. A thin film transistor having a processed protective film, a storage capacitor electrode that is overlapped with the pixel electrode via an interlayer insulating film, and forms a storage capacitor,
A method of manufacturing a liquid crystal display device, comprising: an active matrix substrate comprising: a protective film of the thin film transistor, which is shaped in a self-aligned manner with respect to the gate electrode, and the storage capacitor electrode is formed on an outer peripheral portion of the pixel electrode. A method for manufacturing a liquid crystal display device, which is formed in a portion along the signal line. 7. The inorganic protective film formed in a self-aligned manner with respect to the gate electrode is shaped by backside exposure by exposing from the backside of the insulating substrate using the scanning lines as a resist pattern. The method of manufacturing a liquid crystal display device according to claim 6, wherein the liquid crystal display device is processed.